JPS61251082A - Semiconductor device - Google Patents

Abstract

PURPOSE:To weeken an electric field in the vicinity of the surface and to enlarge the width of a depletion layer by forming the conductor of such width that it projects from the both sides of the width of the guard ring layer surrounding an impurity layer almost equivalently above the guard ring layer through an insulating film. CONSTITUTION:A guard ring layer 40 is formed in the both end positions of a depletion layer formed under the condition that the guard ring layer 40 does not exist. A conductor 50 is made of aluminum or polysilicon and etc. and its width is preset so that is projects from the both sides of the guard ring layer 40 almost equivalently. When a voltage is applied to the conductor 50, a P-type electrode 60, and an N-type electrode 70, a depletion layer 11 expands along the P-N junction part (a) and the electrons included in an insulating film 20 are attracted by the conductor 50, so that the electrons in a semiconductor substrate 10 concentrate in the vicinity of the surface. Because a voltage is excited between the conductor 50 and the semiconductor substrate 10 without bringing the conductor 50 in contact with the guard ring layer 40, the depletion layer 11 has a stable width as shown by the two-dots and dash line.

Description

[Detailed description of the invention] , 1 minute production! The present invention relates to semiconductor devices such as planar high-voltage diodes and transistors, and particularly to a semiconductor device having a structure that stabilizes the width of a depletion layer and is advantageous when increasing the degree of integration.

Conventionally, in semiconductor devices such as planar high-voltage diodes and transistors, a so-called field plate electrode that protrudes outward from a guard ring layer surrounding an impurity layer is contacted to the guard ring layer. In some devices, the electric field at the interface between the semiconductor substrate and the insulating film is weakened by the overhang of the field plate electrode, and the depletion layer is expanded to the overhang.

(゛ ゝ, In this conventional method, in order to bring the field plate electrode into contact with the guard ring layer, a process is required to open a window in the insulating film on the surface of the semiconductor substrate.Moreover, this process requires a margin due to mask alignment. It is necessary to take this into account at the time of design, and it is also necessary to take into account the amount of transverse waves when diffusing the guard ring layer.Based on these factors, semiconductor devices equipped with this type of field plate electrode , which is disadvantageous when increasing the degree of integration.

The present invention has been devised in view of the above circumstances, and aims to provide a semiconductor device in which the width of the depletion layer can be stably obtained, and which is advantageous in increasing the degree of integration.

For this reason, the present invention provides an insulating conductor on top of the guard ring layer with a width that extends approximately evenly from both sides of the guard ring layer surrounding the impurity layer. Formed through a membrane.

A voltage is induced between the plate, that is, the conductor and the semiconductor substrate, thereby weakening the electric field near the surface of the semiconductor substrate, and expanding the depletion layer from the guard ring layer to the conductor overhanging the semiconductor substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described in detail with reference to the drawings. In this embodiment, a planar type high voltage diode 1 shown in FIG. 1 will be explained as an example.

That is, the planar type high voltage diode 1 includes an insulating film 20 made of a silicon oxide film covering the surface of a semiconductor substrate 10 made of N-type silicon, and a P-type impurity layer diffused and formed in a predetermined position of the semiconductor substrate 10. 30, a P-type guard ring layer 40 surrounding the impurity layer 30, and a conductor 50 formed on the surface of the insulating film 20 above the guard ring layer 40.
a P-type electrode 60 in contact with the impurity layer 40;
N-type electrode 70 in contact with the back surface of semiconductor substrate 10
It is equipped with.

Specifically, the guard ring layer 40 is formed at both ends of a depletion layer formed without the guard ring 140. The conductor 50 is made of aluminum, polysilicon, etc., and has a width smaller than that of the guard ring layer 40.
The width is set so that it extends almost equally from both sides.

Here, when a voltage is applied to the conductor 50, the P-type electrode 60, and the N-type electrode 70, the depletion layer 11 along the P-N junction a
spreads, electrons contained in the insulating film 20 are attracted by the conductor 50, and holes contained in the insulating film 20 are pushed toward the surface side of the semiconductor substrate 10.
Electrons within 0 concentrate near the surface.

As a result, the electric field at the interface between the insulating film 20 and the semiconductor substrate 10 is weakened, and the depletion layer 11 spreads to a certain position of the conductor 50. In other words, the conductor 5 is attached to the guard ring N40.
Since a voltage is induced between the conductor 50 and the semiconductor substrate 10 even if the conductor 50 and the semiconductor substrate 10 are not in contact with each other, the depletion layer 11 of the planar high voltage diode 1 having the above structure has a stable width as shown by the two-dot chain line. become. Note that the thickness of the insulating film 2'0 is desirably set to about 1 μm.

Next, a method for manufacturing the planar type high voltage diode 1 having the above structure will be explained with reference to FIG.

(1) After growing the insulating film 20 on the surface of the semiconductor substrate 10, cover the surface of the insulating film 20 other than the portion where the impurity layer 30 and the guard ring Fi 40 are to be formed with a photoresist 80 (see FIG. 2(a)). . Using this photoresist 80 as a mask, P-type impurity ions are implanted (see FIG. 2(b)).

(2) After peeling off the photoresist 80, the ion-implanted semiconductor substrate 10 is heat-treated to diffuse the impurity and form an impurity layer 30 and a guard ring layer 40 (see FIG. 2(C)).

(2) The insulating film 2o on the top of the impurity layer 30 is etched to form a P-type electrode 60 in this part, and a conductor 50 is formed on both sides of the guard ring layer 40 approximately evenly.
is deposited on the surface of the insulating film 20 above the guard ring layer 40 along the guard ring layer 40. Thereafter, the back surface of the semiconductor substrate 10 is lapped to deposit an N-type electrode 70 (see FIG. 2(d)). Note that the impurity layer 30 and the guard ring layer 40 may be formed by solid phase diffusion, vapor phase diffusion, or the like instead of ion implantation.

Furthermore, the present invention is not limited to the above embodiments,
Of course, it can be applied to power transistors, etc., for example.

As detailed above, according to the present invention, a voltage is induced between the conductor and the semiconductor substrate, which weakens the electric field near the surface of the semiconductor substrate and stably widens the width of the depletion layer. be able to. In other words, even if the conductor is not in contact with the guard ring layer, it is possible to obtain the same effect as if the conductor were in contact with the guard ring layer, so the opening of the insulating film, which was conventionally done to bring the guard ring layer and the conductor into contact, can be avoided. The number of processes can be reduced. Therefore, the present invention is advantageous when increasing the degree of integration because it is only necessary to set the transverse wave intensity due to diffusion when forming the guard ring layer at the time of design.

[Brief explanation of the drawing]

FIG. 1 is an explanatory cross-sectional view showing one embodiment of a semiconductor device according to the present invention, and FIG. 2 is an explanatory cross-sectional view for explaining a method of manufacturing the planar high voltage diode 1 shown in FIG. DESCRIPTION OF SYMBOLS 1... Planar type high voltage diode, 10... Semiconductor substrate, 20... Insulating film, 30... Impurity layer, 40
... Guard ring layer, 50... Conductor.

Claims (1)

[Claims] (1) In a semiconductor device in which an impurity layer of one conductivity type is surrounded by a guard ring layer of the same conductivity type as the impurity layer, the width of the guard ring layer is larger than the width of the guard ring layer and extends almost equally from both sides thereof. A semiconductor device characterized in that a conductor is formed on the guard ring layer with an insulating film interposed therebetween.