JPS61248565A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an FET having a high withstanding voltage without increasing a threshold voltage, by isolating the overlapped part of a gate, a source and a drain by an oxide film. CONSTITUTION:A nitride film 217 is applied on a thermal oxide film 215 on an N-type Si substrate 211, and oxidation is performed. Thus an oxide film 219, which has a thickness of about three times the film 215 is formed, and the mask 217 is removed. Then,a poly Si gate electrode 215 is formed by a CVD method. With the electrode 216 as a mask, RIE of the gate oxide film 219 is carried out. P-type impurity diffused layers 213A (source S) and 213B (drain D) are formed. Since the concentration of electrolysis at the time of operation is alleviated by the presence of the thick oxide film 219, the withstanding voltage in the P-N junction is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a MOS type semiconductor device with a high breakdown voltage.

[Conventional technology]

Conventionally known MOS (Metal Oxide Sem
There is a field effect transistor (FET) as a 1 conductor type semiconductor device, and a structure shown in FIG. 4 has been used to provide a high breakdown voltage. Note that this configuration is of the so-called offset gate type, and in this type, the gate (G) region and drain CD)
By separating the regions as much as possible, electric field concentration is prevented. As a result, a transistor with a high breakdown voltage has been realized, and an extremely useful transistor that will not be damaged even under high voltage during use has been provided.

In FIG. 4, a silicon (Si) substrate 411 (N
Impurity diffusion layers 413A and 413B into which impurities having conductivity (P type) opposite to that of the silicon substrate 411 are implanted are formed at regular intervals on the upper surface side of the silicon substrate 411 (type). A gate oxide film 415 covers the impurity diffusion layer 413A, and a metal electrode 417 is formed to overlap with the gate oxide film 415.

The operation of the MOS transistor (n-channel) formed in this way will be examined. Now, the silicon substrate 411 and one impurity diffusion layer 413A (source S) are grounded, and a predetermined voltage (-15V) is applied to the other impurity diffusion layer 413B (drain D). 417
The application of voltage shall be interrupted and continued.

This equivalent circuit is shown in FIG. 5, and the bias voltage EG is supplied to or cut off from the gate G by closing and opening an on/off switch 521.

Depending on whether this voltage Ec is supplied or cut off, the MOS
The transistor is "on" and 1±4 off.

When this MOS transistor is turned off by cutting off the voltage EQ, an electric field is concentrated between the edge of the impurity diffusion layer 413B (drain D) and the gate electrode 417 in the vicinity thereof. As a result, N − formed by the silicon substrate 411 and the impurity diffusion layer 413B (drain D)
The withstand voltage at the P junction will decrease. This results in the disadvantage that it becomes easily damaged.

In order to eliminate such drawbacks, in the configuration shown in FIG. 4, the gate electrode 417 and the impurity diffusion layer 413B corresponding to the drain D are separated so that they do not overlap each other.
The above-mentioned electric field concentration is prevented from occurring between them.

[Problem that the invention seeks to solve]

However, in the conventional offset gate type MOS transistor shown in FIG. 4, if the distance between the impurity diffusion layer 413B corresponding to the drain D and the gate electrode 417 is too small, the withstand voltage will decrease as a result. On the other hand, if the distance is too large, the transistor in question
The threshold for turning on becomes high, and an operational problem arises in that the on state cannot be achieved with a small gate voltage.Therefore, such offset type MO3) transistors are Since the structure is asymmetric, the gate electrode 417 and the impurity diffusion layer 41
It was necessary to take technical measures such as intentionally shifting the superimposed state with 3A and 413B.

This invention was made in order to solve the above-mentioned problems all at once, and the withstand voltage is increased, and the cross-sectional structure of the MOS semiconductor device is symmetrical between the source S and the drain D. Therefore, it is an object of the present invention to provide a semiconductor device in which a gate electrode and a source/drain region can be constructed in a self-aligned manner.

[Means for solving problems]

FIG. 1 shows the configuration of a semiconductor device of the invention related to this patent application.

In FIG. 1, 111 is a semiconductor substrate on which a semiconductor device is to be formed.

113 is a channel region necessary to form a gate.

Impurity diffusion layers 115 and 117 are formed in the semiconductor substrate 111 and serve as sources and drains.

Reference numeral 119 denotes an oxide film formed to cover both impurity diffusion layers 115 and 117 and the channel region.

Reference numeral 121 denotes a gate electrode formed overlappingly on the oxide film 119.

With this configuration, a semiconductor device having an overall structure including a gate, a source, and a drain is formed.

[Effect]

In the semiconductor device according to the present invention, an oxide film is interposed between the gate and the source and drain.

In particular, the portion of the oxide film covering the source and drain is made thicker than the portion covering the channel region between the source and drain.

The presence of this oxide film prevents electric field concentration and increases the breakdown voltage, resulting in a high breakdown voltage semiconductor device.

[Embodiments of the invention]

An embodiment of the present invention will be described below based on the drawings.

Figures 2(a) to 2(d) show an embodiment of the present invention, where 211 is a silicon (Si) substrate, 213A and 213B are conductive (P type) opposite to that of the substrate 211. The impurity diffusion layer 215 and the gate oxide film 216 are gate (G) electrodes.

The manufacturing method of the embodiment of the present invention will be explained in the order shown in FIGS. 2(a) to 2(d).

First, as shown in Figure (a), 1. A thermal oxide film corresponding to the gate oxide film 215 is formed on the silicon substrate 211, and a nitride film 217 is further deposited by the CVD method, and etched so that only the corresponding portion of the nitride film 217 remains in the channel region of the gate G. are doing.

Next, as shown in FIG. 2(b), another gate oxide film 219 having a thickness about three times the thickness of the gate oxide 111215 is formed by selective oxidation.

Here, the nitride 1fi 217 is removed, and then polysilicon that will become the gate electrode is deposited by CVD. Then, as shown in FIG. 2(C), a thin gate oxide film 21
Polysilicon is etched to cover area 5.

Furthermore, as shown in FIG. 2(d), the thick gate oxide film 219 is anisotropically etched using polysilicon as a mask, and then a conductive layer opposite to that of the silicon substrate 211 is etched by diffusion or ion implantation. (P-type) impurity is implanted to form impurity diffusion layers 213A and 213B.
form.

In a MOS transistor (n-channel) manufactured with such a structure, the gate electrode 216
The thickness of the gate oxide film 219 interposed in the overlapping portion of the gate electrode and the impurity diffusion layer 213B on the drain D side is thicker, thereby alleviating electric field concentration during operation. Therefore, a decrease in breakdown voltage at the PN junction is prevented.

Two impurity diffusion layers 2 formed on a silicon substrate 211
Looking at the gate oxide film 219 and gate electrode 216- covering 13A and 213B, the structure can be said to be symmetrical. Therefore, these impurity diffusion layers 213A and 21
It is possible to freely select which of the 3Bs to be used as the source or the drain.

Therefore, it is convenient to aim for the symmetry of the source Φ drain and to consider the design layout of an IC or the like forming this MOS transistor.

By the way, in the conventionally known offset type MoS transistor, the parasitic capacitance caused by overlapping gate electrodes (see FIG. 4) on the source side cannot be ignored due to its electrical characteristics. In the embodiment of the present invention, the source and drain regions 213A and 213B and the gate electrode 21, which are thought to cause parasitic capacitance, are
6, a thick gate oxide film 219 is formed interposed therebetween. Due to this, in the case of the present MOS transistor, the parasitic capacitance between these electrodes can be minimized. Therefore, access time can be reduced in a circuit equipped with this MOS transistor.

3(a) and (b) show another embodiment of the present invention,
In the above semiconductor device shown in FIGS. 2(a) to 2(d), a method was adopted in which a thin gate oxide film 215 was formed and a thick gate oxide fi 219 was formed by selective oxidation. On the other hand, in the semiconductor device shown in FIGS. 3(a) and 3(b), a thick gate oxide film is formed and then a thin gate oxide film is formed to have two gate film thicknesses. There is.

That is, as shown in FIG. 3(a), first, thick gate oxide films 313A and 313B are formed on a silicon substrate 311. Also, a portion 31 that should become a desired thin gate region
Etch 5.

Next, as shown in FIG. 3(b), a thin gate oxide film 317 is formed in the area 315 removed by etching. As a result, two gate oxide films 313A having mutually different thicknesses are formed.

B and 317. Further, a metal gate electrode 319 is provided to cover both gate oxide films 313A, B and 317.

At the same time, the silicon substrate 311 has a certain predetermined interval (
A P-type impurity diffusion layer 32LA, with a channel region in place,
B is formed in the same manner as in FIG. One of these impurity diffusion layers 321A is the source S, and the other impurity diffusion layer 321A is the source S.
321B becomes the drain D.

In this way, a MOS transistor having gate oxide films 313A, B and 317 having two different thicknesses is constructed.

By the way, if the source and drain of a MOS transistor can be specified in advance, the gate oxide film 313 only on the drain side can be used instead of having a symmetrical structure as shown in FIG. 3(b).
Only B may be made thicker. As a result, the overlapping portion of the gate electrode 319 and the source/drain region, which is an impurity diffusion layer, is covered with a thick oxide film 313, especially on the drain side.
B will intervene. As a result, the degree of electric field concentration can be handled simply by controlling the oxide film thickness, and a high-voltage MOS transistor can be formed with high precision.

The structure described above does not increase the threshold voltage required to turn the MOS transistor into the "on" state.

Although the above-mentioned embodiment has been described as an n-channel FET, it goes without saying that a p-channel FET can be similarly constructed by reversing the conductivity types of the semiconductor substrate and impurities.

〔Effect of the invention〕

As detailed above, according to the present invention, since the overlapping portion of the gate and the source/drain is separated by an oxide film, it is possible to realize a semiconductor device that has a high breakdown voltage and does not increase the operating threshold voltage. .

[Brief explanation of drawings]

Figure 1 is a diagram showing the structure of the invention related to the patent application; Figure 2 (
a) to (d) are cross-sectional views for explaining the manufacturing order of a semiconductor device according to an embodiment of the present invention, and FIGS.
b) is a structural sectional view for explaining another embodiment of the present invention;
FIG. 4 is a sectional view showing the structure of a conventional MOS transistor, and FIG. 5 is a diagram showing an equivalent circuit during operation of the MOS transistor shown in FIG. Here, in FIGS. 1 to 5, 111 is a semiconductor substrate, 113 is a channel region, 115, 117, 213A,
213B, 313A, 313B. 413A and 413B are impurity diffusion layers, 119 is an oxide film,
121, 216, 319 are gate electrodes, 211.311
are silicon substrates, 215, 219° 313A, 313B
, 317 and 415 are gate oxide films.

Claims (1)

[Claims] 1) a semiconductor substrate, first and second impurity diffusion layers formed on one surface side of the semiconductor substrate with a channel region separated therefrom, and a semiconductor substrate so as to cover the channel region and both impurity diffusion layers; A semiconductor device comprising an oxide film formed and a gate electrode formed over the oxide film, the first and second impurity diffusion layers serving as a source and a drain. . 2) The semiconductor device according to claim 1, wherein the oxide film has a portion that covers the second impurity diffusion layer serving as the drain thicker than a portion that covers the channel region.