JPS6124850B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention uses a simple circuit configuration to enable audio
Convert ADPCM code to normal PCM code
Regarding ADPCM regenerator. ADPCM is used as an audio band compression method.
(Adaptive Differential Pulse Code
Modulation). This method uses the data between adjacent audio samples (time T ₁ and time T ₂ ) to
By taking the difference between the predicted value calculated at T ₁ and the audio signal at T ₂ and encoding it into an ADPCM code, the audio is compressed, and then the code is decoded. By obtaining the quantized value of the difference signal and adding the values sequentially, the normal
This is a method for reproducing audio in PCM code format. Another feature is that the quantization width required to obtain the quantized value of the difference signal is changed according to the ADPCM code. FIG. 1 shows a conventional ADPCM regenerator. In Figure 1, 1 is an input terminal, 2 is an adder, 3 is a multiplier, 4 is an adder, 5 is a register, and 6
is a table that converts the ADPCM code L _o into a quantization step size movement coefficient M _{o and} outputs it. 7
is a multiplier, 8 is a limiter, 9 is a register, and 10 is a
This is an output terminal for the PCM code, and is a terminal for connecting to a DA converter for converting a digital audio signal to an analog audio signal. Let the ADPCM code of the audio from input terminal 1 be _Lo . L _o is added by adder 2 by 0.5 for bias. The result is multiplied by the output Δ _o of register 9 by multiplier 3 . register 9
The output Δ _o is called the quantization step size. When the output of the multiplier 3 is q _o , q _o is the differential demodulation value reproduced by the ADPCM code L _o , and is given by equation (1). q _o = Δ _o・(L _o +1/2) ......(1) The differential demodulated value q _o of multiplier 3 is added to the output x^ _o of register 5, and the result x^ _o+1 is sent to register 5. Stored. This 〓〓, x^ _o+1 is the PCM code of the voice. On the other hand, the ADPCM code L _o of the input terminal 1 is converted by the table 6, and a movement coefficient M _o is output. Table 6 is a table for obtaining the output M _o for the ADPCM code L _o . The output M _o of table 6 is multiplied by Δ _o by multiplier 7 to obtain Δ _o+1 . Δ _o+1 =Δ _{o ·} Mo (2) Δ _o+1 in equation (2) is limited by the limiter 8 between the minimum value Δ _nio and the maximum value Δ _nax . That is, when Δ _o+1 becomes smaller than Δ _nio , the limiter 8 outputs Δ _nio , and when it becomes larger than Δ _nax , it outputs Δ _nax . Output Δ _o of limiter 8
₊₁ is the quantization step size for the next sample. Δ′ _o+1 is stored in register 9. As described above, the block diagram of FIG. 1 operates. In the process according to the configuration shown in FIG. 1, the amount of calculation required is one multiplication each by multiplier 3 and multiplier 7, and one addition each by adder 2 and adder 4. It is necessary to perform the above-mentioned calculation every short time interval (for example, 125 μsec) when an audio ADPCM code is input from the input terminal 1. This requires high-speed logic elements, especially multiplication circuits, and the arithmetic circuit itself becomes large-scale. An object of the present invention is to replace the multiplication in equation (2) with a simple operation on the memory storing the quantization step size, in order to eliminate these drawbacks. As a result, it has become possible to realize a simple circuit configuration using low-speed elements, which will be described in detail below. FIG. 2 shows a first embodiment of the present invention. 50,
51, 52, 53 are the input terminals of the ADPCM code to be sent, 50 is the polarity bit, and 51 is the ADPCM code.
5 of the most significant bits of the amplitude bits of the code
2 is the second input terminal, and 53 is the least significant bit input terminal. 54 is a serial input of register 58. 55, 56, 57, and 58 are 1-bit registers for storing ADPCM codes. Registers 56-58 have a shift function. 59 is read-only memory (hereinafter referred to as ROM),
The output of register 56 is the highest address, the output of register 57 is the second address, register 58
The output of is the third address (the lowest address)
and outputs the pointer movement amount D _o . Reference numeral 60 is a 6-bit output pointer that changes the output P _o according to the output D _o of the ROM 59 . A pointer monitoring unit 61 limits the output P _o of the pointer 60 to a specific range. 62 is a ROM, and the output P _o of the pointer 60
Outputs 16-bit data X using as the address. This X is an amount corresponding to the quantization step size, and in this example is a reference value corresponding to the amount of demodulation of the most significant bit of the amplitude bit. Reference numeral 63 is a 16-bit shift register, which has the function of processing the output of the ROM 62 and shifting down. 64
is composed of 16 E _x -OR gates, and the input of each E _x -OR gate is commonly connected to register 5.
It is connected to the output of 5. Therefore, when the output of register 55 is 1, the output bit of shift register 63 is inverted and output to adder 65. The output of shift register 55 is 0
In this case, the output bits of the shift register 63 are output to the adder 65 as they are. A 16-bit adder 65 adds the output of the Ex _- OR gate 64 and the output of the register 66. The result is stored in register 66 only when the output of register 56 is 1. 66 is a 16-bit register. 67 is 16
This is a bit register. 68 is an output terminal of the register 67. Next, the operation of the first embodiment will be explained. 4 bits from input terminals 50, 51, 52, 53
The ADPCM codes are stored in register 55, register 56, register 57, and register 58, respectively. Table 1 shows the relationship between each register pattern and L _o . At the same time as these data are stored,
The output X of the ROM 62 is stored in the shift register 63. Based on the output bit patterns of register 55, register 56, register 57, and register 58, adder 65 performs the operations shown in Table 1. This operation corresponds to equation (1). This calculation method will be shown below. However, in Table 1, * indicates the value of the register 66 before calculation.

[Table] First, the calculation section will be explained. Register 55, register 56, register 57, stored from input terminals 50, 51, 52, 53,
Out of the ADPCM code L _o of the register 58 , the output of the register 55 controls the output of the shift register 63 through the _Ex -OR gate 64 and also controls the adder 65 . The details of the control are shown in Table 2.

[Table] That is, the output of the register 55 is a control signal for operating the adder 65 as shown in Table 3.

[Step 1]

The amplitude bits of input terminals 51 to 53 are stored in register 5.
6. When stored in the registers 57 and 58, the output X of the ROM 62 is stored in the shift register 63.
is stored. This point is called step 1. When the output of the register 56 is 1, the output X of the shift register 63 is used as a reference amount, and the calculation is performed according to Table 3, and the result is stored in the register 66. If the output of register 56 is 0, the calculation is performed according to Table 3, but the result is not stored in register 66. Therefore, the contents of register 66 at this time have not changed. [Step 2] Next, the output of register 57 is sent to register 56, the output of register 58 is sent to register 57, and the output of register 58 is sent to register 57.
8 stores 1 from the input terminal 54, respectively. This point is called step 2. At this time, the output of the shift register 63 is simultaneously shifted down to become X/2. This value corresponds to 2Δ _o and is a reference amount corresponding to the demodulation amount of the second digit of the amplitude bit. In step 2, when the output of the register 56 is 1, an operation is performed according to Table 3 based on the output X/2 of the shift register 63, and the result is stored in the register 66. If the output of register 56 is 0, the third operation is performed, but the result is not stored in register 66. Therefore, the contents of register 66 do not change. [Step 3] Next, the register 56 receives the output of the register 57,
The output of the register 58 is stored in the register 57, and 0 from the input terminal 54 is stored in the register 58. Further, the output of the shift register 63 is shifted down to become X/4. This value corresponds to Δ _o and is a reference amount corresponding to the least significant digit of the amplitude bit. This point is called step 3. Step 3
In the case where the output of the register 56 is 1, the calculation is performed according to Table 3 based on the output X/4 of the shift register 63 and stored in the register 66. When the output of register 56 is 0, the operation according to Table 3 is performed, but the result is not stored in register 66, so the contents of register 66 do not change. [Step 4] Next, the register 57 is stored in the register 56, the output of the register 58 is stored in the register 57, and the 0 input from the input terminal 54 is stored in the register 58. The contents of the shift register 63 are shifted down to
It becomes 8. This value corresponds to Δ _o /2, which is half the quantization step size. This point is called step 4. In step 4, register 5
The output of 6 is always 1, which is calculated based on the output X/8 of shift register 63 according to Table 3, and stored in register 66. After this calculation is completed, the contents of register 66 are stored in register 67 and output from output terminal 68. Through the above process, input terminals 50, 51, 5
By ADPCM code from 2,53, register 6
At 6, calculations according to Table 1 are performed. The outputs of register 66, register 67, register 68, and register 63 at each step are shown in Table 4 for easy understanding.

[Step 5]

In step 5, it is expressed by equation (2). Δ _o+1 = Δ _o ·M _o ......The operation of (3) is executed without performing multiplication. The principle will be explained. In equation (2), M _o and Δ _o are transformed as follows. M _o =A ^Dn (4) Δ _o =Δ _nio ·A ^Pn (5) However, A and A _nio are positive constants, and D _o and P _o are integers. Then, according to equation (3), it is expressed as Δ _o+1 = Δ _nio・A ^Pn+Dn ......(6) Since P _o and D _o are integers, P _o+1 = P _o + D _o ... ...(7) is also an integer, and equation (6) becomes Δ _o+1 = Δ _nio・A ^Pn+1 ......(8), and Δ _o+1 can also be expressed in the same form as Δ _o . can. Also, the maximum value Δ _n of the quantization step size Δ _{o+1
The ax} and the minimum value Δ _nio are also expressed in the same form. Δ _nio = Δ _nio・A ⁰ ………(9) Δ _nax = Δ _nio・A ^Pmax ………(10) From formulas (8), (9), and (10), P _o+1 is 0 _.about.Pnax , Δ _o+1 in equation (8) is limited to a value within the range of _Δnio to _Δnax . Therefore, if the value of _Δnio・A ^Pn is calculated in advance for an integer in the range of 0 to P _nax , stored in memory, and P _o is used as a pointer output (address of a storage element), (7 ) can determine the quantization step size Δ _o+1 without performing the multiplication in equation (2). D _o in equation (7) is a value corresponding to the audio compression code L _o , similar to the quantization step size movement coefficient M _o , and is herein referred to as the pointer movement amount, and its values are shown in Table 5.

[Table] ADPCM shown in Table 5 by ROM59
The pointer movement amount D _o is converted from the code L _o .
Further, P _o is the output of the pointer 60, and the calculation of equation (7) is executed by counting up or down by the pointer movement amount D _o . Furthermore, the pointer monitoring unit 61 limits the output of the pointer 60 to a range of 0 to P _nax . Pointer 6 restricted by pointer monitoring unit 61
The output of 0 becomes the address input of the ROM62.
In the ROM 62, the quantization step size Δ _nio A ⁰ to _{Δ nio} A ^Pma is set using the pointer output P _o+1 as an address.
Values up to ^x are stored. However, due to the calculation process, a value four times as large as the above (demodulator for the most significant amplitude bit in the ADPCM code) is actually stored. The contents are shown in Table 6.

【table】

[Table] As described above, the operations from step 1 to step 5 are performed every time an ADPCM code is input from input terminals 50 to 53. Note that in this embodiment, the 1-bit register 56
Since the contents of ~58 change for each step,
While the amplitude bits of the ADPCM code are stored in the registers 56 to 58 in the ROM 59,
Either provide a latch circuit that captures the ADPCM code, or
Or in the first step, the output of ROM62
It is preferable to execute the fifth step immediately after storing the data into the shift register 63. As explained above, the operations performed in this embodiment include one addition in step 1, one addition in step 2, one addition in step 3, and one addition in step 4.
There are only four additions in total, which greatly simplifies the calculation. Note that the same structure can be used even when the code is not a 4-bit ADPCM code. For example, in the case of a 3-bit ADPCM code, the register 57 is omitted and the code stored in the ROM 62 is changed to _2∆o , which is twice the quantization step size. It can be composed of

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 50, 51, 52, 53...Input terminal (1 bit each), 54...Register 58 serial input, 5
5, 56, 57, 58...Register (1 bit each), 59...ROM (address 3 bits, output 5
bit), 60...Pointer (output 6 bits), 6
1... Pointer monitoring unit, 62... ROM (address 6 bits, output 16 bits), 63... Shift register (16 bits), 64... Ex _- OR gates (16 pieces), 65... Adder ( 16 bit), 66...
Register (16 bits), 67...Register (16 bits), 68...Output terminal (12 bits), D _o ...
Pointer movement amount, Δ _o , Δ _o+1 ... Quantization step size, P _o ... Pointer output, L _o ... ADPCM
Sign, X...Quantity corresponding to the quantization step size.

Claims (1)

[Claims] 1. In an ADPCM regenerator that inputs an ADPCM code including polarity bits and amplitude bits and outputs a PCM code, the first memory 62 stores amounts corresponding to a plurality of predetermined quantization step sizes. , a pointer 60 that specifies the address of the first memory and outputs one of the quantities corresponding to the quantization step size from the first memory;
A second memory 5 that stores the pointer movement amount and moves the pointer output according to the ADPCM code.
9 and the output of the first memory as input.
A first register 63 that can output a reference value corresponding to each digit of the amplitude bit in the ADPCM code, and
a second register that can store the PCM code;
An ADPCM regenerator comprising an arithmetic control means that generates a current PCM code by taking the sum or difference between the immediately preceding PCM code and the reference amount corresponding to each digit according to the polarity bit of the ADPCM code and each digit of the amplitude bit. .