JPS61248468A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a shielded gate electrode free from a step cut by a method wherein the bottom part of the shielded gate region reaches the position in a silicon wafer deeper than the first main electrode region. CONSTITUTION:After an N<-> type layer 2 is formed on an N<+> type Si substrate 1, an oxide film 3 is formed. A photoresist PR is formed and the film 3 is etched by an RIE method and further the N<-> type layer 2 is etched. Holes formed in the N<-> type layer 2 are deeper than an N-type source region formed in the upper part of the N<-> type layer 2. After the photoresist is removed, oxide films 4 are formed on the inside walls and bottoms of the holes and the oxide films formed on the bottoms of the holes are removed. Doped polycrystalline Si 5 is deposited over the whole surface and the polycrystalline Si 5 on the oxide film 3 is removed. The polycrystalline Si 5 in the holes is also etched and removed until the surface of the Si 5 comes to the same level as the surface of the N<-> type layer 2. Ions are implanted in the part of the N<-> type layer 2 where a control gate region is to be formed utilizing the photoresist PR as a mask. After annealing, a P-type shielded gate region 6 and a P-type control gate region 7 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to solid-state imaging devices. More specifically, the present invention relates to a solid-state imaging device comprising a single static induction transistor or a plurality of static induction transistors (hereinafter abbreviated as rSIT J) arranged in an array.

Conventional technology and problems Recently, a single SI that has both photodetection and switching functions has been developed.
A solid-state imaging device in which a pixel was constructed with
(Japanese patent application), etc. Furthermore, the drawbacks of the SIT constituting this solid-state imaging device have been resolved, and the shielding gate (W castle) has a sufficient pixel function.
Therefore, a new solid-state imaging device was proposed in order to provide a solid-state imaging device with a structure that is unlikely to cause mutual interference between each SI↑vixel and blooming development (Japanese Patent Laid-Open No. 59-108372
(see publication).

FIG. 1 is a sectional view of Sl and T that constitute this fixed imaging device. As shown in Figure 1, n+9 S + with low resistance
A high-resistance n-type epitaxial layer 2 is formed on a substrate 1, and a P+-type control gate region 4 is formed on the surface of the n-type epitaxial layer 2 so that the upper surface thereof is located at the surface of the n-type epitaxial layer 2. It is formed to be on the same level as. Further, a p-type shielding gate region 5 is formed in the surface portion of the n″″-type epitaxial layer 2 so as to surround the above-mentioned P+ type control gate region 4.

This type shielding gate region 5 is formed so that its upper surface is at a lower level than the surface of the n-type epitaxial layer 2, and an oxide film 6 is formed thereon. Note that the impurity density of the control gate region 4 and P+
The impurity density does not necessarily have to be the same as that of the P+ type shielding gate region 5. For example, the photosensitivity of the SIT can be increased by making the impurity density of the P+ type shielding gate region 5 higher than the impurity density of the P+ gate region 4. can.

Furthermore, there is an n
A + type drain region 3 is formed. This n" type drain region 3 is formed so that its upper surface is at the same level as the surface of the n- type epitaxial layer 2. That is, compared to this n+ type drain region 3, the P+ type shielding gate region 5 is n It is formed deep within the - type epitaxial layer 2, and such structural strength (which is a feature of this SIT solid-state imaging device) is formed deep within the - type epitaxial layer 2. The n+ drain region 3 is formed at two positions so that the distance to the P1 type control gate region and the distance to the P+ type shielding gate region 5 are equal (that is, at the midpoint of the bidirectional region). is the P11 type control gate region 4 surrounding it
It is preferable that at least one is formed at a position shallower than the formation position of the upper type shield gate region 5 in the n- type epitaxial layer 2 between the ffi shield gate region 5 and the P+ type control gate region 4 and the P+ The positional relationship with the mold shielding gate region 5 in the lateral direction (direction perpendicular to the depth direction of the epitaxial calendar 2) is also arbitrary.

A drain electrode 8 made of a first conductive material such as polycrystalline Si (DOPO9) doped with p or the like is formed above the n+ type drain region 3, and an n++ Si substrate 1 is formed opposite to this drain electrode 8. A source electrode 10 made of a metal such as An is formed over the entire surface of the (n1 type source region). Si-N? A transparent control gate electrode 9 made of a second conductive material such as 5N02 is formed via a gate capacitor 7 made of a film 12 of a second insulating material such as. The field part and the p-type shielding gate a region 5 are covered with III oxide 8, and this oxide film 6 and the drain electrode 8 on the n÷-type drain region 3 are covered with a first oxide film such as phosphosilicate glass.
It is coated with a calendar 11 of insulating material.

Reference numeral 13 denotes a shielding gate electrode made of a metal material such as A-shaped and connected to a part of the elbow-shaped shielding gate region 5. This shield gate electrode 13 is a second insulating material film 12 on the double-shaped shield gate region 5 . first layer of insulating material 11 and oxidized N
Pry 6 - #1. It is formed by filling a metal material such as Al using an electron beam method or a sputtering method into a contact hole that has been left unused.
It is not necessary to provide one for each T, and the number and installation location can be determined as appropriate by taking into account the number of SITs constituting the entire solid-state imaging device, the resistance value of the P+ type shielding gate region 5, etc.

14 is A that covers the 24″ type shielding gate area and blocks light.
This is a light shielding film made of a metal material such as n, and suppresses the generation of unnecessary electron/hole pairs in the vicinity of the desired region of the P+ type shielding gate. Note that this light shielding film 14 is formed at the same time as the shielding gate electrode 13, and is therefore integrated therewith.

The SIT constituting the solid-state imaging device described above is formed with the p-type shielding gate region 5 buried in the n-type epitaxial layer 2.

Its electrical vixel separation function is significantly higher than that of the shield gate region of conventional SITs. Therefore, solid-state imaging devices configured by SITs with this structure are free from mutual interference and blooming phenomena between each SIT vixel. is less likely to occur.

In addition, in the SIT constituting this solid-state imaging device, the P+ type shielding gate region 5 is buried deeper in the n- type epitaxial region 2 than the n+ type drain region 3, so it is different from the previous one. Compared to SIT, the degree of isolation between the n+ type drain region 3 and the P+ type gate region 5 is significantly higher.

Therefore, in this solid-state imaging device, even if the n+ type drain region 3 is moved laterally toward the P+ type shielding gate region 5 side in order to increase the photosensitivity of the SIT, the junction capacitance between the blue regions can be kept at a relatively small value. -, and short circuits between blue regions due to misalignment during manufacturing are less likely to occur.

Such an effect is enhanced as the P+ type shielding gate region 5 is formed deeper within the n- type epitaxial layer 2, but if the formation location is too deep, the n
Isolation from the + type St substrate 1 (n++ source region) becomes a problem.

Therefore, in general, the P+ type shield gate region 5 needs to be formed at least IIL11 shallower than the n+ type source region l.

However, in the solid-state imaging device as described above,
There are the following problems. That is, during the manufacturing process, as shown in FIG. 2(a), the PSG film 15. Second insulating material film 12. The first insulating material 11 and the oxide films 6 and 6' are removed to form a contact hole CH, and then as shown in FIG. 2(b).
0~ by electron beam or sputtering method as shown in
A layer containing 10% Si is 0.5 to 2. Op,
The film is deposited to a thickness of m over the entire surface, and then the excess A pattern layer portion is removed to form a shield gate electrode 13 as shown in FIG. However, if we pay attention to the contact hole CH at this time, we see that the shield gate region 5 is made to reach a deep position of the n-type epitaxial layer 2, so that a deep contact hole CH is formed. Furthermore, when miniaturizing the SIT, the width of the shielding gate region 5 may be increased by, for example, 2.
The diameter of the contact hole (J) must also be made small.On the other hand, A9.
has a characteristic of poor step coverage, and therefore it is difficult to fill such a deep and narrow contact hole 0M with An. In addition, as shown in FIG. 3, a nearly right-angled step A is formed in the upper part of the contact hole CH.
M has a characteristic that so-called step coverage is not good. Therefore, in addition to the above-mentioned filling difficulty, as shown in FIG. 3, the An shielding gate electrode 13 is likely to be separated at the step A at the upper part of the contact hole OH. It becomes the cause.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and provide a solid-state imaging device having a shielding gate electrode with no step breaks.

Structure of the Invention The present invention provides a control gate region formed on a first main surface side of a silicon wafer, and a shielding gate region formed on the first main surface side of the silicon wafer so as to surround the control gate region. , of the silicon wafer between the control gate region and the shield gate region! at least one first main electrode region formed on the main surface side of the silicon wafer; and a second main electrode region formed on the second main surface side of the silicon wafer opposite to the first main electrode region. In a solid-state imaging device comprising a vertical electrostatic induction transistor including an electrode region, the bottom of the shielding gate region reaches a deeper position within the silicon wafer than the first main electrode region, and the bottom of the shielding gate region The region is characterized in that it is connected to the shield gate electrode via a semiconductor layer doped with impurities.

Embodiments of the Invention [First Embodiment] FIGS. 4(a) to 4(Cr) are cross-sectional views showing the manufacturing process of an embodiment of the solid-state imaging device according to the present invention.

Below, the explanation will be made by dividing it into items with the same reference numerals corresponding to each figure in FIG. 4.

(a); Impurity density is 10"10"am-' c7
) Prepare an n medium-sized SJ substrate 1. As a dopant for this n+ type Si substrate l, sb, p, etc. can be used, but it is preferable to use sb, which has a small diffusion coefficient.
“Impurity density 10 to 10 am− on the type St substrate 1
After forming n-calendar 2 with a thickness of about 5 to 10 JLm by epitaxial method, the wafer is left in an oxygen atmosphere at 900 to 1000°C for 25 to 60 minutes to form a film with a thickness of 10 JLm.
0 to 500 pad oxide films 3 of 5i02 are formed.

(b) A photoresist PR is formed in a portion other than the portion where the shielding gate region is to be formed by mask alignment using two photolithography.

(C) Second, the oxide film 3 in the portion where the shield gate region is to be formed is etched by the RIE method (gas used: CF4/H2), and the n52 layer underneath is etched by RIE perpendicular to the surface.
Etching is performed by E method (gas used: CC, 3F/Ch). The hole formed in the n' layer 2 by this etching is made deeper than the n-type source region formed on the n' layer (example: 1.0 to 5.0 l layer), as will be described later.

(d): Kl H4% -) Iy (II I!' 2j Cl in dry oxygen at 1000°C after photoresist removal)
Bottom E 10003-2000 Xf) Form oxide film 4.

(8) Etch the oxide film formed at the bottom of the second hole by the RIE method. In this case, the oxide film 3 on the side wall portion, which has a thicker V-type property, remains as it is.

(f): Polycrystalline 5i doped with B in the hole and on the entire surface of the oxide film 3 (Poly Si H, hereinafter referred to as P-S
i) 5 is deposited by the CVD method.

Since P-9i has good step coverage, the holes are reliably filled.

(g): P-9i 5 on the oxide film 3 is removed by RIE method or wet etching, and P-9i in the hole is removed.
-5i 5 is also removed by etching until the surface of the remaining P-9i 5 is flush with the surface of n1 layer 2.

(h): A photoresist (PR) is formed on the oxide film a other than the portion where the control gate region is planned to be formed by mask alignment, and using this photoresist PR as a mask, the P-
B is ion-implanted into the n-layer 21 in the portion where the control gate region is to be formed therebelow through the 9i 5 and the oxide film 3 (doga amount: 1X1O to 2X10).

(i): Remove photoresist PR and heat to 1000℃~1
A p-type shielding gate region 8 made of a p-diffused layer is formed at the bottom of the P-9i (B-doped) 5 filled in the hole by leaving it in an oxidizing atmosphere at 100° C. for 60 to 80 minutes, and p-type control is performed. A gate region 7 is formed. Note that during this thermal oxidation, an oxide film (SiOz) is formed on the surface of the P-3i 5 in the hole.

(j): Using a photoresist, the oxide film 3 on the portion where the source region is to be formed is removed by etching according to a pattern formed by mask alignment to form an opening.

(k): P-Si 8 for forming a source electrode is deposited on the entire surface of the oxide film 3 and in the opening, and A
s ion implantation (dose amount: 10" to 10" cm
-Li.

(1): Using a photoresist, excess P-Si 8 is etched away using a pattern formed by mask alignment to form a source electrode 8A.

(, ): An nfi source region 9 made of an n+ diffusion layer is formed in the n layer 2 directly under the source electrode 8A by leaving it in an oxidizing atmosphere at 900 to 1100°C. This n-type source region 9
The depth is 0.1-Q, 5 p-ra. At this time, the source electrode 8A is covered with an oxide film portion.

(n): Applying photolithography, a photoresistor PR is formed on a portion other than a portion of the control gate region 7 by mask alignment, and using this as a mask, oxide film scratches on a portion of the same region 7 are etched away. to form a control gate opening.

(0): The entire surface is covered with the film 11 of the second insulating material. This film 11 of second insulating material forms a capacitor at the control gate 7. As an insulating material, S i3 N 4 + A fL is used. Although it is possible to use AmiN, etc., the film, which has a high dielectric constant and is of good quality at a low temperature, is formed to a thickness of 50 to 1000 by the CVD method using SiH, /NH3 at 400 to 700°C. .

(p): After coating the entire surface with a layer of second conductive material,
By mask alignment, the portion of the second conductive material other than the portion (capacitor 7) existing on the control gate region 7 is removed by etching, thereby removing the film 11 of the second insulating material in the portion of the control gate region 7. A control gate electrode 12 is formed thereon. Since the control gate electrode 12 is provided on the control gate region 7 which is the light receiving section, it is desirable that the control gate electrode 12 be as transparent as possible, and its thickness is generally 2000 mm.
~5000 people. The conductive material constituting the control gate electrode 12 is SnO□ doped with sb and polycrystalline Si.

In2O3, Ta205, An, etc. can be used, but it is particularly preferable to use sb-doped 5n02 or polycrystalline Si. When using sb-doped SnO□ as the conductive material, 5nCJL
After a 5n02 layer doped with sb is deposited on the entire surface by CVD using 2/5bCfLs, the 5n02 layer other than the control gate electrode 12 is removed by plasma etching by mask alignment. In this case, it is preferable to use CCl4 as the etchant, while when using polycrystalline Si as the conductive material, 5iHa/
After depositing a layer of polycrystalline Si on the entire surface by CVD using PH3, control gate electrode 1 is formed by mask alignment.
Polycrystalline Si layers other than 2 are removed by plasma etching.

In this case, the etchant is CFa, CFa +
02, PC sentence 3 etc. are used. Note that it is suitable as a control gate electrode material when A or the incident beam is a high energy beam such as an electron beam.

(q) A layer (up to 5,000 layers) of phosphosilicate glass (PSG) 13 is deposited on the entire surface of the substrate by CVD and heat treated.

(r): Using a photoresist, the oxide film, nitride film, and PSG directly above the shielding gate region 6 are etched and removed according to a pattern formed by mask alignment to open a contact hole, and the contact hole is filled with a sputtering method. AI is filled and deposited on the entire surface of the PSG calendar 13, and excess AI is removed by etching using a photoresist pattern formed by mask alignment as a mask to form an AI shield gate electrode 14. In addition, since the contact hole is shallow, AI is surely filled in it, and the v
An electrode made of AI is formed on the entire surface (drain region) of the p-type Si substrate 1 and annealed to ensure that the c-type conduction is carried out reliably and that no step breaks occur.
A solid-state imaging device having an I↑ structure is completed.

[Second Embodiment] FIGS. 5A to 5N are cross-sectional views showing the manufacturing process of another embodiment of the solid-state imaging device according to the present invention. Below is the fifth
The explanation will be divided into items with the same reference numerals corresponding to each figure in the figure.

(A) An n+ type Si substrate 2o is prepared, a layer 21 is formed on it by an epitaxial method, and this is oxidized in a high temperature oxygen atmosphere to form an oxide film 2 of SiO□ on the layer 21.
form 2.

(B) A photoresist (PR) is formed in a portion other than the portion where the shielding gate region is to be formed by mask alignment using two photolithography.

(C) Oxidation 111 of the portion where the above-mentioned shield gate region is to be formed
13 is etched by the IIIE method (gas used: CFa/[2), and the layer 21 below is etched by RIE method (gas used: CCf13F102) perpendicular to that surface.
) Etching by ni. The hole formed in the n-type film 21 by this etching is made deeper than the n-type source region formed on the n-film 21 (for example, 1.0 to 5.OILrm), as will be described later.

(D) Polycrystalline 5i (P-9i) 23 doped with B is deposited in the two holes and on the entire surface of the oxide film 22 by the CVD method. * P-3i has good step coverage, so the hole is reliably filled. Ru.

(E): The polySi 23 on the oxide film 22 is removed by RIE or wet etching, and the polySi 23 in the hole is also removed from the remaining po17.
Etching is performed until the si23% surface becomes flush with the surface of the n calendar 21.

(F): 7 photoresist PR is formed on the oxide film 22 other than the portion where the control gate region is planned to be formed by mask alignment;
Using this photoresist PR as a mask, p inside the hole is
B is ion-implanted into the first layer 21 of the portion where the control gate region is to be formed therebelow through the OlySi 23 and the oxide film 22 (dose amount: lXl0 to 2XlO'').

(G): Remove photoresist PR and heat to 1000℃~1
A p-type shielding gate region 24 made of a P diffusion layer is formed around the poly 5i (B-doped) 23 filled in the hole by leaving it in an oxidizing atmosphere at 100° C. for 60 to 80 minutes, and a p-type control gate is formed. A region 25 is formed. Note that during this thermal oxidation, an oxide film (Si02) is formed on the surface of the polySi 23 in the hole.

(H): Using a photoresist, the oxide film 22 on the portion where the source region is to be formed is etched and removed according to a pattern formed by mask alignment to form an opening, and a hole for forming a source electrode is formed on the entire surface of the oxide film 22 and in the opening. poly
S12El is deposited by CVD method, and A
s ion implantation (dose amount: 10'ρ~10μc+
5-2).

(1): Using photoresist, excess polySi 2B is removed by a pattern formed by mask alignment.
is removed by etching to form a source electrode 28A.

(J): An n-type source region 27 made of an n-diffusion layer is formed in the n-type region 21 directly under the source electrode 2EiA by leaving it in an oxidizing atmosphere at 900 to 1100°C. At this time, the source electrode 28A is covered with an oxide film for two days.

(K): A photoresist PR is formed in a portion other than a part of the control gate region 25 by mask alignment using photolithography, and this is used as a mask to form a photoresist PR in the same region 25.
The oxide film 22 on a portion of the oxide film 5 is removed by etching to form an opening for a control gate.

(L): 5jlNa (7) Calendar (
500-1000 people) 28 was deposited, and the entire surface was doped with sb for forming a transparent control gate electrode.
Dopos.

Inz03. Ta205 or the like was deposited by the CVD method, and the remaining 5n02 and Dopos were deposited using a photoresist formed in the opening for the control gate by mask alignment using photolithography.

In, 03, 5n02 doped with sb by removing A2 05 etc., Dopes, I! +, 03,
A transparent control gate electrode 30 made of Ta205 or the like is formed.

(M): Deposit phosphorus silicate and togaras (PSG) calendar (maximum 5000) 31 on the entire surface by CVD method and heat-treat.

(N): Using a photoresist, the layer 3i layer 29 and the oxide film directly above the shielding gate region 24 are etched and removed according to a pattern formed by mask alignment to open a contact hole, and the contact hole is formed by sputter deposition. Fill in A sentence, and PSG calendar 3
Deposit AI on the entire surface of 1, and remove excess AI using the photoresist pattern formed by mask alignment as a mask.
is removed by etching to form an AI shield gate electrode 32. Note that the contact hole is shallow, so there is no A in it.
4 reliably filled and B doped poly Si
23 is made reliably and no step breaks occur, an electrode consisting of the pattern A is formed on the entire surface (drain region) of the p-type Si substrate 1 and annealed, thus forming a single SIT structure. A solid-state imaging device is completed.

As described in detail, according to the present invention, it is possible to provide a solid-state imaging device including an SIT having a shielding gate electrode free from defects such as breakage.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of an SIT that constitutes a conventional solid-state imaging device, Figures 2 (a) and (b) are cross-sectional views showing the manufacturing process of the SIT, and Figure 3 is a cross-sectional view of a part of the SIT. Figure, Figure 4(a)~
(r) is a sectional view showing the manufacturing process of one embodiment of the solid-state imaging device according to the present invention, and FIGS. 5(A) to (N) are sectional views showing the manufacturing process of another embodiment of the solid-state imaging device according to the invention. FIG. Figure 2 Figure 4 Figure 4 Figure 5

Claims (1)

[Claims] a control gate region formed on the first main surface side of the silicon wafer; a shielding gate region formed on the first main surface side of the silicon wafer so as to surround the control gate region; at least one first main electrode region formed on the first main surface side of the silicon wafer between the shield gate region; and a second main electrode region of the silicon wafer opposite to the first main electrode region. In a solid-state imaging device comprising a vertical static induction transistor having a second main electrode region formed on the main surface side of the semiconductor wafer, the bottom of the shield gate region is located further inside the silicon wafer than the first main electrode region. 1. A solid-state imaging device characterized in that the shielding gate region reaches a deep position, and the shielding gate region is connected to the shielding gate electrode via a semiconductor layer doped with impurities.