JPS6124759B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory chip select terminal interface circuit for transmitting a chip enable signal to a memory chip select terminal of a memory.

An example of a conventional backup system for non-volatile CMOS memory is shown in FIG. In the figure, 1 is n random access memory chips.
A memory consisting of RAM _p to RAM _o , 2 is an interface circuit that converts an external chip enable signal into a predetermined voltage and supplies it to the select terminal of each chip in memory 1. Each chip in memory 1 receives this chip enable signal. When supplied, it becomes active and allows reading and writing to the memory. This interface circuit 2 includes a transistor T _r1 , gate circuits G ₁ , G ₂ and resistors R ₁ ,
The circuit is configured by combining _R2 . Each chip of this interface circuit 2 and memory 1
RAM _p to _{RAM o} are connected to the system memory main power supply V ₁ via a reverse current prevention diode D ₁ .
Further, a voltage is applied from the memory auxiliary power supply V ₂ via the reverse current prevention diode D ₂ . Further, a bias circuit consisting of a Zener diode ZD and resistors R ₃ and R ₄ connected between the power supply V ₁ and the ground is connected to the base of the transistor T _r1 of the interface circuit 2, and a bias circuit is connected to the base of the transistor T r1 of the interface circuit 2. _G1 is configured so that a chip enable signal can be applied from the outside to one input terminal thereof.

In such systems, the main power supply for memory V ₁
When the memory 1 is backed up by the auxiliary power supply _V2 during a power outage, the chip select terminal of the memory 1 is pulled up. In other words, if the main power supply for memory V ₁ drops abnormally due to a power outage, current cannot be supplied to the Zener diode ZD (this standard value can be set arbitrarily at the design stage) for detecting the power supply voltage, and this causes the transistor No current can flow through the base of T _r1 , and this transistor T _r1 is in a cut-off state. Therefore,
The voltage from the memory auxiliary power supply V ₂ is applied to the gate circuit G ₁
Participate in input. The inputs of this gate _G1 are an external chip enable signal and a signal from this memory auxiliary power supply _V2 , and the chip enable signal is forcibly pulled up to the "H" level to give priority to the high "H" level. be done.

When the gate circuits G ₁ and G ₂ are constructed of CMOS gates, the load resistor R ₂ becomes unnecessary if the power supply of the CMOS gate circuits is connected to the auxiliary power supply V ₂ during power backup. However, when using memory 1 in the active state, the pull-up of the chip enable signal to the "H" level is delayed due to the delay of this CMOS gate, and the selection of memory 1 is delayed by that amount, resulting in a delay in the apparent memory access time. It turns out. In order to eliminate this drawback,
It is conceivable to use low power TTL or the like for the gate circuits G ₁ and G ₂ . Using this TTL can solve the speed delay, but when backing up memory,
The chip enable terminals of memory chips RAM _p to _{RAM o} may become open. For this reason, a pull-up resistor R ₂ is used, but in order to reduce the delay of the chip enable signal, the resistor R ₂
However, if it is made too small, current will flow through this pull-up resistor _R2 during power backup, resulting in a shortened lifespan of the memory auxiliary power supply _V2 .
However, when using low-power TTL, this TTL
The power source uses an external power source. Also, if the voltage of the Zener diode ZD is _Vz , then the power supplies V ₁ , V ₂
It is assumed that there is a relationship between V ₁ ≧V ₂ and V ₂ <V _z <V ₁ .

The present invention was made in view of the above circumstances, and
The input chip enable signal is transmitted through a gate circuit using a transfer gate or a clocked inverter, and a high resistance load is transmitted.
By configuring the circuit to pull up or pull down the output when switching from the memory main power supply to the auxiliary power supply using a MOS transistor, the delay in the chip enable signal described above can be reduced and the memory access time can be speeded up. Another object of the present invention is to provide a memory chip select terminal interface circuit that can reduce leakage current during power supply backup and extend the life of an auxiliary power supply.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows an interface circuit according to a first embodiment of the present invention, and the interface circuit of this embodiment uses a transfer gate. In this interface circuit, 3 is a transfer gate circuit, and a first P-channel MOS transistor T _P1 whose gate is connected to the output terminal of a CMOS inverter to be described later.
and a first N-channel MOS transistor T _N1 whose gate is connected to terminal B, the sources and drains of both transistors T _P1 and T _N1 are commonly connected, and the input terminal A is applied to the input terminal of the first N-channel MOS transistor T N1 . It transmits a signal from the output end to terminal D. 4 is
In a CMOS inverter circuit, a second P-channel MOS transistor T _P2 and a second N-channel MOS transistor T _N2 , which are provided between a terminal C and the ground and whose gates are connected to the terminal B, are connected in series. The signal applied to terminal B is inverted and outputted, thereby switching the transfer gate circuit 3. T _P3 is a third P-channel load transistor, whose gate is connected to the terminal B and whose drain is connected to the terminal C.
, the source is connected to output terminal D, and the source is connected to output terminal B.
This is for a signal pull-up resistor that pulls up the output signal of the transfer gate circuit 3 and sends a high "H" level signal to the output terminal D when the level of the signal applied to the output terminal D changes (during power backup).

When applying the above interface circuit to a CMOS-RAM power backup system, the third
Circuit connections are made as shown in the figure. That is,
Terminal A of the interface circuit 2' is connected to the input terminal IN to which a chip enable signal is applied from the outside (CPU), and terminal B is connected to a Zener diode ZD to input the voltage detection level signal of the main power supply _V1 for memory. The terminal C is connected to the external main power supply V ₁ for memory and the auxiliary power supply V ₂ for memory through reverse current prevention diodes D ₁ and D ₂ so that the memory power supply is applied. D is each memory chip of memory 1
Connected to the chip select terminals of RAM _p to RAM _o , respectively. Further, as described above, each memory chip RAM _p to RAM _o of the memory 1 has a diode D ₁ ,
A voltage V _DD is applied from the power supplies V ₁ and V ₂ via D ₂ , and the cathode of the Zener diode is connected to the main power supply V ₁ and the anode is connected to the resistor.
Each is connected to ground via R ₃ and R ₄ . Furthermore, the relationship between the power supply voltages V ₁ and V ₂ and the voltage V _Z of the Zener diode ZD is set such that V ₁ ≧V ₂ and V ₂ <V _Z <V ₁ .

In the above device, when using memory 1 in an active state, main power supply V ₁ and auxiliary power supply V ₂ are connected.
A power supply voltage that satisfies the condition of V ₁ ≧V ₂ is applied to each chip RAM _p to RAM _o of the memory 1. At this time, current flows through the Zener diode ZD for voltage detection of the main power supply _V1 , so the voltage drop across the bias resistors _R3 and _R4 causes the terminal B of the interface circuit 2 to go to the high "H" level, which means that the inverter Circuit 4 and load MOS transistor T _P
The input to ₃ becomes "H" level. This high "H" level signal turns on the inverter circuit 4, while turning off the load MOS transistor T _P3 . In the transfer gate circuit 3, a high level signal is applied to the gate of the transistor T _N1 ,
Since the low "L" level output of the inverter circuit 4 is applied to the gate of the transistor T _P1 , the transfer gate circuit 3 becomes active.
Therefore, the chip enable signal applied to the input terminal IN from the outside (CPU) is applied to the chip select terminal of the memo 1 through the transfer gate circuit 3. In other words, since the chip enable signal is delayed only by the transfer gate circuit 3, the delay can be made much smaller than in the prior art, and as a result, the memory access time becomes faster. In addition, the load for pull-up
Since the MOS transistor T _P3 is off when the memory 1 is actively used, its on-resistance value can be set to a large value at the time of design. This load MOS transistor T _P3 can avoid effects such as rounding of the waveform of the chip enable signal when the memory is active.

On the other hand, if the voltage of the external main power supply V ₁ drops due to a power outage and becomes lower than the detection level voltage V _Z of the Zener diode ZD and the voltage of the auxiliary power supply V ₂ , the power supply to the memory 1 is switched to the main power supply. Switching from V ₁ to the auxiliary power supply V ₂ causes no current to flow through the Zener diode ZD, so the voltage level at terminal B of the interface circuit 2' becomes low "L" level. Therefore, the input to the inverter circuit 4 becomes "L" level and the inverter circuit 4 is turned off. On the other hand, in response to this "L" level input, the load
MOS transistor T _P3 is turned on. At this time, the transfer gate circuit 3 is turned off and the external chip enable signal from the input terminal IN is not transmitted to the terminal D, but the load MOS transistor T _P3 is turned on, so that the interface circuit 2'
Terminal D of is pulled up to the voltage level of auxiliary power supply _V2 . This pulled-up level signal is supplied to the chip select terminals of each chip RAM _p to RAM _o in memory 1 as if it were an external chip enable signal, so even in the event of a power outage, access to memory 1 can continue as before. Become. In this case, the load MOS transistor T _P3 is designed to have a large on-resistance to reduce its operating current, and since the transfer gate circuit 3 is off, the load MOS transistor T _P3 is Auxiliary power supply through V ₂
The leakage current flowing through the capacitor becomes extremely small. As a result, the life of the auxiliary power supply _V2 can be extended.

Incidentally, the above-mentioned interface circuit 2' can be modified as shown in FIG. In this circuit,
In place of the transfer gate circuit 3, a clocked inverter circuit 5 consisting of P channel MOS transistors T _P4 and T _P5 and N channel MOS transistors T _N3 and T _N4 is used. The interface circuit using this clocked inverter circuit 5 also has the same function as described above.

Furthermore, if the logic operation of the chip select terminal of the memory 1 is the opposite logic to that of the above-described embodiment, the circuit may be constructed using MOS transistors of the opposite conductivity type.
For example, the load of the interface circuit in Figure 2
The fifth MOS transistor T _P3 is replaced with a reverse conductivity type (N channel) MOS transistor T _N5 .
The circuit may be configured as shown in the figure so that the signal at the terminal 1 and the signals at the terminals B and D are in an inverted relationship. In this case, the level of the chip select terminal is pulled down when backing up the power supply, and has the same operation and effect as the previous embodiment.

The interface circuit of the present invention is a CMOS-
This is effective when the RAM memory is used as non-volatile memory by switching to an auxiliary power supply during a power outage, etc., and is used as a non-volatile memory.In addition, each RAM chip in the memory has only one chip select terminal. Suitable for use in cases.

As explained above, according to the present invention, an input chip enable signal is transmitted through a gate circuit using a transfer gate circuit or a clocked inverter circuit, and a high-resistance load is transmitted.
The circuit configuration is such that the output is pulled up or pulled down when switching from the main power supply for memory to the auxiliary power supply using a MOS transistor, so the delay in the chip enable signal is reduced and the memory access time is speeded up. It is possible to provide a memory chip select terminal interface circuit that can reduce leakage current during power supply backup and extend the life of an auxiliary power supply.

[Brief explanation of the drawing]

Figure 1 shows a diagram using a conventional interface circuit.
FIG. 2 is a configuration diagram of a memory chip select terminal interface circuit according to an embodiment of the present invention, and FIG. 3 is a configuration diagram of a CMOS memory backup system.
FIGS. 4 and 5 are block diagrams of the memory backup system, respectively, and are block diagrams of memory chip select terminal interface circuits according to other embodiments of the present invention. 1...Memory, 2'...Interface circuit, 3...Transfer gate circuit, 4...Inverter circuit, 5...Clocked inverter,
RAM _p ~ _{RAM o} ...Memory chip, T _P1 ~ _{T P3} ...
...P channel MOS transistor, T _N1 to _{T N4} ...
...N-channel MOS transistor, R ₁ to _{R 4} ...
Resistor, V ₁ ... External main power supply for memory, V ₂ ... Auxiliary power supply for memory, D ₁ , D ₂ ... Diode, ZD ...
Zener diode... Chip enable signal.

Claims (1)

[Scope of Claims] 1. In a memory chip select terminal interface circuit that is connected to each memory chip select terminal of a memory, receives a chip enable signal for selecting a memory chip and makes it active, and transmits it to each of the memory chip select terminals. , a gate circuit that transmits the chip enable signal to the memory chip select terminal, an inverter circuit that turns on and off according to a potential level signal of the memory main power supply to control signal transmission of the gate circuit, and the memory main power supply. and a high-resistance load MOS transistor that performs a predetermined level conversion by pull-up or pull-down at the time of power backup when switching from the chip enable signal to the auxiliary power supply, and supplies a signal equivalent to the chip enable signal to the memory chip select terminal. A memory chip select terminal interface circuit featuring: 2. The memory chip select terminal interface circuit according to claim 1, wherein the gate circuit is constituted by a transfer gate circuit. 3. The memory chip select terminal interface circuit according to claim 1, wherein the gate circuit is constituted by a clocked inverter circuit.