JPS61247107A - Synchronous detector - Google Patents

Abstract

PURPOSE:To decrease the ripple of a detection signal by sampling a measured frequency signal and applying subtraction and synthesis to the result at the zero cross point of the leading and trailing of a reference frequency signal. CONSTITUTION:A zero detector 13 generates the 1st sampling pulse (c) and the 2nd sampling pulse (d) at the zero cross point of time of the leading and trailing of the reference frequency signal (b). The 1st sample-and-hold device 14 samples the measured frequency signal (a) when the pulse (c) is generated and outputs a sample-and-hold signal (e). The end sample-and-hold device 15 outputs similarly a sample-and-hole signal (f). A synthesizer 16 synthesizes subtractively the signals (e, f) and outputs a detection signal (g).

Description

[Detailed description of the invention] Industrial applications The present invention relates to a synchronous detection device.

BACKGROUND OF THE INVENTION Conventional synchronous detection devices are widely used to detect amplitude modulated signals of frequency signals under test that are amplitude modulated. The configuration of a conventional synchronous detection device is shown in FIG. Further, a waveform diagram for explaining the operation is shown in FIG. This will be explained below.

The frequency-to-be-measured signal source 2o1 has a specific frequency and generates a frequency-to-be-measured signal a' whose amplitude is modulated (
Figure 9(a)). The reference frequency signal source 202 generates a reference frequency signal b' having the same frequency and phase as the frequency signal a' to be measured (FIG. 9(b)).

The shaper 203 shapes the waveform of the reference frequency signal d to produce a shaped signal C' (FIG. 9(C)). Multiplier 204
multiplies the measured frequency signal a' and the shaped signal ♂ to obtain a multiplied signal d' (@9 (d)). The low-pass filter 205 reduces and removes the ripple component of the multiplied signal d' to obtain a detected signal ♂.

Problems to be Solved by the Invention In such a conventional synchronous detection device, since the multiplier 204 is used, a very large ripple occurs in the multiplied signal d'. Therefore, in order to reduce the ripple of the detected signal e', it is necessary to provide the low-pass filter 206 with a high-order filter characteristic at a considerably low corner frequency.

However, if the low-pass filter 206 is set to a high level, the frequency characteristics of the detected signal e' deteriorate, so there is a limit to the reduction of ripples due to the filter characteristics. That is, the ripple could not be sufficiently reduced by the low-pass filter 205, and the ripple remaining in the detected signal l was large.

Taking these points into consideration, the present invention provides a synchronous detection device that does not use a multiplier and has very small ripples.

Means for Solving the Problems The present invention provides a frequency-to-be-measured signal generating means for generating a frequency-to-be-measured signal to be detected, and a reference having the same frequency as the frequency-to-be-measured signal and a phase difference of 90 degrees or approximately 90 degrees. a reference frequency signal generating means for generating a frequency signal; a first sample hold means for sampling the frequency signal under test at a zero cross point of a rising edge of the reference frequency signal and holding the sampled value until the next sampling point; sampling the frequency signal to be measured (or the inverted signal of the frequency signal to be measured) at the zero cross point of the falling edge of the reference frequency signal;
a second sample hold means for holding the sampled value until the next sampling point; and a synthesis means for subtractively synthesizing (or additively synthesizing) the output signal of the first sample hold means and the output signal of the second sample hold means. The above objective is achieved by having the following.

Operation The present invention significantly reduces the ripple of the detected signal (output signal of the combining means) by adopting the above-mentioned configuration. Furthermore, the isometric sampling frequency is increased to improve the frequency characteristics of the detected signal.

Example FIG. 1 shows a configuration representing an embodiment of the present invention.

Further, FIG. 7 shows a waveform diagram for explaining the operation.

In FIG. 1, a frequency-to-be-measured signal generator 11 generates an amplitude-modulated frequency-to-be-measured signal a of a predetermined frequency (
Figure 7(a)). The reference frequency signal generator 12 generates a reference frequency signal S having the same frequency as the frequency of the frequency signal to be measured a, but having a phase different by 90 degrees or approximately 90 degrees (FIG. 7(bO)).

The zero cross detector 13 receives the reference frequency signal S, and detects the first sample pulse C which becomes "H" (high potential state) for a short time at the zero cross point of the rising edge of the reference frequency signal S, and the reference frequency signal S A second sample pulse d is created which becomes m H for a short time at the falling point (FIG. 7(C)).

@)).

FIG. 2 shows a specific configuration of the zero cross detector 13, and FIG. 6 shows a waveform diagram for explaining its operation.

The comparator 31 shapes the waveform of the reference frequency signal at the zero-cross point, and produces a first comparator rate signal j (FIGS. 6(-) and 6(b)). In addition, the controller 2 (rater 33, 34, reference voltage source 35, 36 and AND circuit 3
7, the reference frequency signal and the reference voltage source 36°360 voltage value are compared by the window controller 2 (rater circuit 32), and the second controller 2 receives the rate signal k (6th
Figure (C)). The second converter (rate signal) becomes "H" (high potential state) when the reference frequency signal is within a predetermined range including zero, and becomes "L" (high potential state) when the reference frequency signal is outside the predetermined range. The first comparator rate signal 1 is input to the data input terminal p of the data input type edge trigger flip-flop 38, and the second comparator signal is input to the clock pulse of the flip-flop 38. Input to input terminal GK.Flip-flop 3
8 inputs the state of the second comparator 2 (the state of the rate signal i at the rising edge of the rate signal to the output signal l, and inputs that state to the second comparator signal at the next rising edge). Hold until the arrival of the edge (6th
Figure (d)).

The AND circuit 41 outputs the first rate signal j
The first sample pulse C is created by ANDing the output signal 1 of the flip-flop 38 and the output signal 1 of the flip-flop 38.
In FIG. 6(, )), the first sample cross C corresponds to the zero cross point of the rising edge 9 of the reference frequency signal S. In addition, a second sample pulse d is generated from the first comparator signal j and the output signal 1 of the 7-lip-flop 38 by the input circuit 39 and 40 and the AND circuit 42 (Fig. 6(f)). The second sample pulse d corresponds to the zero cross point of the falling edge of the reference frequency signal S.

The first sample pulse C of the zero cross detector 13 is input to the first sample hold device 14, which samples the frequency signal a to be measured at the time when the first sample pulse C becomes "H#", and calculates its value. The first sample and hold signal e
, and is held until the next sampling point (FIG. 7(e)).

FIG. 3 shows a specific configuration of the first sample and hold device 14. The first sample and hold device 14 is an operational amplifier 5.
1.54, an analog switch 52, and a capacitor 53. The measured frequency signal a is input to the non-inverting input terminal of the operational amplifier 51. The analog switch 62 is
is in an open state when the first sample pulse C is L'';
When the first sample pulse C reaches 6H', a short circuit occurs. When the analog switch 62 is short-circuited, the power amplifier 61 operates as a buffer circuit, and the capacitor 63
is charged or discharged by the operational amplifier 51, and the terminal voltage of the capacitor 53 becomes equal or approximately equal to the voltage value of the frequency signal to be measured at that time.In addition, when the analog switch 62 becomes open, the terminal voltage of the capacitor 53 at that time The charge and voltage of is maintained. Then, the voltage of the capacitor 63 is outputted as the first sample hold signal e through the output circuit of the operational amplifier 64. The measured frequency signal a is input to the sample hold device 16 and the moment the second sample pulse d becomes @H#
is sampled, and its value is output as the second sample-and-hold signal f, and held until the next sampling point (FIG. 7(f)).

FIG. 4 shows a specific configuration of the second sample and hold device 15. The second sample and hold device 16 is an operational amplifier 6
1.64, an analog switch 62, and a capacitor 63. The measured frequency signal a is input to the non-inverting input terminal of the operational amplifier 61. The analog switch 62 is
is in an open state when the second sample pulse d is L#;
When the second sample pulse d becomes lHIll, a short circuit condition occurs. When the analog switch 62 becomes short-circuited,
The operational amplifier 61 operates as a buffer 1 circuit, the capacitor 63 is charged or discharged by the operational amplifier 61, and the terminal voltage of the capacitor 63 becomes equal to or approximately equal to the voltage value of the frequency signal under measurement a at that time. Also,
When the analog switch 62 is in the open state, the charge and voltage of the capacitor 63□ at that time are held. Then, the voltage of the capacitor 63 is outputted as a second sample-and-hold signal f via a back 1 circuit including an operational amplifier 64.

The first sample and hold signal e of the first sample and hold device 14 and the second sample and hold signal f of the second sample and hold device 16 are input to the synthesizer 16. The synthesizer 16 subtracts and combines the first sample-and-hold signal e and the second sample-and-hold signal f, and outputs a detected signal q (FIG. 7).

(q)). FIG. 5 shows a specific table structure of the synthesizer 16.

The synthesizer 16 includes an operational amplifier 71 and resistors 72 and 73°74.
．． 75, and outputs the result by subtracting the first sample-and-hold signal e and the second sample-and-hold signal f.

As shown in this embodiment, if a sample Hall device is used, the ripple of the detected signal q will be significantly reduced. Therefore, the present synchronous detection device does not require a low-pass filter.

In addition, since there is no low-pass filter, the frequency characteristics of the detected signal q are also improved.Furthermore, the output signal of the first sample and hold device and the output signal of the second sample and hold device are combined to obtain the detected signal q. Therefore, the equal-constraint sampling frequency becomes higher. In other words, there is an effect that the frequency characteristics of the detection signal q are further improved (up to high frequencies can be detected). is not limited to such cases. For example, in a second sample and hold device, the inverted signal of the frequency signal to be measured is sampled using a second sample pulse and held until the next sampling, and in a synthesizer, the first sample and hold signal and the second It goes without saying that the sample-and-hold signals may be added and synthesized, and this is included in the present invention.

In addition, various modifications can be made without changing the gist of the present invention.

Effects of the Invention Although the synchronous detection device of the present invention has a simple configuration, the ripple of the detected signal is small and the frequency characteristics are good. Therefore, if a synchronous detection device for various signals is constructed based on the present invention, very good synchronous detection will be possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a synchronous detection device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration of the zero-cross detector shown in FIG. 1, and FIG. 4 is a block diagram showing a specific configuration of the second sample and hold device in FIG. 1, and FIG. 6 is a block diagram showing a specific configuration of the second sample and hold device in FIG. 1. FIG. 6 is a waveform diagram for explaining the operation of the zero cross detector of FIG. 2, FIG. 7 is a waveform diagram for explaining the operation of the synchronous detection device of the present invention, and FIG. A configuration diagram showing a conventional synchronous detection device, and FIG. 9 is a waveform diagram for explaining the operation of the conventional synchronous detection device shown in FIG.・
...Reference frequency signal generator, 13...Zero cross detector 1.14...First sample and hold device, 15...Second sample and hold device, 16
...Synthesizer. Figure 7 O -c810℃

Claims (1)

[Claims] Measured frequency signal generating means for generating a measured frequency signal to be detected; reference frequency signal generating means for generating a reference frequency signal having the same frequency as the measured frequency signal and a phase difference of 90 degrees or approximately 90 degrees; a first sample and hold means for sampling the frequency signal under test at the zero cross point of the rising edge of the reference frequency signal and holding the sampled value until the next sampling point; and at the zero crossing point of the falling edge of the reference frequency signal; a second sample-hold means for sampling the frequency signal under test (or an inverted signal of the frequency signal under test) and holding the sampled value until the next sampling point; and an output signal of the first sample-hold means; A synchronous detection device comprising: a synthesizing means for subtractively synthesizing (or additively synthesizing) the output signals of the second sample and hold means.