JPS61247067A - Time constant regulator - Google Patents

Abstract

PURPOSE:To enable the regulating of a time constant in a short time without increasing a circuit scale or regulating steps by commonly using the input terminals of a plurality of current mirror circuits, and connecting corresponding time constant circuits with output terminals. CONSTITUTION:A current mirror circuit has a common input terminal of col lectors of transistors Q0, and the collectors of transistor Q1-Qn as output terminals. The current mirror ratio of the circuits are set by the resistance ratio of resistors R1-Rn to the resistor R0. For example, the current mirror ratio of the circuits formed of the transistors Q0, Q1 regarding the time constant circuit CkT1 is decided by the ratio of the resistors R0, R1. The ratio of the current mirror ratios among a plurality of current mirror circuits is determined in response to the time constants between the time constant circuits CkT1-CkTn. The input current of the common input terminal of the circuits is regulated by a variable resistor VR0.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a time constant adjustment device suitable for adjusting the time constants of a plurality of time constant circuits built into a semiconductor integrated circuit.

[Technical background of the invention]

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become more highly integrated, capacitive elements for time constant circuits have often been built into the integrated circuits.

Capacitive elements built into semiconductor integrated circuit ICs are generally
It has a structure as shown in Figure 4.

That is, FIG. 4 shows an MO8 structure i- element formed of a kt layer, an insulating layer, and an n+ semiconductor layer.
''. Although this capacitive element has good accuracy in its area (AL on the left), the thickness and dielectric constant of the insulating layer vary considerably. Therefore, its capacitance value ranges from ±20 to 3
It varies within a range of 0.

FIG. 5 shows an example of a conventional circuit using such a capacitive element as a capacitive element of a time constant circuit in a semiconductor integrated circuit.

The circuit shown in FIG. 5 has a plurality (n) of time constant circuits CkT1 to CkTn in one semiconductor integrated circuit. Each of the time constant circuits CkT and CkTn has capacitive elements 01 to C, respectively.

Since the capacitance values of these capacitive elements 01 to Cn vary within a range of ±20 to 30%, each time constant circuit CkT1 to
To accurately match CkTn to the desired value (design value), provide terminals T1 to Tn for each, connect variable resistors VR and ~vRn to each, and adjust the resistance value to adjust the design value. need to get it.

[Problems with background technology]

However, as mentioned above, each time constant circuit CkT1~
In a configuration in which a time constant is provided for each CkTn,
As the number of time constant circuits CkT1 to CkTn increases, the number of terminals and variable resistors increases. This increases the circuit scale by K, and furthermore, it is necessary to adjust the time constant of each time constant circuit CkT1 to CkTn, which increases the number of adjustment steps and is extremely uneconomical.

[Purpose of the invention]

This invention was made to deal with the above-mentioned situation, and by making the time constant adjustment section of a plurality of time constant circuits common, even when the time constant circuits are integrated into a semiconductor integrated circuit, It is an object of the present invention to provide a time constant adjusting device that can adjust a time constant in a short time without increasing the circuit scale or increasing the number of adjustment steps.

[Summary of the invention]

This invention achieves the above object by providing a current mirror circuit for each time constant circuit, making the input terminals of these plurality of current mirror circuits common, and connecting each output terminal to the corresponding time constant circuit. be.

That is, in the above configuration, by setting the ratio of current mirror ratios between the plurality of current mirror circuits according to the ratio of the time constants of the plurality of time constant circuits, and by adjusting the input current of the common input terminal. , all time constants can be set to desired values at once.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, CkT to CkTn are time constant circuits built into this semiconductor integrated circuit IC.

Each time constant circuit CkT, ~CkTn each has a capacitive element C
It has 4 to Cn.

Each capacitive element C4 to Cn is connected to the collector of current source transistor Q, to Qn, respectively. The emitters of each transistor Q, ~Qn are resistors R4~Rn, respectively.
It is connected to the power supply VCC via. Also, the pace of all transistors Q, ~Qn is diode-connected transistor Q. are commonly connected to the base. The emitter of this transistor Qo is connected to the power supply vcc via a resistor R8. Also, transistor Q. The common connection point between the pace and the collector of is connected to the collector of the transistor Q, which has the opposite polarity to the transistors Q0 to Qn.

The emitter of this transistor Q is terminal T. connected to,
A variable resistor VR is externally connected to this terminal T0.

A bias power supply VB is connected to the base of the transistor Q.

In the above configuration, each time constant circuit CkT, ~CkTn
Transistors Q and -Qn corresponding to each form a current mirror circuit with transistor Q.

Tsumashi, these current mirror circuits are transistor Q
0 as a common input terminal, and each transistor Q1~
Let the collector of Qn be the respective output terminal. The current mirror ratio of each current mirror circuit is set by the resistance ratio of the resistor R and each of the resistors R1 to Rn. for example,
Transistor Q01Q related to time constant circuit CkT,
The current mirror ratio of the current mirror circuit configured by is determined by the ratio of resistors R6 and R1.

Further, the ratio of current mirror ratios among these plurality of current mirror circuits is determined by the time constant circuit CkT1. It is determined according to the ratio of time constants between CkTn. and.

The input terminal of the common input terminal of multiple current mirror circuits is
Variable resistance ■. adjusted by.

The operation in the above configuration will be explained. In a semiconductor integrated circuit, the characteristics of each strand generally vary widely as described above, but if the elements are of the same type, their tendency to change is almost the same (pairing). Therefore, the characteristic ratio between elements of the same type can always have a desired value, regardless of variations in the characteristics of the elements. Therefore, at the design stage, by setting the capacitance ratios of the capacitive elements C1 to Cn and the resistance ratios of the resistors constituting the time constant circuits CkT, ~CkTn to match the desired time constant ratios, variations in element characteristics can be avoided. However, the desired time constant can be obtained. Similarly, by appropriately setting the resistance values of the resistors R0 to Rn according to the desired time constant ratio, the ratio of the current mirror ratios between the plurality of current mirror circuits can also be changed. It can be adjusted to a constant ratio. Furthermore, by setting the element characteristics in this way,
Each current mirror circuit and each corresponding capacitive element C1
The ratio of time constants between the plurality of time constant circuits constituted by ~Cn also matches the desired time constant ratio. Therefore, by measuring the time running number of at least one of the time constant circuits CkT1 to CkTn and adjusting the input current of the current mirror circuit using the variable resistor vRo so that this becomes the desired value, all Time constant circuit CkT
, ~CkTn can be set to desired values with high accuracy.

As detailed above, in this embodiment, each time constant circuit CkT
A current mirror circuit is provided for each discharge, and the input terminals of these current mirror circuits are made common, and the ratio of the current mirror ratio between each current mirror circuit is determined by the above-mentioned time constant circuit CkT.

-CkTn. According to such a configuration, all the time constant circuits CkT, CkT,
The time constant of ~CkTn can be adjusted. Moreover, there is an advantage that all these adjustments are made at the same time. the result,
When incorporating time constant circuits CkT, ~CkT into an integrated circuit IC, even if the number of time constant circuits increases, the number of terminals T and variable resistors does not increase, and the circuit scale and manufacturing costs increase. It can be prevented.

FIG. 2 is a circuit diagram showing an example of a specific configuration of the bias power supply VB shown in FIG. The bias power supply VB in FIG.
It is configured to compensate for variations in the time constant due to variations in the current and temperature drift.

That is, the illustrated circuit has a transistor QA and a resistor RA that form a current mirror circuit with a diode-connected transistor Q0 and resistor R0. The collector of the transistor QA has the same polarity as the transistor Q and is connected to a common connection point between the base and collector of a diode-connected transistor QB. The emitter of this transistor QB is grounded via a resistor R. And the pace of transistor QA is transistor Q. Connect to the pace of
The common connection point between the pace and collector of transistor Q is connected to the pace of transistor Q. In the above configuration, the collector voltage of transistor QA becomes the bias voltage of transistor Q. Therefore, the resistance ratio of resistors R6 and RA and transistors Q, , Qo, Q
If the following relationship is set for the emitter area AEO ratio of B and Q, the above-mentioned compensation can be completely realized.

Ro:RA= AFJ(QA):AE(Q.)=A
E (Qll): AE (Q) - (1) Figure 3 shows the time constants of the 1f'M modulator for luminance signals and the FM demodulator of a video tape recorder (hereinafter referred to as VTR). Adjustment is intended to illustrate the case of this invention.

In FIG. 3, transistors Qtt, Qtz and resistors R10*R11 constitute a bias circuit 11t. An emitter-coupled astable multivibrator including transistors QM, ~QM6, resistors RM, ~RM4, and capacitive element C constitutes the FM modulator 12.

An emitter-coupled monostable multivibrator 13 including transistors QD, ~QD6 *resistors RD, ~RD4, and capacitive element CD, and a multiplier 132 constitute a 1M demodulator 13.

Further, the modulation input terminal Ta of the semiconductor integrated circuit IC is connected to the power supply V via a sink carrier adjustment variable resistor vRc. Connected to C. During recording, signal is input to this input terminal TIL from the video signal source S via the knee adjustment variable resistor vRD. The modulated output of this video signal (FM video signal) is output from the output terminal T.

During playback, the demodulated output of the Ei'M video signal is guided to the terminal 15 via the demodulated pulse output terminal T0 and an external low/yas filter 4.

The operation in the above configuration will be explained.

First, the F'M modulation operation in recording mode R will be explained. In this case, the mode indication signal Sl.

Since S2 is at low level and high level, respectively, transistor QD6 is turned off and transistor QM6 is turned on. Also, the bias circuit 11 is connected to the transistor Q.
The emitter potential of M3 is set to ()v'cc). Therefore, no direct current flows through the variable resistor VRD, but only alternating current.

Here, the current IM driving the emitter-coupled astable multi-pipe rake is as follows. The first term on the right side of the above equation is the DC component, and the second term is only the AC component. Since the oscillation frequency of the FM modulator 12 is determined by this current and the time constant determined by the capacitive element CM, even if the capacitance value of the capacitive element CM varies within a range of ±20 to 30%, the variable resistor vRC1vRD By adjusting it, it is possible to match the specified syn-edge lag carrier frequency and deviation.

On the other hand, in the FM demodulation operation in reproduction mode P, transistor QM6 is turned off and transistor QD6 is turned on. Accordingly, the emitter potential of transistor QD3 is %
(-zVcc). At this time, the amplitude of the video signal from the signal source Si is set to an OK level, and [signal source (S,
) is set as such by the semiconductor integrated circuit that constitutes it.

No current flows through the variable resistor VRD. Therefore, the current engineer driving the emitter-coupled astable multivibrator. becomes . The above equation represents direct current. Jin's current ■.

The demodulation sensitivity of the F'M demodulator is determined by the time constant determined by the capacitance value of the capacitive element CD.

Here, the capacitance value of the capacitive element CD has a variation of ±20 to 30 inches, but since the relative accuracy (pairability) with the capacitive element CM is good, when adjusting the 1M demodulator 13, the capacitance value of the capacitive element CM that varies is If the resistance value of the variable resistor vRc is adjusted correctly with respect to the capacitance value, the current (2) can be obtained by directly substituting this resistance value into equation (3). The time constant determined by the capacitance CD and the capacitance CD hardly vary.

In the above explanation, to summarize the parts related to this invention, all the circuit constants of the circuit shown in FIG.
If the oscillation frequency of the M modulator 12 and the demodulation sensitivity of the I'M demodulator 13 are determined in advance, even if capacitive elements CM and CD with extremely large variations in capacitance value (absolute value) are used,
Variable resistors VR6 and VR
By adjusting the oscillation frequency during FM modulation operation to a desired value using D, the demodulation sensitivity of F'M demodulation operation almost matches the desired value. There is no variation in demodulation sensitivity ' due to variation in the capacitance value (absolute value) of the quantum element CD. At this time, the variation in demodulation sensitivity is caused by the capacitive element C
Variation in the capacitance ratio of MtCD, variation in the resistance ratio of resistors RM□ and RM3, and resistance RD2. Although it is determined by the variation in the resistance ratio of RD3, the variation in the ratio of characteristics of these same types of elements is extremely small in a semiconductor integrated circuit.

In this way, when the present invention is applied to adjusting the time constants of the time constant circuit of the FM modulator 120 for brightness signals of a VTR and the time constant circuit of the 1M demodulator 13, the time constant of the FM modulator 12 is adjusted to oscillate. Just set the frequency to the desired value, F'M
The time constant of the demodulator 13 is also automatically set to a desired value, and its demodulation sensitivity is also set to a desired sensitivity.

It goes without saying that the present invention is also applicable to adjusting the time constant of a time constant circuit other than a time constant circuit integrated into a semiconductor integrated circuit.

〔Effect of the invention〕

As described above, according to the present invention, by making the time constant adjustment section of a plurality of time constant circuits common, even when the time constant circuits are integrated into a semiconductor integrated circuit, there is no increase in the circuit scale or It is possible to provide a time constant adjustment device that can adjust the time constant in a short time without increasing the number of adjustment steps.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a circuit diagram showing an example of a specific configuration of the bias power supply shown in FIG. 1, FIG. 3 is a circuit diagram showing an example of an application example of the present invention, and FIG. 4 is a circuit diagram showing a semiconductor integrated circuit structure of a capacitive element. FIG. 5 is a circuit diagram showing a conventional device. CkT, ~CkTn...time constant circuit, C4~Cn...
・Capacitive element, R-R...resistance, QxsQo-Qn...
・Tran ON soster, VB...Bias power supply, ■...Variable resistor. First cause

Claims (1)

[Claims] A plurality of time constant circuits, and a plurality of count mirror circuits provided in each of the plurality of time constant circuits, having a common input terminal, and each output terminal being connected to a corresponding time constant circuit. , current adjusting means capable of adjusting the input current of the common input terminal of the plurality of current mirror circuits, and the ratio of the current mirror ratio between the plurality of current mirror circuits is such that the ratio of the current mirror ratio between the plurality of time constant circuits is A time constant adjustment device characterized in that the time constant adjustment device is configured to be set according to a ratio of time constants.