JPH011288A - Temperature Compensated Integrated Circuit Hall Effect Device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to Hall effect sensors and similar sensors characterized by sensitivity that changes significantly with temperature.
In particular, it relates to integrated circuit Hall effect devices having means for achieving substantially temperature independent sensitivity.

BACKGROUND OF THE INVENTION Hall effect sensors are recognized as offering significant advantages in numerous sensing applications.

Such sensors have been widely used where on/off output, ie, binary output, is desired or allowed.

Hall effect sensors are also used in a variety of applications requiring analog output.

However, since the output voltage of the Hall effect element is low,
The need for amplification limits its usefulness, and since the sensitivity of the Hall effect element varies with temperature, a temperature varying amplification must be implemented to provide temperature compensation.

In the past, expensive and bulky precision amplifiers and compensation circuits were commonly utilized in an attempt to achieve acceptable accuracy, including linearity and stability over a temperature range. However, such measures did not provide sufficient accuracy for many applications. Moreover, even in many applications where it would be possible to meet the required accuracy requirements with known amplifier and compensation circuits, the high cost of such circuits is unacceptable.

The present invention utilizes a very compact and low cost circuit to provide precise temperature control by forming the Hall effect element and portions of the amplifier gain control resistor and responsivity tracking resistor on the same epitaxial layer. A special Hall effect collector circuit that performs compensation and also features various convenient offset and zero adjustment functions that facilitate the configuration of the elements for the circuit to operate precisely and in a non-temperature dependent manner. Provide an element.

[Means to solve the problem]

The present invention consists in providing an integrated circuit Hall effect element or similar sensing element having means for providing almost no temperature dependent sensitivity. The device includes a Hall effect element formed in an epitaxial layer and amplifier means including resistor means partially formed in the same epitaxial layer. The amplifier means are configured for current/voltage conversion (mutual resistance) with a first amplifier stage formed from a pair of ideally identical amplifiers connected in a voltage/current conversion (transconductance) configuration. and a current mirror interface connecting the first and second amplifier stages to each other. The first amplifier stage is
It may also include a bias resistor, a portion of which is formed in the epitaxial layer. The second amplifier stage has a resistor, a part of which is also formed in the epitaxial layer, and includes adjustment means for adjusting the rate of change of the mutual resistance with respect to temperature.

The first and second amplifiers of the first amplifier stage may be cross-connected via an input offset adjustment circuit to minimize amplifier imbalance conditions.

the amplifiers each have first and second input terminals;
The first input terminal is connected to the Hall effect element and the second input terminal is connected to a separate end of the transconductance adjustment resistor. The output bias reference current through the amplifier is controlled by a bias resistor. A current multiple times the current flowing through the transconductance adjustment resistor is transmitted via the current mirror interface to the resistor of the adjustment means of the second amplifier stage.

The first amplifier stage may also include an output offset adjustment function to roughly reduce the offset error introduced by the amplifier stage. The second amplifier stage is null-adjusted so that the output voltage of the element when the applied magnetic field is zero can be set to any point within the normal output voltage swing range. It may also have a function.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, 10 is a Hall effect element having output terminals 11 and 12. When a current is passed between input terminals 13 and 14 and the element is subjected to a magnetic field, a voltage is generated between these output terminals 11 and 12. The Hall effect element 10 includes a N
It can be formed as an epitaxial layer on a semiconductor substrate by conventional methods from epitaxial materials. Hall effect elements are arranged in an integrated circuit layout such that the directions of the supplied currents are orthogonal to each other to reduce mechanical stress effects.
Preferably, it includes two identical elements. In some situations, it may be advantageous to use more than two elements.

As shown in FIG. 1, a current is passed between the input terminals 13 and 14 of the Hall effect element by connecting them to a voltage source V and a ground point 15, respectively. The output terminals 11 and 12 are respectively connected to a first input terminal and a second input terminal of a first amplifier stage consisting of a pair of amplifiers 16 and 17, which should ideally be identical. Ru. Amplifiers 16 and 17 are cross-connected via an input offset adjustment circuit shown as block 18. The amplifier is also connected to ground 15 via a bias circuit 19 operative to track the responsivity of Hall effect element 10 . To obtain this function, the bias circuit 19 includes resistors 20 and 21 connected in series,
One resistor 21 is formed in the same epitaxial layer as the Hall effect element 10.

The first stage amplifier is a transconductance amplifier with a voltage gain of 1 and a transfer fundance equal to the difference between the output currents of amplifiers 16 and 17 divided by the difference between the voltages of output terminals 11 and 12 of the Hall effect element. It is. Transconductance adjustment of the first stage amplifier is performed by a variable resistor 22, which is shown connected between the transconductance adjustment nodes across the resistor. The first stage amplifier further comprises an output offset adjustment circuit, shown as block 23, connected from the transconductance adjustment connection to ground 15.

The first amplifier stage generates a pair of currents 1 and 2, the difference in their currents representing the magnitude of the magnetic field applied to the Hall effect element 10. Current wires 1 and 2 create mutual congluctance adjustment junctions and current doubling, and currents 211 and 21. current mirrors 24 and 25 configured to flow the current to the second amplifier stage.

The second amplifier stage is a two-tone amplifier with a voltage gain of unity and a transfer resistance equal to the output voltage difference divided by the stage's input current difference. The second amplifier stage includes adjustment means 26 for adjusting the rate of change of the second stage mutual resistance with respect to temperature. As shown, the adjustment means 26 consists of two resistors 2T and 28 connected in series. The resistor 27 is formed in the same epitaxial layer as the Hall effect element 10.

will be accomplished.

The adjustment means 26 are connected between the emitters of a pair of NPN transistors 29 and 30 forming part of the second amplifier stage. The pace of the NPN transistor 29 is connected to zero adjustment means in the form of a voltage divider consisting of a variable resistor 31 and a fixed resistor 32 connected in series between the voltage source vs and the ground point 15. NPN transistor 2
Collectors 9 and 30 are connected to the non-inverting current input 91M of the differential amplifier 33 and the inverting current input terminal, respectively. The output signal of the differential amplifier 33 forms the output signal v0 at the output terminal 34 of the Hall effect element and is also fed back to the base of the NPN transistor 30.

The circuit diagram in Figure 2 shows a Hall effect element and its terminals,
a reference voltage source or ground point, two amplifiers forming a first amplifier stage, a resistor forming a bias circuit, a resistor for adjusting the transconductance of the first stage, two current mirrors, and a second amplifier stage. The resistors in the adjusting means in the second stage, the zero adjustment resistors, and the output terminals of the elements are indicated by the same reference numerals as in FIG. 1. In FIG. 2, 35 is a voltage supply conductor connected to a source of supply voltage v8, indicated as 36. Reference numeral 37 is a reference voltage source, that is, a reference voltage conducting wire connected to the ground point 15. The Hall effect element 10 is connected directly between the voltage supply conductor 35 and the reference voltage conductor 37 in order to achieve a ratio characteristic of sensitivity.

That is, the output voltage of the Hall effect element always changes by the same percentage as the supply voltage.

A ratio current source is further connected between the voltage supply conductor 35 and the reference voltage conductor 37, which in the preferred embodiment has a collector connected to the voltage supply conductor 35 via a resistor 39. It is composed of an NPN transistor 38. The base drive signal for NPN transistor 38 is provided via an NPN transistor 40 whose collector is connected to voltage supply conductor 35 via a resistor 41 in series with PNP transistor 42 . NPN
The base of transistor 40 is connected to the collector of NPN transistor 38, and its emitter is connected to the base of NPN transistor 38 to perform base current load compensation.

The emitter of NPN) transistor 40 is arranged as a diode.NPN) transistor 43 and resistor 44
It is also connected to the grounding point 15 (reference voltage conducting wire 3γ) via. The diode formed by NPN transistor 43 matches the characteristics of NPN transistor 38. N
The emitter of the PN) transistor 38 is connected to the ground point 15 via a resistor 45 and an NPN) transistor 46 arranged as a diode.

The base drive signal provided to NPN transistor 40 is also provided to NPN transistor 50. This NPN
The collector of the transistor 50 is connected to the voltage supply conductor 35 via a resistor 51 and a transistor 52 connected in series therewith, which can be arranged as a diode,
The emitter of the N transistor 50 is the NPN transistor 4
Connected to the emitter of 0. If the resistance of resistor 39 is twice the resistance of resistor 45, then the base of the transistor
It can be seen that the emitter voltages cancel each other out, and the voltage at the emitter of the NPN transistor 43 is independent of temperature and changes at a rate according to the supply voltage.

Amplifier 16 has first and second input terminals, the first input terminal being connected to output terminal 11 of Hall effect element 10 . A connection point 53 shared with the amplifier 17 is Ea
rly) connected to a ratio current source to perform effect compensation. A first input terminal of amplifier 17 is connected to output terminal 12 of Hall effect element 10 .

Amplifiers 16 and 17 are combined with variable control resistor 22 to form a voltage/current converter. This scheme makes the load current of the Hall effect element independent of both the gain resistor value and the input signal from the Hall effect element, as is necessary to achieve temperature independent sensitivity.

Variable resistor 22 is preferably an external thick film resistor that is laser trimmable. Amplifiers 16 and 17 form a balanced pair and, as explained in more detail below,
Cross-connected via an input offset adjustment circuit with cross-connect compensation.

The amplifier is connected in a configuration with a voltage gain of 1, and the voltage across the variable resistor 22 is equal to the output voltage of the Hall effect element. The signal produced by the first amplifier stage is the difference between the output currents produced by amplifiers 16 and 17 and is proportional to the voltage across variable resistor 22.

Although only amplifier 16 will be described in detail here, a preferred configuration of amplifiers 16 and 17 is such that the base electrode entirely forms the first input terminal of the amplifier, and the emitter electrode is connected to one end of variable resistor 22. It includes an NPN transistor 60. The collector of NPN) transistor 0 and the base of NPN) transistor 1 are connected to the input offset adjustment circuit.

The amplifier 16 further includes a PNP transistor 62 with multiple collectors, the emitter of which is connected to the voltage supply conductor 35 and the first collector 63 connected to its base. The first collector 63 is further connected to the collector of an NPN transistor 64 whose base is connected to the connection point 53 .

The second collector 65 of the PNP transistor 62 is an NPN
) is connected to the emitter of transistor 0 and supplies feedback current. A third collector 66 of transistor 62 generates a current that constitutes one input signal to the second amplifier stage. This output voltage is connected to the transistors 8 and NP connected to each other in order to produce the Early effect, i.e. base width modulation compensation with respect to temperature changes: PNP)
N) Supplied via Ranjistaro 7.

The current flowing through the collectors 65 and 66 of the transistor 62 is generated regardless of whether a magnetic field is applied to the Hall effect element 10 or not.

When no magnetic field is applied, the current required is temperature independent. When a magnetic field is applied, the portion of the current that is affected by the magnetic field is temperature dependent. Compensatory tracking with respect to the current bias of the differential transistor pair 61, 64 is performed by supplying the current bias through series connected bias resistors 20 and 21.

One resistor 21 is formed in an epitaxial layer. The bias current may be made to track the responsivity of the Hall effect element 10 by appropriately setting the resistance ratio of the resistors 20 and 21.

The bias current supply source is an NPN transistor 69. In detail, the collector of this transistor 69 is N
It is connected to the emitters of PN transistors 61 and 64, and the emitter of NPN transistor 69 is connected to ground point 15 through resistors 20 and 21. (NPN) transistor 9 is supplied by a reference circuit 70 which is used in conjunction with a corresponding transistor 69' in amplifier 17 and an output offset trim resistor as described below. A base drive current is also supplied to the current source transistor.

Ideally, amplifier 17 is identical to amplifier 16. However, variations in the manufacturing process are inevitable and some differences in performance parameters will occur. Furthermore, if the amplifier exhibits a small input offset voltage (1), the offset must be compensated because the output signal of the Hall effect element is small and requires high accuracy. For example, if the base-emitter voltage of NPN transistor 600 and the base-emitter voltage of corresponding NPN transistor 0' in the circuit of amplifier 17 are not equal, then
A temperature error term appears at the input to the first amplifier stage. Since this error appears in human effort, it becomes very significant due to circuit gain multiplication. Input offset adjustment is performed by trim resistor 71. A second trim resistor 72 may be provided to further facilitate input offset tuning.

The input offset adjustment circuit is a PN with two collectors.
P) includes transistors 3 and 74 and is combined with a cross-connected configuration that allows the current density of the base-emitter junctions of NPN transistors 60 and 6σ to be adjusted without disturbing the output balance.

Cross-connection is accomplished by keeping the difference in current flowing into the connection points across the variable resistor 22 constant and constant, regardless of the base-emitter current density. As the base-emitter current density in one of NPN transistors 60 and 60' is increased by trimming, the current flowing into the associated node of variable resistor 22 increases. However, since the circuit simultaneously applies the same amount of current to the other connection point of variable resistor 22, a continuous equilibrium condition is obtained.

PNP ) Collector 75 of Langistav 3 is NPN!
- Connected to the base of the Langisthu 6, hJPN) The emitter of the Langisthu 6 is connected to the collector of the NPN transistor 61' of the amplifier 17. The collector 75 is
NPN transistor 77 arranged as a diode
It is also connected to the collector of the NPN transistor 60 via. The collector 78 of the PNP) transistor 3 and one collector of the PNP) transistor 2' having a plurality of collectors of the amplifier 17 are connected to the connection point of the amplifier 17 at one end of the variable resistor 22.

Similarly, the collector 79 of PNP transistor 74 is NP
N is connected to the base of transistor 80, and the emitter of NPN transistor 80 is connected to the collector of NPN transistor 1 of amplifier 16.

The collector 79 is an NPN arranged as a diode.
It is also connected to the collector of NPN transistor 60' via transistor 81. PNP) The collector 82 of the Langstaff 4 and the collector 65 of the transistor 62 having multiple collectors of the amplifier 16 are connected to the variable resistor 22.
It is connected to the connection point of the amplifier 16 at the other end. NPN
) The collectors of the Langistavs 6 and 80 are connected to the voltage supply line 35 via resistors 83 and 84, respectively.

The base current of NPN) transistor 1 is approximately equal to the base current of NPN) transistor 80, and the base current of NPN) transistor 1' is approximately equal to the base current of NPN) transistor 6. NPN transistor GO
The collector load of is the NPN transistor 61 and the NPN
equal to the sum of the base currents of transistors 76. Similarly,
The collector load of NPN transistor 60' is equal to the sum of NPN transistor 61' and NPN) run raster 800 pace current. Therefore, the collector load currents of NPN transistors 60 and 60' are constrained to be equal to each other.

85 and 88 are capacitors that are combined with NPN transistors 76 and 80 and resistors 83 and 84 to perform frequency compensation for stable operation.

Diodes 81 and 77 bias transistors 6 and 80 (NPN) and capacitors 85 and 86.
to increase the capacitance per unit area, thereby facilitating current integration.

NPN) Transistor 7 and PNP transistor 68
compensates for the Early effect in PNP transistor 62 by providing collectors 65 and 66 with the same bias voltage temperature customization. Similarly, the NPN of amplifier 11
) Rangistaro 7' and PNP) Rangistaro 8'
performs a similar function with respect to PNP transistor 62'.

Next, temperature compensation of the total gain of the Hall effect element will be explained in rough detail. However, it should be pointed out here that in order to couple such compensation without zero shift, the voltage across resistors 27 and 28 must be zero when no magnetic field is applied. I'll keep it. This adjustment is performed by output offset trim resistors 92 and 93. A trim resistor 92 in series with current source transistor 94 is connected between a connection point at one end of variable resistor 22 of amplifier 16 and ground point 15 . Similarly, a trim resistor 93 in series with current source transistor 95 is connected between a connection point at the other end of variable resistor 22 of amplifier 17 and ground point 15 . Base drive signals for current source transistors 94 and 95 are provided by base circuit 70. Trim resistors 92 and 93 can be trimmed to adjust the voltage across resistors 27 and 28 to zero for zero condition temperature compensation.

The output signal currents of amplifiers 16 and 17 are suitably multiplied by current mirrors 24 and 25, preferably by a multiplier of 2, and fed to the second amplifier stage.

In the current mirror 24, an NPN transistor 100
and 101 form a conventional current mirror.

NPN) transistor 102 operates to compensate for the effects of base load current. NPN ) transistor 102
The emitter of is maintained at a voltage one emitter-base voltage drop above ground by transistors 103 and 104 arranged as series-connected diodes that can be supplied with a positive voltage bias via PNP transistor 105. Transistor 106 functions to compensate for the IJ-effect. Current mirror 25 is exactly the same as current mirror 24.

In the second amplifier stage, the input current difference is forced through resistors 27 and 28, thereby producing an output voltage that is related to an externally adjustable voltage at the zero circuit voltage divider junction. The zero circuit is designated by the reference numeral 108 in FIG. Zero circuit 108 connects voltage supply conductor 35 and ground point 15
The voltage divider includes an adjustable variable resistor 31 and a fixed resistor 32 connected in series between the two. PNP
Transistor 109 is combined with resistor 110 to
A current source that biases the NPN transistor 111 is formed.

NPN transistor 111 is current source transistor 112
The collector of transistor 112 is NP
N is connected to the base and collector of transistor 111, and the emitter of transistor 112 is connected to ground point 15 via resistor 113. Therefore, the load effect on the voltage divider can be made very small, and the effect of minimizing temperature drift of zero voltage can be obtained.

The voltage signal generated by the NPN) transistor 111 is transferred to the NP via the PNP) transistors 117 and 118.
It is supplied to the pace of N transistor 116. PNP
Transistor 117, along with NPN transistors 111 and 112, primarily provides output fault protection (
It is necessary to match the corresponding transistor to perform the output fault grotetanyon.

The emitter of NPN transistor 116 and the corresponding emitter of transistor 120 are connected across the series combination of resistors 27 and 28. Transistor 120 is connected to transistor configuration 1 from push-pull output circuit 122.
A feedback signal is received through a configuration of transistors 123-126 corresponding to transistors 11, 112, 117 and 118.

Transistors 123-125 are needed primarily to provide output fault protection. Voltage feedback to the base of transistor 120 causes the emitter currents of transistors 116 and 120 to be equal to each other. Therefore, when the output currents of current mirrors 24 and 25 are equal, no voltage drop occurs across resistors 21 and 28, and the output voltage V at output terminal 34.

is equal to the voltage at the zero circuit voltage divider junction.

The bases of transistors 116 and 120 are connected to the collector of a two-collector PNP transistor 128, and the emitter of PNP transistor 128 is connected to voltage supply conductor 35. transistors 116 and 120
The collector of can be connected to the voltage supply conductor 35 via a mutual fundance reduction circuit 130.

Mutual conductance reduction circuit 130 is necessary because if the input current to resistors 27 and 28 is too low, they would be required to have a large resistance and would consume too much chip area. .

However, the current at the base of the NPN transistor 1310 is reduced so that the compensation capacitor 132 can be made small in order to keep the chip area as narrow as possible while still being wide enough to generate a stable phase margin. Must be low. Therefore, preferably about 20.
Current reduction may be achieved by using a current mirror consisting of PNP transistors 133 and 134 with two collectors that produce a reduction of 1.

In case 7, the active load is formed by a current mirror consisting of NPN transistors 135 and 136. Transistor 137 compensates for the effects of base load current and also PNP transistor 133 to compensate for Early effects in PNF transistors 133 and 134.
On the other hand, the NPN transistor 131 provides the same collector bias 2 that is applied to the PNP transistor 134.

The NPN transistors 139 and 140, whose emitters are connected to the reference voltage conductor 37 via a resistor 141, form a current source connected to the emitters of the NPN transistors 131 and 137, providing even better early effect compensation. This helps to equalize the base-emitter voltage of the transistor.The current image area method is as follows:
The voltage fluctuation at the base of transistor 120 is expressed as PN
P can be larger than when using an active load. This is required to prevent transistor 120 from saturating when the output voltage is at the upper end of its range.

The push-pull output circuit 122 of the second amplifier stage is configured to eliminate crossover distortion. Scaling the pace emitter area of transistors in the circuit and NP
N) By setting appropriate values of the currents generated by transistors 142 and 143, the zero load dark current and maximum load current can be set to desired values.

The output circuit, together with the above-mentioned fault protection circuit, is designed to provide protection in the event of a break in the conductors from the external reference voltage source and supply voltage source to the terminals of the reference voltage conductor 37 and voltage supply source 36, or to the output terminal 34. , performs fault protection such that the voltage at the output terminal is approximately equal to the supply voltage or ground voltage. The circuit described above is required because substrate diode current must be prevented from reaching output terminal 34.

In particular, if the external conductor leading to the terminal of supply source 36 breaks, no current will be supplied to the circuit and the output of output terminal 34 will be connected to the external load resistor to ground. The voltage will be zero volts. The load resistor also pulls the output terminal 34 to zero volts if the wire between the push-pull output circuit 122 and the output terminal 34 breaks.

In the event of a break in the conductor connecting the reference voltage conductor 37 to ground, the substrate diode current can be blocked in order to provide fault protection. The substrate is connected to the ground point 15, and the Hall effect element 1o is connected between the terminal of the voltage supply source 36 and the ground point, so that a current path is established between the voltage supply terminal and the substrate. Transistor 144 in push-pull output circuit 122 is a PNP transistor, so its pace substrate diode current is blocked by the reverse biased pace-emitter junction. transistor 1450
Base current is blocked by PNP transistors 143 and 146 that pace drive. Further, since the feedback interface is formed by the PNP transistor 123, the substrate current does not flow to the output terminal 34. Therefore, in the event of a break in the external connection to reference voltage conductor 37, the output voltage will be zero volts.

Transistors 123, 124 and 125 and corresponding transistors 111, 112 and 117 serve to enable this fault protection. Without these transistors, output terminal 34 would be PNP transistor 1
If connected directly to the 260 base, the pace board diode would conduct current to the output terminal in the event of a break in the external connection to the reference voltage conductor 37.

According to the foregoing description, the present invention provides a unique Hall effect integrated circuit that produces a linear, highly accurate output signal over a wide temperature range, and is ideal for mass production at very low cost. I understand that. Although specific embodiments of the Hall effect device of the present invention have been illustrated and described for purposes of illustration, numerous modifications and changes will become apparent to those skilled in the art. It is intended that the scope of the invention be limited not to the specific embodiments illustrated, but only by the claims that follow.

[Brief explanation of drawings]

FIG. 1 is a functional diagram partially showing in block form a preferred embodiment of the Hall effect device according to the present invention, and FIG.
FIG. 2 is a schematic circuit diagram of the Hall effect element shown in the figure. 10...Hall effect element, 11.12...Output terminal, 13.14...Input terminal, 15...Grounding point, 16.17...Amplifier, 18,...・Input offset adjustment circuit, 19...bias circuit, 20.2
1...Resistor, 22...Variable resistor, 23...
... Output offset adjustment circuit, 24.25 ... Current mirror, 26 ... Adjustment means, 27.28 ...
Resistor, 29.30...NPN transistor, 31
...Variable resistor, 32...Fixed resistor, 33.
...Differential amplifier, 34...Output terminal, 35...
・Voltage supply conductor, 36...Supply voltage (V3) source, 3
7...Reference voltage conductor. Patent Applicant Honeywell Incorporated Sub-Agent Masaki Yamakawa (epi) 2 persons) 1. Indication of the case 1985 Patent Application No. C < OZ No. 3, Person making the amendment Relationship with the case Patent Applicant Name (Name) Heneziel Ishifu Ki Oshiichi Tesotopa 5;Date June 2nd, 1929 Showa et al.
−′ Party B, engraving of the details subject to amendment (no change in content)

Claims (2)

[Claims] (1) a substrate having an epitaxial layer on its upper surface; a substrate formed on the epitaxial layer, having first and second output terminals, and having a voltage difference indicating the magnitude of the applied magnetic field;
and a Hall effect element generated between the first and second output terminals of the Hall effect element, the Hall effect element being connected to the first and second output terminals of the Hall effect element and receiving a voltage difference generated in response to a magnetic field and capable of operating over a wide temperature range. a first resistive portion formed in the epitaxial layer and a second resistive portion having a constant temperature coefficient; and amplifier means including resistor means having a temperature compensated integrated circuit Hall effect element. (2) A temperature-compensated integrated circuit Hall effect element having a voltage supply terminal, a reference voltage terminal, and an output terminal, comprising: a substrate having an epitaxial layer on its upper surface; third and fourth terminals formed on the epitaxial layer; a Hall effect element operative to generate a voltage difference between the first and second terminals when a current is passed between them and subjected to the action of a magnetic field; a voltage supply connected to the voltage supply terminal; a conductor; a reference voltage conductor connected to the reference voltage terminal;
each having first and second input terminals, an input offset adjustment terminal, a temperature tracking bias terminal, and output terminal means, the first input terminal being connected to the first and second terminals of the Hall effect element. a first resistor connected to the substrate, an input offset adjustment terminal connected to the voltage supply conductor through first and second input offset adjustment circuits, respectively, and a temperature tracking bias terminal formed in an epitaxial layer of the substrate. a first and second voltage conductor connected to said reference voltage conductor through bias resistor means including a bias resistor means and whose output terminal means is connected to said reference voltage conductor through output offset adjustment means including an output offset adjustment resistor; a second ideally identical amplifier; a first gain control resistor connected between second input terminals of said first and second amplifier; first and second input terminals; , a zero level adjustment terminal, and an output terminal connected to the output terminal of the Hall effect element, and the zero level adjustment terminal is connected to the voltage supply conductor and the reference voltage conductor via a voltage divider. a third amplifier; a second gain control resistor including a first resistive portion formed in an epitaxial layer of the substrate and connected between the first and second input terminals of the third amplifier; a temperature compensated integrated circuit comprising: a first and second current mirror connecting output terminal means of the first and second amplifiers to first and second input terminals of the third amplifier, respectively; Hall effect element.