JPS61246835A - Pattern shift circuit - Google Patents

Abstract

PURPOSE:To decrease the time when pattern data is shifted and outputted by providing a register inputted with parallel pattern data, two ROMs having a program setting an output after shifting and an OR circuit. CONSTITUTION:Parallel pattern data (a) is inputted to a register 2 and a ROM 3 and the output pattern data of the register 2 is inputted to a ROM 1. In inputting a consecutive pattern data sequentially to the register 2 and a ROM 3 synchronously with a clock signal CL, the pattern data before one point of time in the ROM 3 is inputted to the ROM 1. Data (e) designating the pattern data and the shift bit number inputted to the ROMs 1, 2 is an address data of the ROMs 1, 3 and the output pattern data (c, b) corresponding to the address data are outputted. The output pattern data (c, b) of the ROMs 1, 3 are ORed by OR circuits 4a-4h and outputted as the output pattern data (d).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern data processing circuit, and more particularly to a circuit that shifts an entire pattern that exists continuously in word units in bit units.

[Conventional technology]

Conventionally, to perform this type of shift operation, a shift register is used to convert word-based pattern data into serial data, and then the serial data is edited again into word-based data by shifting the bits. I was trying to repair it.

[Problem that the invention seeks to solve]

The conventional pattern shift circuit described above has a problem in that it cannot perform high-speed processing because it repeats the shift operation by the number of bits of one word length when converting parallel data to serial data.

Means for Solving Problem C] In order to solve such problems, the present invention provides a first register having a register into which parallel pattern data is input and a program for presetting the output after shifting. ROM of
and a second ROM, and an OR circuit for calculating the logical sum of the outputs of the first ROM and the second ROM.

[Effect]

In the present invention, pattern data obtained by performing necessary shift operations on parallel pattern data is output.

〔Example〕

An embodiment of a pattern shift circuit according to the present invention is shown in FIG. In Figure 1, 1 and 3 are the second and first
ROM, 2 is a register, 4a to 4h are O to take the logical sum
This is an R circuit.

Next, the operation of the circuit configured in this way is shown in Figure 1.
This will be explained using FIG. Parallel pattern data a shown in FIG. 2(a) is input to the register 2 and the ROM 3. The clock signal CL of the register 2 is output from the OR circuit 43 to
The output cover turn data d output from the register 4h is synchronized with a signal to be written into a memory or the like, and the output cover turn data of the register 2 is input to the ROMI. Clock signal CL
Continuous pattern data is sent to registers 2 and R in synchronization with
When input to OM3, pattern data at a point before, that is, one word before, in ROM3 is input to ROMI. Data e specifying the number of shift bits (within word length) is also stored in ROM1. It is input to ROM3. The pattern data and shift bit number data e input to ROMI and ROM3 become the address data of ROMI and ROM3, and the output pattern data c and b (see Figure 2 (01, (bl)) according to this address data are ROM1.R
Output from OM3. The output turn data b of ROM3 and the output turn data C of ROMI are connected to the OR circuit 43~
At step 4h, a logical sum is performed and the output pattern data d shown in FIG. 2(d) is output.

Next, the operation of this circuit will be explained using parallel pattern data a shown in FIG. 2(a) as an example. In Figure 2, A,
B represents a word, and word A is a word immediately before word B. In the example of FIG. 2, the number of shift bits is 3 bits. ROM3 uses input pattern data a and shift bit number data e as address data, and outputs pattern data b according to an internal program.
Determine. This pattern data b includes bits b of word A of pattern data a, as shown in Figure 2).
Shift b4 to the right by 3 bits, ~b? As a bit,
The value of bits b0 to b2 is set to "0". Thereafter, similar processing is repeated to obtain bit b0 of pattern data a.
Output pattern data b obtained by shifting ~b4 to the right by 3 bits. Although this pattern data b has been shifted, the word itself is at the same point in time as pattern data a, and the word is not shifted.

The pattern data a is input to the ROMI with a delay of one word. That is, at the time of word B in FIG.
OM3 processes data in word B, but ROMI processes data in word B.
Process the data of word A that is delayed by a word. The data of word A of pattern data a delayed by one word is similarly shifted to the right by three bits. That is, word A of pattern data a is ~b? The bit data becomes the data of word B of pattern data C, .about.b2 bits. The values of bits b3 to b of word B of pattern data C are set to "0". Thereafter, similar processing is repeated to output pattern data C in which bits b, .about.b of pattern data a are shifted to the right by 3 bits. Note that, as described above, the pattern data C output from the ROMI is pattern data delayed by one word from the pattern data a.

Next, in the OR circuits 4a to 4h, the output cover turn data C of ROMI and the output cover turn data b of ROM3
As shown in FIG. 2(d), output pattern data d, in which pattern data a is shifted to the right by 3 bits, can be obtained.

In the above example, pattern data a is shifted to the right by 3 bits to obtain output pattern data d, but when shifted by 3 bits to the left, shift bit is used.

The data e representing the number of bits may be set to 5 bits, and the second word of the output pattern data d may be made valid.

(Effects of the Invention) As described above, the present invention has a register into which parallel pattern data is input, a first ROM having a program for presetting the output after shifting, and a second (7) ROM.
By providing an OM and an OR circuit that takes the logical sum of the outputs of the first (7) ROM and the second ROM, the time required to shift and output the input pattern data can be shortened. effective.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a pattern shift circuit according to the present invention, and FIG. 2 is a data state diagram for explaining the operation of this circuit. 1.3...ROM, 2...Register, 4a-4
h...OR circuit.

Claims (1)

[Claims] a register into which parallel pattern data is input; a first ROM having a program for presetting the output after shifting; and into which the parallel pattern data and a signal representing the number of shift bits are input; a second ROM that has a program for presetting subsequent outputs and receives signals representing the output of the register and the number of shift bits;
and an OR circuit that takes the logical sum of the outputs of the first ROM and the second ROM, and outputs pattern data obtained by performing a necessary shift operation on the parallel pattern data. pattern shift circuit.