JPS61246684A - Generator for desired frequency signal - Google Patents

Abstract

PURPOSE:To elevate the frequency as desired keeping the phase accuracy of the frequency signal generated as it is, by arranging an extraction filter to turn a desired frequency component to that intended for the generation of the extraction signal from the output frequency signal of a mixing circuit. CONSTITUTION:After the frequency division of a pulse train of a clock pulse source 1 with a frequency dividing circuit 2, the pulse train thus divided is counted with a counter 3 to read out a memory data at a memory address of a read-only-memory 4 corresponding to the counts. Then, memory outputs of respective bits are latched into latch circuits 601-608 from which output multi-phase frequency signals of 8 channels are outputted. Frequency signals of 8 channels outputted in a square wave train from the circuits 601-608 are introduced to exclusive OR circuits 701-708 respectively to be mixed with a mixing signal outputted from a mixing signal generation circuit 8. Then, the frequency signals resulting from the mixing with the circuits 701-708 are subjected to filters 901-908 to extract specified frequency signals respectively.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to generating frequency signals whose frequency or phase changes over time, and further relates to generating multiple frequency signals having a phase relationship with each other. The present invention relates to an apparatus suitable for use in the case of phase generation.

(Prior art) The applicant has proposed a device of this type in Japanese Patent Application No. 57-13814.
No. 1 and Japanese Patent Application No. 137745/1983.

The present invention relates to an improvement on the above-mentioned conventional device.

In the conventional device described above, generation of the frequency signal is performed by sequentially reading out stored data written in the storage circuit.

The frequency of the generated frequency signal is limited by phase accuracy, that is, phase resolution. This is due to the access time of the memory circuit.

When reading data stored in a memory circuit, a time lag occurs due to access time. For example, the access time is 1.
In the case of the most widely used MOS type ROM (read-only memory), it has about 20 Or+sec. Therefore,
When the above-mentioned frequency signal is generated using this storage circuit, the phase of the generated frequency signal cannot be resolved into 200 nsec or more.

In addition, in the above device previously provided by the applicant, in order to generate a practical frequency signal, the frequency of the frequency signal stand is as follows. Therefore, in the case of the above conventional device, the frequency is 78.125K.
It is not possible to generate a frequency signal higher than Hz.

(Problems to be Solved by the Invention) This invention improves the conventional device described above to realize a device that can arbitrarily increase the frequency while maintaining the phase accuracy of the generated frequency signal as described above. .

(Means for Solving the Problem) As a means for solving the problem, there is provided a storage circuit that generates a frequency signal when stored data is read;
A generation circuit for a mixed signal to be mixed with the generated frequency signal, a mixing circuit for mixing the generated frequency signal and the mixed signal, and a filter for extracting a specific frequency signal from the mixed signal of the mixing circuit. provided.

(Function) In the same manner as in the conventional device described above, the stored data is read out from the memory circuit and a frequency signal is generated. The generated frequency signal is mixed with a separately generated mixed signal in a mixing circuit, and a specific frequency signal is extracted from the mixed signal in a filter. Then, the extracted signal extracted by the filter is output as a desired frequency signal.

(Embodiment) In FIG. 1, a clock pulse source 1, a frequency dividing circuit 2, a counter 3, a read-only memory 4, a latch pulse generation circuit, and latch circuits 801 to 608 are configured to generate multiphase frequency signals in the same way as in the conventional device. generate. In FIG. 1, each of the latch circuits 801 to 1308 outputs a frequency signal, thereby generating eight channels of multiphase frequency signals. That is, the pulse train of the clock pulse source 1 is frequency-divided by the frequency dividing circuit 2 and then counted by the counter 3.

The counter 3 counts the frequency-divided pulse train and reads out the stored data at the storage address of the read-only memory 4 corresponding to the counted value.

The read-only memory 4 outputs 8-bit storage data every time a storage address is specified by the counter 3, and the storage output of each bit is sent to the latch circuits 601 to 60.
8, the latch circuits 801 to 8
08 to 8 channels of multiphase frequency signals are output. Note that the latch circuits 801 to 808 latch the stored data read from the read-only memory 4 in synchronization with the read operation using the latch pulse output from the latch pulse generation circuit 5. Further, the multiphase frequency signals outputted from the latch circuits 801 to 808 are outputted as a rectangular wave train, similar to the conventional device described above.

The eight channels of frequency signals output from the latch circuits 801 to 808 in the form of rectangular wave trains are transmitted to the exclusive OR circuit 7.
01 to 708, and are mixed with the mixed signals output from the mixed signal generation circuit 8. Then, from each frequency signal mixed by the exclusive OR circuit, a specific frequency signal is extracted by each of filters 901 to 808.

For example, one of the outputs of the latch circuits 801 to 808.

If the output frequency signal of the latch circuit 801 is 5 inches (ω.t+01) and the output frequency signal of the mixed signal generation circuit 8 is 5 inches (ω.t+θp), then the output frequency signal of the exclusive OR circuit 702 is 5 inches (ωct+θ). ,)
t(ω.+ω,)1+(θ1+θ,) ) ] −−−
-Represented by ■.

In addition, the output frequency signal of the latch circuit 802 is set at 5 inches (ωct
+θp, the output frequency signal of the exclusive OR circuit 702 is 5in(ωct+θpXsin(ω.t+θp=4
[cos(((1).−(1)O)t + (θ2−θ
ρ)−cos((ω.+ωρt+(0□10,) )
] −−−−■.

Exclusive jib 0R701°7 expressed by the formula ■,■
Assuming that the sum frequency component (ω.+ωp is extracted from the output frequency signal of 02 in filters 901 and 902,
The filter 901 outputs a frequency signal of ((ω.+ω, 3t+(θ1−θp)), and the filter 802 outputs a frequency signal of (((ω.+ω, 3t+(θ1−θp)).
ω. +ω, )1+(θ2−θp) A frequency signal is output.

Therefore, when the output frequency signals of filters 901 and 802 are compared with each other, the frequencies of both are (ω.+ωp), and the phase difference between the station wave number signals is (θ2−01).

On the other hand, when the output frequency signals of the latch circuits 801 and 602 are compared with each other, as is clear from the above, both frequencies are ω, and the phase difference between the image frequency signals is (θ2−01).

As is clear from this, the output frequency signals of the filters 901 and 902 have the same relative phase relationship with respect to the output frequency signals of the latch circuits 801 and 1302, and only the frequency is ω. It can be seen that the value changes from (ω.+ωp).

Similar frequency signals are also output from the other filters 803 to 908.

Therefore, the output frequency signals of the filters 901 to 808 have the same phase relationship as the output frequency signals of the latch circuits Ei01 to 808, and differ only in frequency.
The output frequency signals of the filters 901 to 808 can be used instead of the output frequency signals of the filters 901 to 808. As is clear from the above, the output frequency signals of the filters 801 to 908 can be set to arbitrary frequencies by changing the frequency output from the mixed signal generation circuit 8.

In FIG. 1, the phase relationship of the output frequency signals of the filters 901 to 808 is the same as that of the latch circuits 801 to 608.
The phase relationship of the output frequency signals of
By arbitrarily setting the phase of the mixed signals guided to each of the signals 708 to 708, an arbitrary phase relationship can be established.

(Effects of the Invention) As described above, according to the present invention, an arbitrary frequency signal can be generated by using a relatively inexpensive exclusive OR circuit as a mixing circuit. The phase accuracy can be maintained to be the same as that of the frequency signal generated by the read-only memory.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the invention. l...Clock pulse generation circuit, 2...
・Frequency divider circuit, 3... Counter, 4...
・Read-only memory, 5... Latch pulse generation circuit, 601 to θ08... Latch circuit, 70
1 to 708...Exclusive OR circuit,
8...Mixed frequency signal generation circuit, 801 to 90
8...Filter

Claims (1)

[Scope of Claims] A clock pulse train generation circuit that generates a clock pulse train with a cycle sufficiently smaller than the cycle of a predetermined specific frequency signal, a counting circuit that counts the clock pulse train, and a count value of the counting circuit. When the stored data at the specified storage address is read out and the read stored data changes in response to the change in the count value, the stored data is adjusted to each storage address so that the data change matches the specific frequency signal. a storage circuit written in a memory circuit, a generation circuit for a mixed frequency signal to be mixed with the specific frequency signal, a mixing circuit for mixing the mixed frequency signal and the specific frequency signal, and an output frequency signal of the mixing circuit. 1. An arbitrary frequency signal generation device, comprising: a filter for extracting a desired frequency component therein; and outputting a signal extracted by the filter as a frequency signal to be generated.