JPS61244129A - Transmission system for analog signal - Google Patents

Transmission system for analog signal

Info

Publication number
JPS61244129A
JPS61244129A JP8535685A JP8535685A JPS61244129A JP S61244129 A JPS61244129 A JP S61244129A JP 8535685 A JP8535685 A JP 8535685A JP 8535685 A JP8535685 A JP 8535685A JP S61244129 A JPS61244129 A JP S61244129A
Authority
JP
Japan
Prior art keywords
analog signal
value
dac
digital
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8535685A
Other languages
Japanese (ja)
Inventor
Fumio Nagasaka
文雄 長坂
Hiroshi Watanabe
裕志 渡辺
Shinichi Akano
赤野 信一
Hiroshi Okaniwa
岡庭 広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azbil Corp
Original Assignee
Azbil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azbil Corp filed Critical Azbil Corp
Priority to JP8535685A priority Critical patent/JPS61244129A/en
Publication of JPS61244129A publication Critical patent/JPS61244129A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To send out an analog signal with high resolution by using an inexpensive DAC which has a small number of input bits by calculating a large and a small digital signal value which are closest to an analog signal value to be sent out according to the number of input bits of the DAC and supplying them to the DAC alternately. CONSTITUTION:A fixed memory ROM 2, a variable memory RAM 3, timer TIMs 4 and 5, and interface I/Fs 6 and 7 are arranged at the periphery of a CPU 1 such as a microprocessor and connected by a bus; the I/F 6 is supplied with input data D1 and the I/F 7 sends output data with a digital signal (d). Then, the data is converted by the DAC 8 into an analog signal (a), which is averaged by an averaging circuit 9 using an integration circuit, etc., and sent out as an analog signal a0. In this case, the DAC 8 is supplied with digital signals of the large and small values which are closest to the analog value to be sent out alternately as a specific duty ratio according to the number of input bits.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ディジタル信号をディジタル・アナログ変換
器によりアナログ信号へ変換して送出する方式に関する
ものでおる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for converting a digital signal into an analog signal using a digital-to-analog converter and transmitting the analog signal.

〔従来の技術〕[Conventional technology]

ディジタル信号をアナログ信号へ変換して送出する場合
、一般にディジタル・アナログ変換器(以下、DAC)
が用いられており、この際には、送出するアナログ信号
の変化状況を如何に細分化して示す必要があるかにした
がい、この分解能に応じた入力ビット数を有するDAC
を用いるものとなっている。
When converting a digital signal into an analog signal and sending it out, a digital-to-analog converter (hereinafter referred to as DAC) is generally used.
In this case, a DAC with the number of input bits corresponding to this resolution is used, depending on how finely it is necessary to show the changes in the analog signal to be sent.
is used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、アナログ信号の分解能を高精度とするには、こ
れに応じて入力ビツト数の多いDACを用いねばならず
、これにしたがってDACが高価となる問題を生じてい
る。
However, in order to improve the resolution of analog signals with high accuracy, it is necessary to use a DAC with a correspondingly large number of input bits, resulting in the problem that the DAC becomes expensive.

〔問題点を解決するための手段〕[Means for solving problems]

前述の問題を解決するため、本発明はつぎの手段により
構成するものとなっている。
In order to solve the above-mentioned problem, the present invention is constructed by the following means.

すなわち、上述の方式において、DACの入力ビツト数
に応じ、送出するアナログ信号値に最も近くかっ大きな
値および小式な値のディジタル信号値を求め、これらの
大きな値および小さな値のディジタル信号を交互にDA
Cへ与え、このDACの出力を平均化して送出するアナ
ログ信号とし、かつ、このアナログ信号の値が送出する
アナログ信号値となるデユーティ比として大きな埴およ
び小さな値のディジタル信号をDACへ与えるものとし
ている。
That is, in the above method, the digital signal values of the large value and small value that are closest to the analog signal value to be sent are determined according to the number of input bits of the DAC, and these digital signal values of the large value and small value are alternately transmitted. To DA
C, the output of this DAC is averaged and sent as an analog signal, and the value of this analog signal becomes the analog signal value to be sent.As a duty ratio, a digital signal with a large value and a small value is given to the DAC. There is.

〔作 用〕[For production]

したがって、DACの出力側へ積分回路等を挿入し、D
ACの出力を平均化すれば、送出するアナログ信号値が
得られると共に、DACには、これの入力ビツト数に応
じ、送出するアナログ値に最も近くかつ大きな値および
小さな値のディジタル信号を所定のデユーティ比として
交互に与えればよいものとなる。
Therefore, by inserting an integrating circuit etc. on the output side of the DAC,
By averaging the output of the AC, the analog signal value to be sent out can be obtained, and the DAC also has a predetermined digital signal that is closest to the analog value to be sent out, and has a large value or a small value, depending on the number of input bits. It is sufficient if they are given alternately as the duty ratio.

〔実1!A例〕 以下、実施例を示す図によって本発明の詳細な説明する
[Act 1! Example A] Hereinafter, the present invention will be described in detail with reference to figures showing examples.

第2図はブロック図を示し、マイクロプロセッサ等のプ
ロセッサ(以下、CPU ) 1を中心とし、固定メモ
リ(以下、ROM ) 2、可変メモリ(以下、RAM
 ) 3、タイマー(以下、TIM)4.5およびイン
ターフェイス(以下、I/’F ) 6 、7を周辺に
配し、これらを母線により接続しており、I/F6には
入力データDiが与えられ、I/F7からは出力データ
がディジタル信号dにより送出されたうえ、DAC8に
よシアナログ信号畠へ変換式れ、これが積分回路等を用
いた平均化回路9により平均化てれ、アナログ信号龜。
Figure 2 shows a block diagram, centered around a processor such as a microprocessor (hereinafter referred to as CPU) 1, a fixed memory (hereinafter referred to as ROM) 2, and a variable memory (hereinafter referred to as RAM).
) 3, a timer (hereinafter referred to as TIM) 4.5 and interfaces (hereinafter referred to as I/'F) 6 and 7 are arranged around the circuit, and these are connected by a bus bar, and input data Di is given to I/F6. The output data is sent from the I/F 7 as a digital signal d, which is converted into an analog signal by the DAC 8, which is averaged by an averaging circuit 9 using an integrating circuit, etc., and converted into an analog signal. The barrel.

とじて送出されるものになっている。It is designed to be sent out in a closed format.

こ\において、CPU1はROM2中の命令を実行し、
必要とするデータをRAM3に対してアクセスしながら
制御および演算を行なっており、入力データD1に基づ
く演算によりアナログ信号a0の値を求め、これの送出
をディジタル信号dにより行なっているが、DAC8と
しては、例えば入力ビツト数が4ビツトのものを用いて
おシ、アナログ信号a0の必要とする分解能を実現する
には不十分な入力ビツト数となっている。
At this point, CPU1 executes the instructions in ROM2,
Control and calculation are performed while accessing the necessary data to RAM3, and the value of analog signal a0 is obtained by calculation based on input data D1, and this is sent out using digital signal d. For example, if the number of input bits is 4 bits, the number of input bits is insufficient to realize the resolution required for the analog signal a0.

このため、DAC8の入力へ与えられるディジタル信号
dの値dn と、これから得られるアナログ信号aの値
&。との関係は第3図のとおりであり、dn=15をa
nの100俤とすれば、drh=7のときa n= 4
6.7 %、dn=8のとき1n=53.3%となり、
an=50%のアナログ信号anを得ることができない
Therefore, the value dn of the digital signal d given to the input of the DAC 8, and the value & of the analog signal a obtained therefrom. The relationship with is as shown in Figure 3, and dn=15 is a
If n is 100 yen, when drh=7, a n= 4
6.7%, when dn=8, 1n=53.3%,
It is not possible to obtain an analog signal an of an=50%.

したがって、an=50チを得るには、第4図のとおり
、1周期化。を期間Xおよび期間yにより分割し、期間
Xにおいて、i n =50 %  K最も近くかつ小
石な値のディジタル信号値dl(7=46.7%)をD
AC8へ与え、期間yにおいては、atl=50%に最
も近くかつ大きな値のディジタル信号値dl+、(8=
53.3%)をI)AC8ヘ与え、これを各々x:y=
1:1のデユーティ比によシ交互に反復すれば、これに
応じたアナログ信号11および町ヤ、が平均化回路9に
より平均化され、平均値a0は50チとなる。
Therefore, to obtain an=50chi, one period is required as shown in FIG. is divided by period X and period y, and in period
In the period y, the digital signal value dl+, which is closest to atl=50% and has a large value, is given to AC8, (8=
53.3%) to I) AC8, and each x:y=
By repeating alternately with a duty ratio of 1:1, the corresponding analog signals 11 and 2 are averaged by the averaging circuit 9, and the average value a0 becomes 50.

すなわち、to=100%としたとき、X”−y−50
%であり、aoは各期間x、yの面積平均値となるため
、 46.7 X −+ 53.3 x賃i= 50 (%
)・・・(1)となり、&11&i+□と対応するdi
ldl+1をDAC8の入力ビット数に応じて求め、こ
れらを&i 、ILi+1の平均値a0が所望のアナロ
グ信号値となるデユーティ比により反復すれば、送出す
べき値のアナログ信号a0が得られる。
That is, when to=100%, X"-y-50
%, and ao is the area average value of each period x, y, so 46.7 X − + 53.3 x rent i = 50 (%
)...(1), and di corresponding to &11&i+□
By determining ldl+1 according to the number of input bits of the DAC 8 and repeating these with a duty ratio such that the average value a0 of &i and ILi+1 becomes a desired analog signal value, an analog signal a0 of the value to be sent can be obtained.

したがって、(1)式を一般化すれば次式が成立する。Therefore, by generalizing equation (1), the following equation holds true.

) ・・・・(2) x+y=100 (2)式からXおよびyを求めると、次式が得られる。)...(2) x+y=100 When X and y are determined from equation (2), the following equation is obtained.

)’=100−x            ・・・・(
4)このため、例えば、a0=51  とすれば、dl
−46,7チ、a、、=53.3%であり、(35式か
ら、y = 100−34.4=65.6  (チ)の
デユーティ比により、各ディジタル信号値dl。
)'=100-x ・・・(
4) Therefore, for example, if a0=51, dl
-46.7chi, a, , = 53.3%, and (from formula 35, each digital signal value dl.

d1+1t−DAC8へ交互に与えればよいものとなる
It is sufficient to alternately apply the signals to d1+1t-DAC8.

第1図は、CPU1による制御および演算状況のフロー
チャートであり、′イニシャライズ” 101により各
部の初期化を行なってから、入力データD1に基づく“
a0演算” 102を行ない、これに応じて” dl、
di+1を求める”111を行なったうえ、これらのd
l 、d1+1およびaoを用い、(3)式による′X
演算”112を行ない、”TIM4 ヘxセットl11
21およびTIM5へt。セット”122を行なった後
、”TIM4.5スタート°°123を行なう。
FIG. 1 is a flowchart of the control and calculation status by the CPU 1, in which each part is initialized by 'Initialize' 101, and then 'Initialize' is performed based on the input data D1.
Perform a0 operation "102" and accordingly "dl,
In addition to performing “111 to find di+1”, these d
'X according to equation (3) using l, d1+1 and ao
Perform operation "112," TIM4 hex set l11
21 and to TIM5. After performing the set "122", perform the "TIM4.5 start °°123".

ついで“dl送出” 131をI/F 7から行ない、
“TIM4タイムアツプ?”132がY(YES)とな
れば、′dl+、送出’ 141を行ない、T IM5
タイムアツプ?″142のYに応じ、入力データ“Di
変化? ” 151をチェックし、これがN(No)の
間はステップ121以降を反復するのく対し、ステップ
151がYとなればステップ102以降を反復する。
Next, perform “dl sending” 131 from I/F 7,
If “TIM4 time up?” 132 is Y (YES), perform ``dl+, send'' 141, and TIM5
Time up? According to Y of ``142, input data ``Di
change? ” 151 is checked, and while this is N (No), steps 121 and subsequent steps are repeated, whereas if step 151 is Y, steps 102 and subsequent steps are repeated.

なお、ステップ111は、第3図の関係をROM2また
はRAM3ヘテーブルとして格納のうえ、これを用いて
求め、または、DAC8の入力ピット数に応じた各入力
ディジタル値と10 との逐次比較により求めるものと
すればよい。
In step 111, the relationship shown in FIG. 3 is stored as a table in the ROM 2 or RAM 3 and calculated using this table, or by successive comparison of each input digital value corresponding to the number of input pits of the DAC 8 with 10. And it is sufficient.

したがって、第3図のディジタル入力値dnと対応する
アナログ出力値&。以外の中間値も送出が自在となり、
DAC8として入力ビツト数の少ない安価なものを用い
て十分となる。
Therefore, the digital input value dn in FIG. 3 and the corresponding analog output value &. You can also send intermediate values other than
It is sufficient to use an inexpensive DAC 8 with a small number of input bits.

たソし、TIM4 、5をCPU1およびRAM3によ
りソフト的に構成してもよく、期間yも演算してTIM
5へこれをセットし、ステップ132のYに応じてスタ
ート嘔せても同様である。
Alternatively, TIM4 and TIM5 may be configured by software using CPU1 and RAM3, and the period y is also calculated to configure TIM4 and TIM5.
The same effect can be obtained by setting this to 5 and starting in response to Y in step 132.

また、平均化回路9には、抵抗器およびコンデンサによ
る積分回路のほか、演算増幅器を用いた積分器等を用い
、または、低域F波器等を用いてもよく、贅にCPU1
を用いず、各種の演算回路および論理回路により同等の
ものを構成しても同様であり、第1図においては、ステ
ップ112を″y演算”とし、これに応じてステップ1
21を“yセット′°とすればよい等、種々の変形が自
在である。
Further, in addition to an integrating circuit using a resistor and a capacitor, the averaging circuit 9 may also use an integrator using an operational amplifier, or a low-frequency F-wave device, etc.
The same effect can be achieved by constructing equivalent circuits using various arithmetic circuits and logic circuits without using
Various modifications can be made, such as setting 21 to "y set'°.

〔発明の効果〕〔Effect of the invention〕

以上の説明により明らかなとおり本発明によれば、少な
い入力ビツト数の安価なりACを用いて高分解能のアナ
ログ信号が送出できるため、ディジタル信号をDACに
よりアナログ信号へ変換して送出する各種の用途におい
て顕著な効果が得られる。
As is clear from the above explanation, according to the present invention, a high-resolution analog signal can be sent using an inexpensive AC with a small number of input bits, so it can be used for various applications in which a digital signal is converted into an analog signal using a DAC and then sent. Remarkable effects can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の実施例を示し、第1図は制御および演算状
況のフローチャート、第2図はブロック図、第3図はD
ACの入力値と出力値との関係を示す図、第4図はディ
ジタル信号の送出状況を示す図でおる。 1・・・・CPU (プロセッサ)、4.5・・・・T
IM (タイマー)、8・・・・DAC(ディジタル・
アナログ変換器)、9・・・・平均化回路。
The figures show an embodiment of the present invention, in which Figure 1 is a flowchart of control and calculation status, Figure 2 is a block diagram, and Figure 3 is a D
FIG. 4 is a diagram showing the relationship between the input value and the output value of the AC, and FIG. 4 is a diagram showing the transmission status of the digital signal. 1...CPU (processor), 4.5...T
IM (timer), 8...DAC (digital
analog converter), 9...averaging circuit.

Claims (1)

【特許請求の範囲】[Claims] ディジタル信号をディジタル・アナログ変換器によりア
ナログ信号へ変換して送出する方式において、前記ディ
ジタル・アナログ変換器の入力ビット数に応じ送出する
アナログ信号値に最も近くかつ大きな値および小さな値
のディジタル信号値を求め、これらの大きな値および小
さな値のディジタル信号を交互に前記ディジタル・アナ
ログ変換器へ与え、該変換器の出力を平均化して送出す
るアナログ信号とし、かつ、該アナログ信号の値が前記
アナログ信号値となるデューティ比として前記大きな値
および小さな値のディジタル信号を前記ディジタル・ア
ナログ変換器へ与えることを特徴とするアナログ信号送
出方式。
In a method in which a digital signal is converted into an analog signal by a digital-to-analog converter and sent out, a digital signal value that is closest to the analog signal value to be sent out according to the number of input bits of the digital-to-analog converter, and has a large value or a small value. , and alternately apply these large value and small value digital signals to the digital-to-analog converter, average the output of the converter to make an analog signal to be sent out, and the value of the analog signal is equal to the analog signal. An analog signal sending system characterized in that the digital signals of the large value and the small value are given to the digital-to-analog converter as duty ratios serving as signal values.
JP8535685A 1985-04-23 1985-04-23 Transmission system for analog signal Pending JPS61244129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8535685A JPS61244129A (en) 1985-04-23 1985-04-23 Transmission system for analog signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8535685A JPS61244129A (en) 1985-04-23 1985-04-23 Transmission system for analog signal

Publications (1)

Publication Number Publication Date
JPS61244129A true JPS61244129A (en) 1986-10-30

Family

ID=13856414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8535685A Pending JPS61244129A (en) 1985-04-23 1985-04-23 Transmission system for analog signal

Country Status (1)

Country Link
JP (1) JPS61244129A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281844A (en) * 2006-04-06 2007-10-25 Texas Instr Japan Ltd Method and apparatus for generating weight level

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281844A (en) * 2006-04-06 2007-10-25 Texas Instr Japan Ltd Method and apparatus for generating weight level

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