JPS6124324A - Check circuit of digital timer - Google Patents

Abstract

PURPOSE:To detect a defective digital timer with a simple circuit by giving a check command at the same time to >=2 of plural digital timers constituted that an output of the check command and an output of a settling circuit are switched to a signl simulating circuit to which a predetermined signal is given. CONSTITUTION:When a check command is given, an output of an NOT8 goes to logical ''0'', an output of AND 61, 62 goes to logical ''0'' and no output of the settling circuit 3 is inputted to a comparator circuit 4. On the other hand, an output of the signal simulating circuit 7 is inputted to the comparator circuit 4 since the check command is logical ''1'' via AND 63, 64 and a timer output is obtained when an output of a counter circuit 2 and an output of the signal simulating circuit 7 are coincident. In detecting the time error of three digital timers, a check command is inputted to on-delay timers 51-53 at the same time. When the time tT decided by the signal simulating circuit 7 due to defective counter circuit in the timer 53 is decreased to tT', a signal ahving a time difference between the tT and tT' is given to a timer 20 and when this value is larger than t0, it is decided as a defective digital timer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital timer inspection circuit.

[Technical Background of the Invention 1 A digital timer consists of an oscillation circuit that generates a reference pulse, a counting circuit that counts the output of this oscillation circuit, a setting circuit that sets the timer time limit, and a combination of the output of the counting circuit and the output of the setting circuit. It consists of a comparator circuit that performs comparison, and a counting circuit counts the reference pulse, and after a certain period of time, the comparator circuit detects and outputs that the output of the counting circuit and the output of the settling circuit match. Common.

FIG. 2 is an example of the above-mentioned general digital timer. In FIG. 2, an oscillation circuit 1 is connected to the counting input terminal of the counting circuit 2 through one input of AND6, and a timer start command is connected to the reset terminal of the counting circuit 2. 3 is a setting circuit using a digital switch, and comparison circuit 4
The output of the aforementioned counting circuit 2 is connected to the second input terminal of the comparator circuit 4. The output of the comparator circuit 4 is NOT
5 to the other input of AND2.

To explain the operation of the circuit shown in Figure 2, the output pulse of oscillation circuit 1 is input to counting circuit 2 via AND6, but if the timer start command is "0", counting circuit 2 remains reset. The timer start command is “1” without counting up to
”, the counting circuit 2 starts counting. The output of the counting circuit 2 and the output of the setting circuit 3 are input to a comparison circuit 4,
When both inputs do not match, the comparator circuit 4 outputs "0" to the timer output, and when both inputs match, it outputs "1" to the timer output, and at the same time outputs the input of 8ND6 via N0T5. rOJ to prevent the output pulse of the oscillation circuit 1 from being input to the counting circuit.

Therefore, the output of the counting circuit does not change, and the timer output is "
1" continues, and when the timer start command becomes "0", the counting circuit is reset and its output becomes "0", and the output of the comparison circuit also becomes "0" and the timer is reset.

Here, the inspection circuit for detecting the time error of the timer shown in FIG. 2 will be explained with reference to FIG. 3. FIG. 3 is a circuit for detecting the time error of three digital timers.
Timer start command A is connected to the timer start terminal of on-delay timer 11.21 via OR circuit 41, and timer start command B is connected to on-delay timer 12.22 via OR circuit 42. C is OR circuit 4
3 to the on-delay timer 13.23. An inspection command is given to the other pano of the OR circuits 41, 42, 43. On-delay timer 11.21 timer output] GEL EXCLtlSIVE 0R31, on-delay timer 12.22 timer output is EXC
LUSIVE OOR32k, Ontilay timer 13
．． 23 Tsuta-1'``';' Output G, t EXCLI
ISIVE OOR33k input, EXCLUSI
V[0R31, 32, 33 are connected to the delay timer 20 through 0R44.

The response of the circuit shown in FIG. 3 will be explained using the time chart shown in FIG. In FIG. 3, the on-delay timer 11
．． 12.13 are set to different time periods t1, t2, t3, and the on-delay timers 21.22.23 are set to tl', respectively.
, t2', t3', and tl and tl',
Although t2 and t2' and t3 and t3' are set at the same level, due to an error at the start of counting, there are differences between the mouth and tl', and t2 and t2'.
, t3 and t3', an error time Δt occurs. E
The output of XCLUSIVE 31.32.33 becomes "1" only during the m period when the outputs of the on-delay timers 11, 21.12, 22.13, and 23 do not match, and goes through the OR circuit 44 to start the on-delay timer 20. . Since the time limit to of the on-delay timer 20 is set to [0>3Δt, no output is generated during the above-mentioned error time Δt. When inspection commands are input to 0R41, 42, 43 at the same time, on-delay timers 11.12.13.21.
When 22.23 is normal, only 610 human power is given to the on-delay timer 20, as shown in Fig. 4(a).
The output remains "0" and each timer is determined to be normal. Suppose that the time limit t3 of the on-delay timer 13 is t3''
If the value fluctuates, a signal with a time difference of [3' and 13'' is given to the on-delay timer 20, as shown in Figure 4(b), and if this value is greater than to, it is detected as a defective digital timer. are doing.

[Problems with the Background Art] The conventional device having the above configuration requires n additional on-delay timers with the same setting in order to check n digital timers, and has the disadvantage of requiring a large amount of circuitry. there were.

[Object of the Invention] The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a digital timer inspection circuit that can be inspected with a simple circuit.

[Summary of the invention] In the present invention, a signal simulation circuit is provided separately from the setting circuit, and at the same time as the inspection command is output, the output of the setting circuit is switched to the signal simulation circuit side that gives a predetermined signal, and the signal is output after a predetermined time. A digital timer is configured so as to derive , an inspection command is given to two or more of these digital timers at the same time, and furthermore, if the exclusive OR of each output of the digital timer is established for a certain period of time or more, it is determined that the digital timer is defective. It is determined that

[Embodiments of the Invention] Examples will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a digital timer according to the present invention. In FIG. 1, parts that are the same as those in FIG. 2 are given the same numerals and symbols, and their explanation will be omitted.

The timer start command is connected to the reset terminal of the counting circuit 2 via 0R47, and the inspection command is connected to the other input of 1.0R47. The setting circuit 3 is connected to the first input terminal of the comparator circuit 4 via AND61.62 and 0R45, 46, and the inspection command is connected via 140T8 to the other input of AND61.62. Signal simulation circuit 7
is connected to the remaining terminals of 0R45, 46 via AND63.64, and the inspection command is connected to the other input of AND63.64.

The features of this configuration include the provision of ^ND61, 62 that locks the output of the setting circuit 3 in response to an inspection command, the provision of a signal simulation circuit 7, and the provision of a signal simulation circuit 7 that locks the output of the signal simulation circuit 3 in response to an inspection command. Enter ^ND63.64. ,
The reason is that 0R45 and 0R46 are provided, and 0R47 is provided which sets the reset terminal of the counting circuit 2 to "1" according to the inspection command.

Next, the response of the circuit of FIG. 1 will be explained, but the explanation of the same parts as the circuit of FIG. 2 will be omitted.

First, in normal times, the inspection command is "0", so the output of NOT 8 is "1", and the output of the setting circuit 3 is input to the comparison circuit 4 via AND61, 62 and 0R45, 46. .

On the other hand, since the inspection command is rOJ, the output of the signal simulation circuit 7 does not hold AND63.64, and 0R45, 46
It is not input to the comparator circuit 4 via. In this case, the timer output is generated when the outputs of the setting circuit 3 and the counting circuit 2 match, as is clear from the explanation of FIG.

Next, when an inspection command is given, the output of N0T8 will be rOJ
Therefore, the output of AND61 is set to [01]. As a result, the output of the setting circuit 3 is no longer input to the comparison circuit 4 via the 0Rs 45 and 46.

On the other hand, since the inspection command is "1", the output of the signal simulation circuit 7 becomes the first input of the comparison circuit 4 via the ANRO 63, 64 and the OR 45, 46. Here, the timer output is obtained when the output of the J1 number circuit 2 and the output of the signal simulation circuit 7 match, and is "1" until the inspection command becomes "0".
Continue. Further, it goes without saying that the time from when the inspection command is given until the timer output is obtained is determined by the output of the signal simulation circuit 7, regardless of the setting value of the setting circuit 3.

FIG. 5 shows a check circuit for detecting the time error of the digital timer shown in FIG. 1, and FIG.
Indicates the

FIG. 5 shows a circuit for detecting time errors of three digital timers similarly to FIG.
Similarly, timer start command B is sent to on-delay timer 52,
Timer activation command C is connected to on-delay timer 53.

On-delay timer 51, 52, 53 is EXCLUSI
VE 0R34, and its output is connected to the on-delay timer 20.

The input of the on-delay timer 20 is the time difference of the on-delay timers 51, 52, and 53. However, when an inspection command is input to the on-delay timer, as is clear from the explanation of FIG. Since the time periods [1, t2, and t3 are switched to the time period [■] determined by the signal simulation circuit 7, the time difference of the on-delay timers 51, 52, and 53 is equal to the counting error Δt when the timers are activated.

Figure 6(a) is a time chart when the on-delay timers 51, 52, and 53 are normal, and the on-delay timer 2
0 can only be given an input of Δt, so its output is
0", each timer can be determined to be normal.

FIG. 6(b) shows a case where the time of the on-delay timer 53 is shortened to tT' due to a defect in the counting circuit, etc., and the on-delay timer 20 is given a signal of the time difference between tT and tT', and this value is If it is larger than to, it can be determined that the digital timer is defective.

The purpose of this proposal is that even if 0R47 is not provided in the digital timer shown in FIG. 1, and the timer start command is given by providing an OR for each of the timer start commands A, B, and C in FIG. Needless to say, they are not excluded from the list. Further, in this proposal, the inspection of three digital timers has been explained, but it goes without saying that inspection of two or more digital timers is possible.

Effects of the Invention 1 As is clear from the above description, according to the present invention, in a digital timer equipped with an oscillation circuit, a counting circuit, a setting circuit, and a comparison circuit, the output of the setting circuit is determined in advance by an inspection command. By switching to the signal simulating circuit that provides the signal and at the same time giving a timer start command to start the counting circuit, when an inspection command is issued, the timer outputs after a certain period of time determined by the value of the signal simulating circuit, regardless of the value of the setting circuit. You can get

In addition, by using two or more of the digital timers mentioned above, giving an inspection command at the same time, and determining that these digital timers are defective when the exclusive OR of the outputs of these timers is established for a certain period of time, inspection can be performed. There is no need to separately provide an on-delay timer for this purpose, and it becomes possible to detect defects in the digital timer with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a digital quadruple timer according to the present invention, FIG. 2 is a block diagram of a conventional digital timer, and FIG.
This figure is a block diagram of one embodiment of the inspection circuit of the digital timer shown in FIG. 1, and FIG. 6 is a time chart of the inspection circuit of FIG. 5. 1... Oscillation circuit 2... Counting circuit 3...
Setting circuit 4...Comparison circuit 5.8...NO
T 6, 61, 62, 63.64...
AND7...Signal simulation circuit 11.12, 13, 20, 21, 22, 23, 51, 5
2.53...On delay timer 31.32, 33.34 ・EXCLUSIVE 0R
41, 42, 43, 44, 45, 46, 47...OR
1QA Figure 4 (α) (b)

Claims (1)

[Claims] an oscillation circuit, a counting circuit that starts counting the output of the oscillation circuit in response to a timer start command, a setting circuit for setting the time limit of the timer, and an output when the output of this setting circuit and the output of the counting circuit match. In a digital timer equipped with a comparator circuit that generates a signal, the output of the settling circuit is switched to a signal simulating circuit that provides a predetermined signal based on an inspection command, and at the same time the counting circuit starts counting, and the value of the output of the signal simulating circuit is changed to the value of the output of the signal simulating circuit. The output of the comparator circuit is derived after a certain period of time according to the specified time, and an inspection command is simultaneously given to two or more of the plurality of digital timer outputs, so that the exclusive OR of the outputs from the digital timer is established for a certain period of time or more. A digital timer inspection circuit that determines that the digital timer is defective if the digital timer is defective.