JPS6124318A - Impedance converter - Google Patents

Abstract

PURPOSE:To obtain an impedance converter with very small distortion by connecting a depletion FET and an enhancement FET in series, giving an input signal in common and eliminating channel modulation of the enhancement FET. CONSTITUTION:N channel transistors (TR) Q1, Q2 and a constant current source 1 are connected in series between a power suply VDD and ground, gates of the TRs Q1, Q2 are connected in common and the substrate of the TRQ2 and the source are connected. An input signal VIN is fed in common to the gate electrode of the TRs Q1, Q2 and an output signal VOUT is extracted from the connecting point between the TRQ2 and the constant current source 1. The TRQ1 is the depletion FET and the TRQ2 is the enhancement FET.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an impedance converter with extremely low distortion, and a D-
It is used for impedance conversion of the output of an AC digital-to-analog converter.

[Technical background of the invention and its problems]

As a conventional impedance converter, there is a source follower as shown in FIG. Here, Q□ is MO8 type F
ET (field effect transistor), 1 is constant current source, vD
D is a power source. The transistor Q1 is an enhancement type FET, and since its source and substrate are commonly connected, the body effect (pack gate bias effect) can be ignored. However, due to channel modulation, the input voltage v
As 1N increases, the output voltage V. Relationship with U'
VfN-v+IT" increases. This causes distortion, so the one in Figure 6 is a high-precision D that requires low distortion.
- It could not be used for impedance conversion of the A converter.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and aims to provide an impedance converter with extremely low distortion.

[Summary of the invention]

The present invention makes it possible to configure an impedance converter with low distortion by connecting a depletion type f'ET and an enhancement type FET in series and using an input signal circuit for these in place of the transistor Q1 in FIG. This is what I did.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. The configuration of the present invention is, for example, as shown in FIG.
and constant current source 1 are connected in series, transistor Qt+Qs
The gate electrodes of the two transistors are connected in common, and the substrate and source end of the transistor Q2 are connected. Input signal v1N is commonly supplied to the gate electrodes of transistors Ql-Q2, and transistor Q
The configuration is such that the output signals ①o and JT are taken out from the connection point between z and the constant current source 1.

The above transistor Qt is a depression type F'ET,
) 5Nzostar Q2 is an enhancement type FFJT, and each gm (mutual conductance) is gml”rn2
Let the channel lengths of transistors Ql and Q2 be Ll + Lg + channel modulation coefficient 1, respectively.
z K 2 and the change in input voltage is ΔV1N
The change in I output voltage is 14f'voU1. Channel length L
1 + L 2 changes are respectively ΔL8. ΔL2.
The change in voltage Vl between transformer Ql and Q2 is Δ
V, then the following equation holds.2, ΔWork 0 is the change in the current Io passing through the transistors Q5 and Q2 (ΔWork◇=0
) ΔL, = −Kl@ΔvXN.

ΔL2=4(ΔV□−ΔVIN) Here, for example, K,=2=0.1 μm/v, I o
= 1 m A (Jm1=gm2=1m Q r L
If i ""L2 = 20/'m, ΔV - ΔV
=2.5X10, ΔV, , −・・−
・(2) IN 0LIT.

On the other hand, in the case of the conventional example shown in FIG. 6, ΔL=- is equal to fist ΔvXN. When using each of the above, ΔvIN - ΔvoUT = 5 0 - Δ"sN""' (4)
It is expected that the distortion will be about two orders of magnitude larger than in the case of the present invention using equation (2).

FIG. 2 shows another embodiment of the present invention, in which the conductivity type is changed from the N-channel configuration shown in FIG. 1 to the P-channel configuration. In the case of this configuration, the same thing can be said as in the case of FIG. 1, so the same reference numerals are used for corresponding parts, a dash is attached thereto, and the explanation is omitted.

FIG. 3 to FIG. 5 are circuit examples of the conventional constant current source 1. Figure 3 shows the transistor Q11゜Qtz + impedance Zll, Figure 4 shows the transistor Q21.
-Q241 impedance z21, FIG. 5 consists of transistor Q3l-Q341 impedance z3□. In FIGS. 4 and 5, transistor Q 21
r Q 221 impedance z211) Lansostar Q
ssrQzz* Impedance z31 is not for bias, transistor Qzs and Qz4 - transistor Q3
When a and Q34 are operated in the saturation region, the constant current properties in FIGS. 4 and 5 are much better than in FIG. 3.

〔Effect of the invention〕

As explained above, according to the present invention, an impedance converter with extremely low distortion can be provided.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing another embodiment of the invention, and Figs. 3 to 5 are circuit diagrams of constant current sources used in the circuit. , FIG. 6 is a circuit diagram showing a conventional impedance converter.
yQ'2...Enforcement type FET, 1
...constant current source, vDD...power supply. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 5 VDD VDD Figure 4 DD

Claims (2)

[Claims] (1) Between the first potential supply end and the second potential supply end,
A first depletion type FET, a second enhancement type FET, and a constant current source are connected in series, and the first
The gate electrodes of the FET and the second FET are commonly connected, an input signal is supplied to the common connection point of these gate electrodes, and an output signal is taken out from the connection point of the second FET and the constant current source. impedance converter. (2) The constant current source includes two FEs operating in the saturation region.
The impedance converter according to claim 1, characterized in that it consists of a series circuit of T.