JPS6124095A - Memory device for semiconductor - Google Patents

Abstract

PURPOSE:To absorb leak current flowing into a common data line by setting an MOSFET whose source is connected with the earthing point of a circuit, and whose gate and drain are connected to the common data line. CONSTITUTION:MOSFET Q15 absorbing leak current is provided between a common data line and an earth potential point. The gate and drain of MOSFET Q15 are connected to the common data line CD, the source is connected to the earth potential of circuit, and the conductance of MOSFET is designed to have a character of variable conductance complying with the potential of common data line CD. When the potential of common data line CD happens to become suddenly higher, the potential of common data line CD can be lowered at a comparative high speed by enlarging conductance, and or when the potential is comparatively low, the supplied current should be limited to comparatively smaller value. Therefore, when the common data line falls to a specified level, current thereof can be made smaller and low in consuming power.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technology effective for use in FAMO3 (floating gate, avalanche injector, and insulated gate electric field EFROM (electrically programmable read only memory) devices).

(Background Art) An EPROM device using a semiconductor element such as FAMO3 (Floating Avalanche Injection S7 MOS FET) as a memory element (memory cell) is known (e.g., Japanese Patent Laid-Open No. 152933/1983). reference).

E F R0 Mmm! For example, a sense amplifier circuit as shown in FIG. 1 is used. This sense amplifier circuit uses memory information appearing on the common data line CD by addressing the memory cells to be amplified by a common gate type M.
It is supplied to the source of the O3FET QI 4, and its drain output is transmitted to the differential sense amplifier SA.

In such a readout circuit, the following problems occur. In other words, when the chip is not selected, the above increase @
If the potential of the common data line rises abnormally due to leakage current flowing from MO5FETQ14 or the like, the common data line CD continues to maintain this high potential because there is no discharge path. In the data line selection operation of this memory array, the data line selection signal line and the common data line CD
Since the potential of the common data line CD is further increased due to capacitive coupling with the common data line CD, the reading speed of low-level storage information is extremely slowed down. In addition to deterioration of element characteristics, one of the causes of leakage current in the amplification MO3FET QI 4 is as follows. That is, in order to substantially reduce the parasitic capacitance in the common data line CD and increase its signal change speed, the number of MO3FET switches constituting the column selection circuit coupled to the common data line CD is reduced. . In this case, the signals of each divided common data line are commonly supplied to the input terminal of the sense amplifier circuit through the amplifying MO3FET as described above. When the memory array and the common data line are divided in this way, a read operation in the selected memory array causes the amplification MO3FET in the non-selected memory array to perform an undesired current supply operation.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that achieves stable and fast reading.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, by providing a MOSFET whose gate and drain are coupled to the common data line and whose source is connected to the ground point of the circuit, leakage current flowing into the common data line is absorbed.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of a memory array section when the present invention is applied to an EFROM device.

Each circuit element and circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using a known MO3 semiconductor integrated circuit manufacturing technique.

In the EFROM device of this embodiment, a complementary address signal formed through an address buffer receiving X, Y address signals (not shown) supplied from an external terminal (not shown) is supplied to an address decoder DCH. In the same figure,
An address buffer and an address decoder are shown as the same circuit blocks XADB-DCR and YADB-DCR, respectively. Although not particularly limited, the address buffers XADH and YADB are connected to the internal chip selection signal cl.
It is activated by 1, takes in an address signal from an external terminal, and forms a complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an address signal in opposite phase.

Address decoder DCR(X) forms a selection signal for word line W of memory array M-ARYO according to its complementary address signal.

Address decoder DCR(Y) forms a selection signal for the data line of memory array M-ARY according to its complementary address signal.

The above memory array M-ARYO is shown as a representative Jt
It is composed of a plurality of FAMO3l transistors (nonvolatile memory elements...MOSFETQI...-Q6), word lines Wl, W2, and data IJID1 to Dxs. In memory array M-ARYO, FAMOS transistor Q3 arranged in the same row;
The control gates of (Q4-Q6) are connected to the corresponding word line Wl (W2), respectively, and the F A M OS transistors Ql, Q4 to Q4 arranged in the same column
Q3. The drain of Q6 is connected to the corresponding data line D.
1 to Dn. The common source line C8 of the FAMOS transistors is, but is not particularly limited to, a debension type MO3FET QI that receives the write signal we.
It is grounded via O. The conductance of this MOSFET QIO is relatively blurred by the low level of the internal control signal ii during writing. As a result, the potential of the common source aC3 becomes MO3FETQIO
By making the conductance relatively small, it is brought to a relatively high potential. When the potential of this common source line C5 is made relatively high, the threshold voltage of the transistor FAMO3) is made relatively high. Therefore, by supplying a write high voltage to the data line and making the word line non-selected, the effective threshold voltage of the non-selected FAMOS transistor is increased, so that the leakage current flowing therein can be reduced. As a result, the write current supplied from the external terminal is efficiently selected in FAMO3).
Since it is supplied to the transistor, efficient write operations can be performed. Note that during the read operation, the high level of the control signal 71 makes the conductance of the MO3FET QIO relatively large. This results in
This increases the read speed.

Each of the data lines D1 to Dn is connected to the address decoder D.
Through column selection switches MO3FETQ7 to Q9 that receive the selection signal formed by CR(Y),
Connected to common lotus data 1llcD. common data line CD
is connected to the output terminal of a write data input buffer DIB that receives a write signal input from an external terminal I10.

Further, the common data llCD constitutes an input stage circuit of the sense amplifier SA, and is connected to the source side of an increase @MO3FETQ14 having a level limiter function, which will be described next.

The gate of the above enhancement @MO5FETQ14 is equipped with dibrera silane WMO5FETQI 1 and enhancement type M
A divided voltage of the power supply voltage Vcc formed according to its conductance ratio is supplied as a bias voltage.

An enhancement type MO8FETQ13 whose gate and drain are connected to the power supply voltage VCC is provided as a load on the drain side of the 11M03FETQ14. The drain output signal of the 1111 MO3FET Q14 is sensed by the differential mesense amplifier SA which sets the reference voltage Vref to a determination level.

When the stored information of the memory cell continues, a bias voltage is applied to the memory cell selected by the address decoders X-DCR and Y-DCR through the MO3FETQ14.6 The selected memory cell receives the write data. Accordingly, it has a high threshold voltage or a low threshold voltage with respect to the word line selection level.

If the selected memory cell is turned off regardless of the word line selection level, the common data line CD is
The current is supplied from MO5FETQI4 to a relatively high level. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data 1JllcD is set to a relatively low level. In this case, common data II CD (D Hirehe) Lt
is, the gate voltage of MO3FETQ14 is
TQI 1. According to the conductance ratio of Ql2, it is made relatively low and is brought to a relatively low level by "C".

The low level of the common data line CD is MO3FBTQI
4. A relatively high level can be achieved by appropriately setting the size ratio between Q13 and the MOSFET constituting the memory cell. By restricting the high level and low level of the common data mCD, it is possible to speed up reading even though there is a stray capacitance or the like that limits the signal change speed on the common data line CD. can. That is, when data is read out from a plurality of memory cells one after another, the time required for one level of the common data line CD to change to the other level can be shortened.

However, as described above, once the potential of the common data line CD is raised by the leakage current flowing from the amplifying MO3FETQ14 etc., the MO3FETQ14 is turned off. Therefore, the common data line CD continues to maintain the above-mentioned high potential.Therefore, in this embodiment, MO3FET QI 5 that absorbs the above-mentioned leakage current is installed between the common data line and the ground potential point of the circuit. provided.

The gate and drain of this MO3FET QI 5 are coupled to the common data line CD, and its source is coupled to the ground potential of the circuit. This MOSFET has its gate and train coupled to the common data line CD, so that its conductance has a variable conductance characteristic in accordance with the potential of the common data line CD. Therefore, when the potential of the common data line CD suddenly increases as described above, the conductance of the common data line CD increases and the common data line C
Lower the potential of D. Further, when the potential of the common data line CD is relatively low, its conductance is made relatively small, so that the current supplied from the MO3FETQ14 is limited to a relatively small current value, for example, about 2 pA.

Note that the MO3FET Q14 for amplification performs an amplification operation of the gate-grounded source input, and transmits its output signal to the sense amplifier SA. The output signal of the sense amplifier SA is sent from the external terminal I10 via the data output buffer DOB. Depending on the enable signal, program signal and write high voltage, the internal control signal ce
, we, etc., and a write high voltage Vpp/'read low voltage Vcc, etc., which are selectively supplied to the address decoder.

〔effect〕

(11) By providing a MOSFET whose gate and drain are coupled to the common data line to absorb leakage current, when the potential of the common data line becomes abnormally high, the current flowing therein is increased and the common data line CD is quickly connected. The level can be lowered to a desired level.This allows the logic “0” from the selected memory cell to be lowered to the desired level.
” (Low level) reading can be performed at high speed.

(2) Since a MOSFET whose gate and drain are connected to the common data line is used, an absorption current can be generated according to the potential of the common data line. Therefore, when the common data line drops to a certain level, the current can be reduced, resulting in an effect that power consumption can be reduced.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, an EPROM device that writes/reads multiple-bit signals in parallel can be configured by providing a plurality of memory arrays M-ARY, sense amplifiers SA, data output buffers, data input buffers, etc. shown in FIG. 2 above. It is possible. The specific circuit configuration of each circuit block constituting the above-mentioned EPROM device can be modified in various ways.

[Application field]

In the above explanation, the invention made by the inventor of the present application was mainly applied to an EPROM device, which is the technical field behind the invention, but it is not limited to this, and the invention is not limited to this. EEPROM, fixed ROM that can be electrically erased using a memory element such as oxide semiconductor
It can be widely used in semiconductor storage devices such as devices.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a read operation considered prior to the present invention, and FIG. 2 is a circuit diagram showing an embodiment of an EPROM device to which the present invention is applied. XADB-DCR, YADB-DCR...Address buffer/address decoder, M-ARYO.

Claims (1)

[Scope of Claims] 1. A memory element configured in a matrix arrangement, which has a threshold voltage higher or lower than a selected level of a word line coupled to a gate according to stored information. a common data line coupled to the data line of this memory array via a column selection circuit, its gate and drain coupled to this common data line, and its source connected to the ground potential point of the circuit. , a MOSFE that absorbs the leakage current flowing into the common data line.
1. A semiconductor memory device comprising: T. 2. The semiconductor memory device according to claim 1, wherein the memory element is a FAMOS transistor.