JPS60212898A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To set up the potential of respective common source lines to respective optimum values by dividing the common source lines in every plural memory arrays and connecting a variable impedance means between each common source line and an earth potential point of a circuit. CONSTITUTION:The common source lines CS1-8 are separately connected to the memory arrays M-ARY1-8. When a memory cell for writing exists out of respective memory arrays, the potential of respective common source lines are determined in accordance with writing current formed on the basis of a constant voltage formed by a writing circuit. Therefore, writing current for only one memory cell is always made to flow into the common source lines of the writing memory array and the potential of the common source lines can be set up to their optimum values only by the composite impedance of the MOSFETs Q10, Q11' and the writing current.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, which is composed of, for example, a MOSFET (insulated gate field effect transistor) and a semiconductor integrated circuit device such as a FAMO3 (floating avalanche injection MO3FET). The present invention relates to a technique effective for use in a semiconductor integrated circuit device incorporating an EPROM (Electrically Programmable Read Only Memory) in which an element is a storage element (memory cell).

[Background technology]

A semiconductor element such as FAMO3 (Floating Avalanche Injection MO3FET) is used as a memory element (
EP ROM devices with memory cells (memory cells) are known (
(Refer to Japanese Patent Application Laid-Open No. 152933/1983).

An EP in which a plurality of memory arrays each having the above-mentioned FAMOS transistors arranged in a matrix is provided to perform parallel writing/reading of information of multiple focus points.
The inventor's research has revealed that the following problems occur in ROM devices.

That is, a MOSFET as a variable impedance means is provided between the common source line of the FAMOS transistors constituting the memory array and the ground potential point of the circuit. The reason for this is that in the write operation, the data line to which the drain is connected is in the selected state, and the word line to which the gate is connected is in the unselected state.
-Prevents leakage current from flowing into the transistor. MOSFE as the above variable impedance means
By setting the impedance characteristic of T to a relatively large value and floating the potential of the common source line to about 0.5 V, the threshold voltage of the FAMO3) transistor is increased by utilizing the substrate effect in the transistor. This makes it possible to prevent or significantly reduce the leakage current flowing through the non-selected FAMO3) transistor.

Therefore, by preventing or reducing the leakage current,
As a result of being able to increase the current value of the write current supplied to the selected FAMO3) transistor, an efficient write operation can be realized. Further, in the read operation, the impedance characteristic of the MOSFET as the variable impedance means is made small to reduce the increase in the threshold voltage of the FAMO transistor 5) due to the substrate effect. This achieves high-speed reading.

As the variable impedance means described above, this MOS
Since the FET is commonly provided for a plurality of memory arrays, the following problem arises.

That is, among the plurality of memory arrays, the number of FAMOS transistors to which writing (herein referred to as charge injection into the floating gate) is performed differs depending on the writing data at that time. From this,
The current flowing between the common source line and the ground potential point of the circuit will be significantly different. This makes it impossible to perform stable write operations. This is because when performing the above writing to all FAMOS transistors, all write currents flow to the common source line, and if the potential of the common source line rises too much, the MO3I-transistor is As the threshold voltage becomes too large, leakage current no longer flows to the unselected FAMOS3) transistor, but on the other hand, the threshold voltage of the selected FAMOS transistor increases, its drain current decreases, and the floating gate This is because the amount of charge injected becomes smaller. On the other hand, 1
When performing the above-mentioned writing to the FAMO3) ransis table, only the source current flows to the common source line. As a result, the potential of the common source line is insufficiently raised, and a leakage current flows to the unselected FAMO3I-transistor, and the write current flowing to the selected FAMO3 transistor becomes smaller accordingly. Put it away.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device including an EFROM with improved write/read characteristics.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, variable impedance means each operating according to a write/M extraction control signal is provided between a common source line in a plurality of memory arrays and a ground potential point of the circuit.

〔Example〕

FIG. 1 shows 1 in the EPROM device according to the present invention.
A circuit diagram of one embodiment of the memory array M-ARYI is shown as a representative. By providing a plurality of such memory arrays, an EFROM device that writes/reads data consisting of a plurality of bits is configured. Each circuit element in the figure is formed on a semiconductor substrate such as, but not limited to, single-crystal silicon by a known MO3 semiconductor integrated circuit manufacturing technique.

In this embodiment of the EPROM device, complementary address signals processed and formed are input to address decoders X-DCR and Y-DCR through an address buffer that receives address signals supplied from external terminals (not shown).

Address decoder X-DCR forms a selection signal for word line W of memory array M-ARYI according to its complementary address signal.

Address decoder Y-DCR forms a selection signal for the data line of memory array M-ARYI according to its complementary address signal.

Is the memory array M-ARY l shown above as a representative? It is composed of lJ number of FAMOS transistors (nonvolatile memory elements... MO3FETQI to Q6), word lines Wl, W2, and data lines D1 to Dn. Although not particularly limited, gummy FAMOS transistors Qll and Q12 are provided on each word line Wl and W2 in order to form a read reference voltage Vrof.

In the memory array M-ARY, FAMOS transistors Ql-Q3 (Q4 to Q6) arranged in the same row
The control gates of the respective word lines W
FAMO connected to l (W2) and placed in the same column
3l--transistor Ql.

Q4-Q3. The drains of Q6 are connected to corresponding data lines D1 to Dn, respectively. Also, dummy FAM
O3l-transistor Q11. The drains of Q12 are commonly connected.

And the common source IJ of the above FAMO3 transistors
[C3 is a depletion type MO3FET QI O and an enhancement type MO3F, which are in parallel configuration, with the write signal i commonly supplied to the gate, although not particularly limited.
Grounded via ETQI Oo.

Each of the above-mentioned data Il[D1 to Dn is connected to the common data line CD via column selection switches MO3FETQ7 to Q9. In addition, the above dummy FAMO3)
The potential of the commonly connected drains of transistors Qll and Q12 is taken out via MOS F E 'FQ 13 equivalent to the column selection switch MO3FET. The gate of this MO3FET0.13 has a power supply voltage V
cc is supplied regularly. The common data line CD is connected on one side to the output terminal of the next write circuit,
On the other hand, it is connected to the input terminal of the sense amplifier SA.

Note that the reference voltage V rer formed by the dummy circuit is also input manually to the sense amplifier SA. This output signal is then sent out from the external terminal I10 via the data output sofa DOB.

Further, the write signal inputted from the external terminal I10 is inputted to the data input cover sofa DIB, and the write data signal dll is formed by this data input cover sofa DIB. This write data signal dil is supplied to the next write circuit. The drain of the depletion type MO3FET Q14 whose gate and source are commonly connected is connected to a high voltage for writing (VPI). Although not particularly limited,
Between the source side of this MO3FET Q14 and the ground point of the circuit, there are a depletion type MO3FET QI 5 whose gate and source are commonly connected in the same way as above, and an enhancement type MO3FET QI 7 whose gate is applied with the write data signal dil. installed in series. Furthermore, between the source of the depletion type MO3FET Q14 and the ground potential point of the circuit, a depletion type MO3FET Q16 and an enhancement type MO3FET Q1B in the same series configuration as described above are provided. In this way, in this embodiment, the above-mentioned series diversion type MOS FETs are used in correspondence with the number of plural memory arrays.
and an enhancement type MO3FET are provided, respectively. The connection point between the MO3FETs QI5 and Q17 is connected to the gate of an enhancement type MO3FETQ20 that supplies a write signal to the common data line CD. Between the drain of this MO3FET Q20 and the high voltage terminal V11+) is a dibrella silane type MO3FET QI 9 whose gate and source are commonly connected.
will be provided.

The connection point between the MO3FETs QI6 and Ql8 similar to the above is connected to the gate of an enhancement type MO3FET that supplies a write signal to a common data line similar to the above provided for other memory arrays (not shown).

Note that when reading information stored in a memory cell, a bias voltage is applied to the memory cell selected by the address decoders X-DCR and Y-DCR by a sense amplifier SA having a level limiter function, although this is not particularly limited. The selected memory cell has a threshold voltage higher or lower than the word line selection level according to the write data.

If the selected memory cell is turned off regardless of the word line selection level, the common data line CD is
It is set to a relatively high level by the sense amplifier SA.

On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is set to a relatively low level. Such a common data line CD
By limiting the high level and low level of this common data ij [CD, etc., there is a capacitance such as a stray capacitance that limits the speed of signal change, but the reading speed can be increased. That is, when data is read out from a plurality of memory cells one after another, the time required for one level of the common data line CD to change to the other level can be shortened.

The control circuit C0NT is a chip enable signal supplied to external terminals CE, OE, PCM and Vl)I).

Depending on the output enable signal, program signal, and high voltage for writing, internal control signals ce and we, which will be described later, are activated.
form etc.

Next, the operation of the write circuit will be explained. Although not particularly limited, in the write circuit, for example, among the plurality of write data signals dil to din, the write data signal din of the Nth memory array is set to a high level. By this, enhancement type MO3FETQ1
Since B is in the on state, the above depression type M
A divided voltage a is formed by O3FETQ14 and Ql6.

Therefore, for example, when the write data signal di1 is at low level, the enhancement type MO3FETQ17
is in the off state, the enhancement type MO3FE
The gate of TQ20 is a diversion type MO3FE.
Since the divided voltage Va is transmitted through TQI 5, the high level signal transmitted to the common data line CD is '
It becomes Ja-Vth.

As shown in the characteristic diagram of voltage VPp and current I in FIG.
5 (Ql 6) and the characteristic curve Q14 of MO3FET QI 4 on the voltage VpP side. In this case, the characteristic curve Q15 (
The drain current I of Ql6) exhibits constant current characteristics with respect to fluctuations in voltage VpI). On the other hand, the characteristic curve Q1
In the current I of No. 4, only the non-linear portion thereof changes with respect to the fluctuation of the voltage VPp, and the vicinity of the above-mentioned intersection point does not change. As a result, the divided voltage Va becomes a constant voltage.

As a result, in the write circuit of this embodiment, even if the voltage VPP drops, a constant write signal can be supplied to the drain of the transistor FAMO3.

FIG. 3 shows an E P ROM! according to the present invention. A memory array layout diagram of one embodiment of f is shown. In this embodiment, although not particularly limited, the X address decoder X-0C
As an example, a 2-mat memory array in which four memory arrays M-AI≧Y1 to rv1-A I-Y4 and memory arrays M-ARY5 to M-ARY8 are arranged on the left and right sides of "C" with R as the center is taken as an example. It is shown.

In this embodiment, each memory array M-ARYI to M-ARY4 and memory array M-
Even in ARY5 to M-ARY8, common source lines are separated like C3I to C38. Between each common source line C31 to C38 and the ground potential point of the circuit, a common source line C31 to C38 shown as a representative is connected.
81, a depletion type MO3FETQI whose gate is supplied with an internal write enable signal We
O and enhancement type MO3FET QI 1 are provided in parallel.

In this way, each memory array M-ARY 1 to M-AR
Among Y8, if there is a memory cell to which the above writing is performed, the constant voltage Va formed by the above writing circuit
The potentials of common source lines C3I to C38 are respectively determined according to write currents formed based on . Therefore, in the common source line C5 of the memory array M-ARY where writing is performed, only the write current for one memory cell can always flow, so the potential of the common source line C3 is The optimal value can be set only by the composite impedance characteristics and the write current.

〔effect〕

(1) By dividing the common source line for each of a plurality of memory arrays and providing variable impedance means between each common source line and the ground potential point of the circuit, the write data can be written independently of the write data. The effect is that the potential of each common source line can be set to an optimum value without being affected by the number of memory cells performing the process.

(2) According to the above (11), the potential of the common source line in the memory array can be set to l&common value during the write operation and during the read operation, so it is possible to improve the write characteristics and the read characteristics. In other words, since the write current can actually be set accurately in the memory cell, it is possible to realize high-speed and reliable write and high-speed read operations.

(3) Parallel depletion type MO3FE as variable impedance means to set the potential of the common source line
By using T and an enhancement type MO3FET, the impedance ratio during write operation and read operation can be increased to 10:1, so the potential change of the common source line during the above write operation and read operation can be optimized. This has the advantage of being configurable.

(4) A constant voltage can be formed by using a divided voltage formed by a depletion type MO3FET whose gate and source are shared. and,
By supplying this constant voltage to the FAMO3) transistor as a high level for writing, the high voltage for writing VP
It is possible to improve the write characteristics when P decreases. In other words, the high voltage Vpρ and the writing time are equal to
The effect is that ideal write characteristics that change linearly can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the variable impedance for setting the potential of the common source line can be modified in various ways, such as one constructed by combining fixed resistance means and the above-mentioned MOSFET.

Further, the specific circuit configuration of the write circuit may be of any kind, and similarly, the specific circuits of the peripheral circuits such as the read circuit can take various embodiments.

[Field of Application] The present invention can be applied to EP ROM devices that store information by selectively injecting charges into floating gates, as well as various semiconductor integrated circuit devices such as microcomputers that incorporate such EFROMs. It is something.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an EPROM device according to the present invention, FIG. 2 is a characteristic diagram for explaining the operation of the write circuit in the embodiment circuit of FIG. 1, and FIG. 1 is a layout diagram of a memory array showing an embodiment of an EPROM device according to the present invention. X-DCR, Y-DCR...address decoder, M-A
RY...Memory array, SA...Sense amplifier, DIB
・・Data output bath sofa, DOB・・Data output bath sofa Fig. 1 Fig. 2 Fig. 3

Claims (1)

[Claims] 1. A plurality of memory arrays in which non-volatile semiconductor memory elements having control gates and floating gates and storing information by taking charge into the floating gates are arranged in a matrix. and are respectively provided between the common source of the nonvolatile semiconductor storage element in each memory array and the ground potential point of the circuit, and the impedance characteristic during writing is larger than that during reading according to a predetermined control signal. 1. A semiconductor integrated circuit device comprising an EPROM including variable impedance means having a characteristic. 2. The variable impedance means is composed of a depletion type MO3FET and an enhancement type MOSFET arranged in parallel, and an internal write enable signal that is set to a low level during writing is commonly supplied to the p gate. A semiconductor integrated circuit device according to claim 1, characterized in that: