JPS61240646A - Semiconductor device - Google Patents

Abstract

PURPOSE:To effectively improve an alignment accuracy and the certainty and to further improve the through-put and the yield by providing a pattern region for the alignment on a region adjacent to a semiconductor through a straight line and increasing it. CONSTITUTION:A semiconductor device adjacent to a straight line is deformed to form an alignment region, thereby firstly increasing an alignment pattern. This is because the region for forming the alignment pattern deforms the straight line and the semiconductor device of the invention to sum the obtained regions to increase. In other words, the shape of the alignment pattern 1 is increased as compared with the conventional pattern by the alignment pattern reign 2 formed by deforming the semiconductor device of the invention to be readily align by a worker, thereby obtaining sufficient necessary size and largely improving the workability. As to an automatic alignment, a distance from a real element pattern which disables the automatic alignment is increased to reduce or eliminate a real defect.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the manufacture of semiconductor devices, and particularly to patterns for alignment of semiconductor devices.

[Conventional technology]

Conventionally, as shown in FIG. 4, an alignment pattern has been formed within a straight line.

In this case, no special measures or considerations were taken in forming a special alignment pattern.

[Problem that the invention seeks to solve]

When forming alignment patterns within straight lines using conventional techniques, the major problems are:
First, the size (especially width) of the alignment pattern is limited.

In order to ensure long-term reliability of the semiconductor device, the cross-sectional structure of the straight line must have a cross-sectional shape in which, for example, the field film, second field film, and final passivation film overlap from below. For this reason, the width of the straight line, which is approximately 100 μm in the initial stage of semiconductor device manufacturing, becomes smaller as the later process progresses to 60 to 70 μm corners in order to form the above-mentioned straight line cross-sectional structure. There is no choice but to include an alignment pattern and a pattern for identifying the alignment pattern within the straight line. For this reason, the size of the alignment pattern is extremely small, and when viewed through the alignment optical system of the aligner, the operator can visually recognize the amount of alignment deviation from the gap between the wafer pattern and the mask pattern. The shape of the alignment pattern is limited to a length of about 20 μm at its maximum length, and as the process progresses and the layers become heavier, it becomes very difficult to observe. This is a major cause of deterioration of alignment accuracy. Furthermore, since it is difficult to see, alignment becomes laborious and reduces throughput, and furthermore, the effect on the visual acuity of the operator is a concern.

Next, when an auto-alignment pattern is used as an alignment pattern, the actual element pattern of the semiconductor device, especially adjacent to the straight line, cannot maintain a sufficient distance from the auto-alignment pattern, preventing execution of auto-alignment. It will harm you. Not only does the actual device pattern come under the alignment optical system instead of the wafer pattern for auto-alignment due to poor pre-alignment accuracy, making auto-alignment impossible.
Depending on the aligner used, the actual element pattern may vary from 2 to 2.
As the size has become as small as 5 μm, there are cases where auto-alignment is performed incorrectly. For this reason, flf operators are forced to perform manual alignment support when auto-alignment is not possible, which increases man-hours, reduces throughput, and if the alignment pattern is incorrect, it may lead to alignment (nv) defects and a decrease in yield. This has become a major problem in semiconductor device manufacturing.

[Means for resolving the down payment]

The semiconductor device of the present invention is characterized in that it has an alignment pattern region in the semiconductor device (d) and the region that filtrates to the straight line.

[Effect]

First, by deforming the semiconductor device adjacent to the straight line to form an alignment region, it becomes possible to enlarge the alignment pattern. This is possible because the area in which the alignment pattern can be formed is larger than the sum of the straight line and the area secured by deforming the semiconductor device according to the present invention. For this reason,
This makes it easier for the operator to see the alignment pattern, making it easier to perform the alignment work itself. Also, even with auto-alignment, the distance from the actual element pattern that makes auto-alignment impossible has been expanded, and the number of defensive features has been reduced or eliminated.

[Practical Example 1] Fig. 1 shows an example of forming a pattern for manual alignment in Example 1. c2 is an alignment pattern area formed by modifying the semiconductor device of the present invention. This results in 1
The shape of the alignment pattern is larger than that of the conventional pattern shown in FIG. 4, which makes it easier for the operator to perform alignment, ensuring sufficient dimensions and greatly improving work efficiency.

[Example 2] FIG. 2 shows an example using an auto-alignment pattern. As a result, the auto-alignment pattern 11 has become larger and the auto-alignment possible area has become narrower, so manual alignment support work has been significantly reduced and throughput has improved.

[Example 5] Figure 5 shows an example of an auto-alignment turn (for this auto-alignment).
This is an alignment pattern for a stem kuichi with a mechanical IJK-8PACE. The distance from the actual element turn is more than twice that of the conventional method, and alignment accuracy and probability have been greatly improved.

[Effects of the present invention]

The effects of the present invention are to improve alignment accuracy and reliability by expanding the alignment pattern area,
Furthermore, it aims to improve throughput and yield.In addition, by making the alignment pattern easier to align, it is also possible to reduce the strain on the eyesight of the operator. The cross-sectional structure of the straight line can be formed into a structure that can ensure long-term reliability of the semiconductor device.

Further, the effect of the present invention is that if it is used as is in a conventional alignment pattern, it can be formed with a short straight line dimension due to a two-row arrangement, and will be particularly useful for semiconductor devices with small chip sizes.

[Brief explanation of drawings]

FIG. 1 Seven diagrams of the putter of Example 1. 1...Pattern for manual alignment 2...Pattern area for alignment 5...Straight line 4...Semiconductor device actual element pattern FIG. 2 Pattern diagram of actual flight example 2. 11...Auto alignment pattern 12...Alignment pattern area 16...Straight line 14...Semiconductor device actual element pattern FIG. 5 Pattern diagram of Example 5. 21...Auto alignment pattern 22...Alignment pattern area 25...Straight rhino 24...Semiconductor device actual element pattern 25...Semiconductor device 1 characteristic evaluation pattern 26...
Alignment accuracy measurement pattern Figure 4 How many layers of the conventional pattern. 51...Pattern for manual alignment 52...
・Straight try 1 55...Semiconductor device actual element slam'' 2

Claims (1)

[Claims] A semiconductor device characterized by having an alignment pattern region in a region adjacent to the semiconductor device and a straight line.