JPS61236214A - Frequency division circuit - Google Patents

Abstract

PURPOSE:To attain the frequency division of a clock in a fast operating speed of an integrated circuit comprising a single FF forming by connecting a multi-FF forming integrated circuit and the single FF forming integrated circuit so as to minimize the increase in number of components. CONSTITUTION:Outputs QB, QC, QD of a 4-bit binary counter integrated circuit 2 are counted up synchronously with a clock 1. When the level of the outputs QB, QC, QD are all at logical '1', the output of a four-NAND gate integrated circuit 3 goes to logical '0' because of all logical '1' to the inputs and the output Q of a D FF integrated circuit 4 goes to logical '0' at the next clock. When the output Q goes to '0', the input of an LD terminal goes to logical '1', the parallel input of the integrated circuit 2 is made effective by the leading of the clock 1 and frequency division information is set to the integrated circuit 2. Through the repetition of the operation above, a frequency-divided clock is outputted at an output Q' of the integrated circuit 4.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a logic circuit that divides a clock.
In particular, it relates to a frequency divider circuit with high operating speed.

BACKGROUND OF THE INVENTION Conventionally, this type of frequency division of a clock of two or more has been performed using a large number of integrated circuits having a clip-flop structure, such as a four-pit binary converter.

For example, using only the 4-bit binary counter 2 in FIG. 1 showing the embodiment of the present invention, the parallel input terminals IA, I
Input the frequency division information to B, IC, and ID, and output the logical product of the counter output QI Qct QD and the enable signal.The C output is used as the frequency division clock, and this inverted value is applied to the LD terminal. The most common method was to input the information into the data and repeat the counter operation. (For example, 8N74S163fi4 by f') h'
)nfi, TEXA8 lN8T-UMENTS,
THE BIPOLAR DIGITAL INT-E
GR,ATED CIRCUIT DATA BOUK
PA TI, 1980. P7-178-193) However, the operating speed of integrated circuits with multiple flip-flops is slower than that of single 7-lip-flops; company's 8N748163
For M4-bit binary counter, it is 25nsac,
The disadvantage was that fast frequency division could not be obtained.

In addition, in order to increase the operating speed, if the frequency divider circuit is constructed using only integrated circuits with a single 7 lip-flop configuration, the number of integrated circuits used will increase, that is, in the case of frequency division by 10, four integrated circuits will be required. , and the load increases. Also, a large amount of current is required, and the clock must be amplified, which is time-consuming.

Problems to be Solved by the Invention An object of the present invention is to provide a frequency divider circuit that solves the above-mentioned drawbacks, such as slow operation speed and an increase in the number of circuits.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a binary counter with parallel inputs, a gate circuit connected to the output terminals of the binary counter except for the lowest output terminal, and a gate circuit connected to the output terminals of the binary counter except for the lowest output terminal. 9, the above-described binary A configuration is adopted in which a clock is input to each clock input terminal of a counter and a D-type 7 flip-flop.

Operation Since the present invention is configured as described above, arbitrary frequency division information is set to the parallel input of the parallel input material pinari counter, and the output of the binary counter is counted up in synchronization with the clock, and the lowest output terminal All outputs of terminals except 1 are 1
Then, the gate circuit becomes O, and the output Q of the D type flip-flop to which this value is input is delayed by one clock and becomes 0.
! : By doing so, the frequency division information is reloaded by this output Q and the counter is operated, whereby an arbitrary frequency division output Q can be obtained.

Example Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, which shows a block circuit diagram of an embodiment of the present invention, the frequency dividing circuit of the present invention has a clock 1 to be frequency divided, and a 4-bit binary counter integrated circuit 2 which uses clock 1 as a clock input. , a four-gate integrated circuit 3 connected to the high-level outputs QB, QC, and QD except for nine of the four outputs of the integrated circuit 2, and a D-type flip-flop integrated with the output of the integrated circuit 3 as a delay input. The output Q of the integrated circuit 4 is input to the parallel input load terminal LD of the integrated circuit 2 and the input terminal of the integrated circuit 30, and the clock 1 is input to the clock input terminal CP of the integrated circuit 4. . Also, the parallel input terminal IAs of the integrated circuit 2
Frequency division information for clock frequency division is input to +IC+ID.

FIG. 2 is a time chart of this embodiment. The operation of this embodiment will be explained with reference to FIG.

The outputs QB, QC, and QD of the integrated circuit 2 count up in synchronization with the clock 1. When the outputs QB, QC, and QD are all "1", the inputs of the integrated circuit 3 are all "1".
Therefore, the output becomes ``0'', and the output Q of the integrated circuit 4 becomes ``O'' at the next clock. Output Q is #0'''
Then, the output of the integrated circuit 3 becomes "1", and the output Q becomes "1" at the next clock.

Also, when the output Q becomes "O"", the input of the LD terminal becomes 11
1, the parallel input of the integrated circuit 2 becomes valid at the rising edge of the clock 1, and frequency division information is set in the integrated circuit 2. In this embodiment, an example of frequency division by 10 is shown. By repeating this operation, the frequency-divided clock is output to the output Q of the integrated circuit 4. In the conventional frequency divider circuit, the 几・C output of the integrated circuit 2 was used as the frequency-divided output. The R-C output is a 748 series with a delay time of 25nsee, and a clock input of 40MH
Only zi can handle this. However, the output Q of the integrated circuit 4 in this embodiment is a 748 series with a delay time of 9 ns.
EC has the advantage of being able to support up to IIOMHz as a clock input.

In addition, in this example, to show the case of frequency division by 10, the frequency division information IA, In, Ic, In is (0110)=6
However, in general, if the frequency division number is m, then 16-m
IAw Ise Ic, ID
It is possible to divide the counter up to the maximum value of 16 by giving it in order from low to high. Furthermore, by using a gn-bit binary counter and an n-bit Nant gate, it is possible to divide any frequency higher than this. It becomes possible.

As explained above and beyond the effects of the invention, Kinoe F! According to AK, by combining an integrated circuit with a multiple 7 lip-flop configuration and an integrated circuit with a single 7 lip-flop configuration, the increase in the number of components can be minimized and the operating speed of the integrated circuit with a single 7 lip-flop configuration can be increased. This has the effect of being able to divide the clock frequency.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, and FIG. 2 is a time chart of FIG. 1. 1...Clock, 2...4-bit binary counter integrated circuit, 3...4 Nant gate, 4...D type flip 70 tube, CP...
...Clock input. D...Delay input, LD...Load, I
Mul'BS lCfID-... Frequency division information, Q...
...Output, Q...Divide output, Qmut QB
, Qct QD...Counter output, R-C・
...Conventional frequency division output (ripple carry output), M
R...Reset, MS...Set.萬ττ glance-pe

Claims (1)

[Claims] A binary counter with parallel input, a gate circuit whose input is the output from the output terminals excluding the lowest output terminal of this binary counter, the output of this gate circuit which is input to the delay input terminal, and a complementary value output terminal. The output of the binary counter is a frequency-divided output, and the output from the positive value output terminal is input to the parallel input load terminal of the binary counter and the input terminal of the gate circuit. A frequency divider circuit configured to input a clock to each clock input terminal of a frequency divider circuit.