JPS61236191A - Substrated carrying integrated circuit - Google Patents
Substrated carrying integrated circuitInfo
- Publication number
- JPS61236191A JPS61236191A JP7780885A JP7780885A JPS61236191A JP S61236191 A JPS61236191 A JP S61236191A JP 7780885 A JP7780885 A JP 7780885A JP 7780885 A JP7780885 A JP 7780885A JP S61236191 A JPS61236191 A JP S61236191A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit chip
- board
- substrated
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路搭載基板に関し、とくに、集積回路チ
ップを回路基板に７エイスダウンポンデイングした集積
回路搭載基板の構造に関するものでろる〇
〔従来の技術〕
従来、集積回路チップ１の表面電極紫回路基叛４の配線
パターン３に直接接続して搭載した集積回路搭載基板で
は、第２図のように、集積回路チップｌと回路基板４と
の間にスキ間８ができる。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an integrated circuit mounting board, and particularly relates to the structure of an integrated circuit mounting board in which an integrated circuit chip is 7-eighth downponded onto a circuit board. Conventional technology] Conventionally, in an integrated circuit mounting board mounted directly connected to the wiring pattern 3 of the surface electrode purple circuit board 4 of the integrated circuit chip 1, as shown in FIG. There will be a gap of 8 between.
この状態で樹脂５ｔ−ポツティングして集積回路チップ
１を被覆し、この後果梗回路搭載基板に他の回路素子全
半田リフロー等により半田付けするのでおるが、この半
田付時の熱にエフスキ間８の空気が膨張して樹脂５や集
積回路チップ１にクラックを生じる。このクラック會防
ぐため集積回路チップ１の下に穴６ｔ−設は回路基板４
の裏面にしゃ元板７會設けた１１！造になっていた。尚
、本従来例では配線パターン３上にはソルダーレジス）
２Ｑ有している。In this state, the integrated circuit chip 1 is covered by resin 5t potting, and then all other circuit elements are soldered to the circuit board using reflow soldering. The air expands and causes cracks in the resin 5 and the integrated circuit chip 1. To prevent this cracking, a hole 6t is provided under the integrated circuit chip 1 on the circuit board 4.
11 with 7 original boards on the back! It was built. In addition, in this conventional example, there is no solder resist on the wiring pattern 3)
Has 2Q.
かかる従来の構造では、集積回路チップ１下の穴６なら
びにしゃ元板７が必要となり、製造が複雑で困難でめり
、し中元板７の材質ならびに貼ｐ付けの構造上、信頼度
的にも問題がめり友。Such a conventional structure requires a hole 6 under the integrated circuit chip 1 and a barrier plate 7, which is complicated and difficult to manufacture, and is difficult to manufacture due to the material of the intermediate plate 7 and the bonding structure. My friend also has problems.
本発明の集積回路搭載基板は、回路基板の配線に集積回
路チップ表面の電極が直接取り付けられており、この集
積回路チップ表面と回路基板との間にスキ間を生じない
ように耐熱性の樹脂を有している。In the integrated circuit mounting board of the present invention, the electrodes on the surface of the integrated circuit chip are directly attached to the wiring of the circuit board, and heat-resistant resin is used to prevent gaps from forming between the surface of the integrated circuit chip and the circuit board. have.
次に、本発明について図面全参照して説明する。 Next, the present invention will be explained with reference to all the drawings.
第１図は、本発明の一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of the present invention.
基板４上の配線パターン３の所定部にはソルダーレジス
ト２を有している。配線パターン３の集積回路チップ１
の電極を接続する部分にはソルダーレジスト２は有して
いない。この繕出部に集積回路チップ１の電極が７エー
スダウンで接続されている。集積回路チップ１下の基板
４上にも配線パターン３′を有しており、この配線パタ
ーン３′と集積回路チップ１との間はソルダーレジスト
２でスキ間がないように埋められている。配線パターン
３′は基板４と集積回路チップ１との間隔ｔせまくする
外に基板４全通して侵入する水分の遮弊の作用もしてい
る。集積回路チップｌｔ−取り付は友後に、樹脂５ｔボ
ツテイングして集積回路チップ１の保護がなされる。A solder resist 2 is provided at a predetermined portion of the wiring pattern 3 on the substrate 4. Integrated circuit chip 1 with wiring pattern 3
There is no solder resist 2 in the portion where the electrodes are connected. The electrodes of the integrated circuit chip 1 are connected to this patch with 7 aces down. A wiring pattern 3' is also provided on the substrate 4 below the integrated circuit chip 1, and the space between this wiring pattern 3' and the integrated circuit chip 1 is filled with solder resist 2 so that there is no gap. The wiring pattern 3' not only narrows the distance t between the substrate 4 and the integrated circuit chip 1, but also functions to prevent moisture from penetrating through the entire substrate 4. After the integrated circuit chip lt is attached, the integrated circuit chip 1 is protected by bottling 5 tons of resin.
かかる集積回路搭載基板によれば、その後半田リフロー
等により他の回路素子上堰り付けても。According to such an integrated circuit mounting board, even if it is mounted on other circuit elements by subsequent solder reflow or the like.
集積回路チップ１下にすき間がないので樹脂５や集積回
路チップ１のクラックという問題点が解消される。この
念め集積回路チップ１下のソルダーレジスト２は他の耐
熱性を有する絶縁性の樹脂にすることもできる。ま几、
集積回路チップ１下の配線パターン２になくても良い。Since there is no gap under the integrated circuit chip 1, the problem of cracks in the resin 5 and the integrated circuit chip 1 is solved. The solder resist 2 under the integrated circuit chip 1 may be made of other heat-resistant insulating resin. Well done,
It does not have to be in the wiring pattern 2 under the integrated circuit chip 1.
以上説明したように本発明は、特に基板に集積回路チッ
プ全７エイスダウンポンテイングする際、この集積回路
チップ下にスキ間會埋める樹脂ｋＶすることにより、そ
の後の半田付は時に集積回路チップやこの集積回路チッ
プｔおお９樹脂被覆が破壊されることがなくなり、また
従来の如く集積回路チップ下の穴やし中元板も不要とな
るので製造も簡単で、信頼度的にも優れたものとなる。As explained above, the present invention is particularly advantageous in that when all seven integrated circuit chips are down-ponted on a board, by applying resin kV to fill the gaps under the integrated circuit chips, subsequent soldering is sometimes carried out on the integrated circuit chips. This integrated circuit chip's resin coating will not be destroyed, and the hole base plate under the integrated circuit chip, which was required in the past, is no longer required, making it easy to manufacture and superior in reliability. becomes.
。.
第１図は本発明の集積回路搭載基板の一実施例の断面図
、第２図は従来構造の集積回路搭載基板の一実施例の断
面図である。
１・・・集積回路チップ、２・・・ソルダーレジスト、
３．３′・・・配線パターン、４・・・基板、５・・・
樹脂、６・・・穴、７・・・し中元板、８・・・スキ間
０“６”′”′” １・；１．、、ｌｔｌヤ＼〜ノ
第１図
第２図FIG. 1 is a sectional view of an embodiment of an integrated circuit mounting board according to the present invention, and FIG. 2 is a sectional view of an embodiment of an integrated circuit mounting board of a conventional structure. 1... Integrated circuit chip, 2... Solder resist,
3.3'... Wiring pattern, 4... Board, 5...
Resin, 6... Hole, 7... Center plate, 8... Gap 0"6"'"'"1.;1. ,,ltlya＼〜ノFig. 1Fig. 2
Claims (1)
続した集積回路搭載基板において、前記集積回路チップ
と前記回路基板との間にスキ間がないように、耐熱性を
有する樹脂を有することを特徴とする集積回路搭載基板
。An integrated circuit mounting board in which an integrated circuit chip is directly connected to a circuit board with electrodes on its surface, characterized by having a heat-resistant resin so that there is no gap between the integrated circuit chip and the circuit board. A board mounted with an integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7780885A JPS61236191A (en) | 1985-04-12 | 1985-04-12 | Substrated carrying integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7780885A JPS61236191A (en) | 1985-04-12 | 1985-04-12 | Substrated carrying integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61236191A true JPS61236191A (en) | 1986-10-21 |
Family
ID=13644316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7780885A Pending JPS61236191A (en) | 1985-04-12 | 1985-04-12 | Substrated carrying integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61236191A (en) |
-
1985
- 1985-04-12 JP JP7780885A patent/JPS61236191A/en active Pending
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