JPS61236170A - Constant-voltage diode - Google Patents
Constant-voltage diodeInfo
- Publication number
- JPS61236170A JPS61236170A JP7780985A JP7780985A JPS61236170A JP S61236170 A JPS61236170 A JP S61236170A JP 7780985 A JP7780985 A JP 7780985A JP 7780985 A JP7780985 A JP 7780985A JP S61236170 A JPS61236170 A JP S61236170A
- Authority
- JP
- Japan
- Prior art keywords
- type
- impurity region
- concentration impurity
- diffused
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 244000292604 Salvia columbariae Species 0.000 description 1
- 235000012377 Salvia columbariae var. columbariae Nutrition 0.000 description 1
- 235000001498 Salvia hispanica Nutrition 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 235000014167 chia Nutrition 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は定電圧ダイオード罠関し、特にＰＮ接合の降伏
部分が半導体層内に位置する様にした定電圧ダイオード
（以下サブサーフェスツェナーダイオードと称する）Ｋ
関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a constant voltage diode trap, and particularly to a constant voltage diode (hereinafter referred to as a subsurface Zener diode) in which the breakdown portion of the PN junction is located within a semiconductor layer. )K
related.
従来、この種のサブサーフェスツェナーダイオードはＰ
Ｎ接合の降伏部分が半導体層内に位置するため、ツェナ
ーダイオードの一刀の極は半導体層内にあり、降伏部分
から半導体層表面の電極までの経路が低インピーダンス
になる様第３ 図（ａ）。Traditionally, this type of subsurface Zener diode is P
Since the breakdown portion of the N junction is located within the semiconductor layer, the pole of the Zener diode is located within the semiconductor layer, and the path from the breakdown portion to the electrode on the surface of the semiconductor layer has a low impedance as shown in Figure 3 (a). .
（ｂ）の様な構造を有するサブサーフェスツェナーダイ
オードが使われている（例えば特開昭５５−１３４９８
３ ）ｎ すなわち、第３図（ａ）、（ｂ）は陽極側
に低インピーダンス路が形成されているサブサーフェス
ツェナーダイオードの平面図および断面図で、Ｐ型不純
物領域２が埋込まれたＰ型基板１にＮ厘エピタキシャル
層３を形成し、Ｐ型筒濃度不純物領域４および４１を形
成（通常絶縁拡散と同時に形成）シ、次いでＮ型高濃度
不純物領域５を形成（通常トランジスタのエミ、り拡散
と同時に形成〕しツェナーダイオードを構成したもので
ある。第３図（ｂ）ではＮ型エピタキシャル層３上に形
成されるシリコン酸化膜は省略されている。又、陽極お
よび陰極６．７はそれぞれＰ型筒濃度不純物領域４１お
よびＮ型高濃度不純物領域５上に設けられている。この
構造のサブサーフェスツェナーダイオードではＰ型不純
物領域２により陽極領域に低インピーダンス路を確保し
ている。A subsurface Zener diode having a structure as shown in (b) is used (for example, Japanese Patent Application Laid-Open No. 55-13498
3)n That is, FIGS. 3(a) and 3(b) are a plan view and a cross-sectional view of a subsurface Zener diode in which a low impedance path is formed on the anode side, and a P-type impurity region 2 is embedded. An N-type epitaxial layer 3 is formed on a type substrate 1, P-type tube-concentrated impurity regions 4 and 41 are formed (usually formed at the same time as insulation diffusion), and then an N-type high-concentration impurity region 5 is formed (usually a transistor emitter, The silicon oxide film formed on the N-type epitaxial layer 3 is omitted in FIG. 3(b). Also, the anode and cathode 6.7 are provided on the P-type cylindrical impurity region 41 and the N-type high concentration impurity region 5, respectively.In the subsurface Zener diode having this structure, the P-type impurity region 2 ensures a low impedance path to the anode region.
上述した従来のサブサーフェスツェナーダイオードは陽
極を埋込層２よりチア１表面に導くためＮ型高濃度不純
物領域５０回りＫＰ型嵩高濃度不純物領域４１設けてい
る。この構造では高＃に度不純物領域５および４１によ
る降伏電圧がサブサーフェスツェナーダイオードの降伏
電圧よりも低くならない様、領域５と４１の間は十分な
間隔をとる必要があり、降伏が不純物領域の表面でおこ
るツェナーダイオードと比較し電気的特性が優れている
反面素子面積が数倍になる欠点がある。。In the conventional subsurface Zener diode described above, a KP type bulky impurity region 41 is provided around an N type high concentration impurity region 50 in order to guide the anode from the buried layer 2 to the surface of the chia 1 . In this structure, it is necessary to provide a sufficient distance between regions 5 and 41 so that the breakdown voltage due to the high impurity regions 5 and 41 does not become lower than the breakdown voltage of the subsurface Zener diode. Although it has superior electrical characteristics compared to a Zener diode that occurs on the surface, it has the disadvantage that the device area is several times larger. .
〔問題点を解決するための手段〕
本発明のサブサーフェスツェナーダイオードはＰ型基板
に埋込まれたＰ型不純物領域によりＰウェルを形成し、
Ｐウェル内に［６度のＮ型およびＰｆｉ不純物領域を形
成している。ＰウェルはＰ型基板に埋込まれた不純物に
より形成するため、不゛純物磯度はＰウェル内部が高く
テア１表面が最も低い。このためＰウェルとＮ型高＠匿
不純物領域の接合部分では降伏をおこすことなく陽極の
低インピーダンス路を確保でき、降伏が不純物領域の表
面でおこるツェナーダイオードとほぼ同等の素子面積で
ダイナミックインピーダンスの低いサブサー７エスツェ
ナーを実現できる。[Means for solving the problem] The subsurface Zener diode of the present invention forms a P-well by a P-type impurity region embedded in a P-type substrate,
[6 degree N type and Pfi impurity regions are formed in the P well. Since the P-well is formed by impurities embedded in the P-type substrate, the impurity degree is high inside the P-well and lowest at the tear 1 surface. Therefore, a low impedance path for the anode can be secured without breakdown at the junction between the P-well and the N-type high @concentration impurity region, and the dynamic impedance can be maintained with a device area approximately the same as that of a Zener diode, in which breakdown occurs at the surface of the impurity region. It is possible to achieve a low sub-ser 7 Eszener.
次に１本発明について図面を参照して説明する。 Next, one embodiment of the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の一実施例の平面図、纂１図（ｂ
）は縦断面図である。図において、１〜５０Ω−６−の
Ｐ型基板１に表面酸度ｔｏ１７〜１０１９α−３のＰ型
不純物（例えばホク某）を拡散した後（最終工程で第１
図（ｂ）の領域８に相当する部分を形成した後）、１〜
１０Ω−αのＮ型エピタキシャル層３を形成する。次に
、表面鎖車ｌＯ〜１０２０ｒ、ｘ−３のＰ型不純物（例
えばホワ素）を拡散し、ＰＪ高濃度不純物領域４を形成
する。Ｐ型高濃度不純物領域４は集積回路装置の絶縁領
域と同時に形成する。さらに、Ｐ型高濃度不純物領域４
の形成と同時にＰ型基板ｌに埋込まれたＰ型不純物領域
をテ、グ表面まで拡散させ、ＰウェルであるＰ型低濃度
不純物領域８を形成する。次に表面濃度１０１９〜１０
２１湿−３のＮ型不純物（例えばリン、ヒ素）を拡散し
、Ｎ型高濃度不純物領域５を形成する。FIG. 1(a) is a plan view of an embodiment of the present invention, and FIG. 1(b) is a plan view of an embodiment of the present invention.
) is a longitudinal sectional view. In the figure, after diffusing a P-type impurity (for example, Hoku) with a surface acidity of to17 to 1019α-3 to a P-type substrate 1 of 1 to 50 Ω-6 (in the final step, the first
After forming a portion corresponding to region 8 in Figure (b)), 1 to
An N-type epitaxial layer 3 of 10Ω-α is formed. Next, a P-type impurity (for example, boron) of the surface chain wheels lO to 1020r and x-3 is diffused to form the PJ high concentration impurity region 4. The P-type high concentration impurity region 4 is formed at the same time as the insulating region of the integrated circuit device. Furthermore, P-type high concentration impurity region 4
At the same time as forming the P-type impurity region buried in the P-type substrate 1, the P-type impurity region 8 is diffused to the surface of the P-type substrate 1 to form a P-type low concentration impurity region 8 which is a P-well. Next, the surface concentration 1019-10
21 - 3 N-type impurities (for example, phosphorus, arsenic) are diffused to form N-type high concentration impurity regions 5.
Ｎ型高濃度不純物領域５はトランジスタのエミッタと同
時に形成する。陽極および陰極の電極６゜７はそれぞれ
第１図ｔｂ）のＰ型低級度不純物領域８およびＮ型高濃
度不純物領域５より取シ出す。The N-type high concentration impurity region 5 is formed at the same time as the emitter of the transistor. The anode and cathode electrodes 6.degree. 7 are taken out from the P-type low grade impurity region 8 and the N-type high concentration impurity region 5 of FIG. 1tb), respectively.
この構造のサブサーフェスツェナーダイオードでは、降
伏は半導体層内部でおこり、Ｐ嵩低装置不純物領域８と
Ｎ型高磯度不純物領域５の接合部分では降伏はおこらな
い。In the subsurface Zener diode having this structure, breakdown occurs inside the semiconductor layer, and breakdown does not occur at the junction between the P low-bulk device impurity region 8 and the N-type high-strength impurity region 5.
第２図は第１図に示したサブサーフェスツェナーダイオ
ードにおける表面からの深さに対する不純物濃度の特性
を示す図である。第２図において４０．５０．８０で示
した不純物分布は、それぞれ第１図の不純物領域４．５
．８の不純物衾匿を示す。ツェナーダイオードの降伏は
第２図Ａの部分でおき、不純物領域５と８の接合部分Ｂ
では降伏はおきないことは明らかである。FIG. 2 is a diagram showing the impurity concentration characteristics with respect to the depth from the surface in the subsurface Zener diode shown in FIG. 1. The impurity distributions shown at 40, 50, and 80 in FIG.
．． 8 shows impurity concealment. The breakdown of the Zener diode occurs at the portion A in FIG. 2, and at the junction B between the impurity regions 5 and 8.
It is clear that there will be no surrender.
以上説明したように本発明は高纜度のＮ型およびＰ型不
純物領域を基板に埋込まれたＰ型不純物により形成され
たＰウェル内に形成することにより、素子面積を表面降
伏ツェナーダイオードとほぼ同等の素子面積にできかつ
ダイナミックインピーダンスを低くできる効果がある。As explained above, the present invention forms high-strength N-type and P-type impurity regions in the P-well formed by P-type impurities embedded in the substrate, thereby reducing the device area to that of a surface breakdown Zener diode. This has the effect of making the device area approximately the same and lowering the dynamic impedance.
なお説明は陽極を接地して使用するサブサーフェスツェ
ナーダイオードについて行ったが、第１図（ｂ）の領域
８と基板ｌとの間にもう一層Ｎ型の不純物領域を埋込み
、陽極を７０−ティングにしてもよい。Although the explanation has been given regarding the subsurface Zener diode used with the anode grounded, another N-type impurity region is buried between the region 8 and the substrate l in FIG. 1(b), and the anode is You can also do this.
第１図（ａ）および（ｂ）は本発明の一実施例の平面図
および縦断面図、第２図はＭ１図に示すサブサーフェス
ンエナーダイオードの不純物細度の分布を示す図、第３
図（ａ）および（ｂ）は従来の改良されたサブサーフェ
スツェナーダイ万一ドの平面図および縦断面図であるＯ
１・・・・・・Ｐ型基板、２・・・・・Ｐ型埋込み層、
３・・・・・・Ｎ型エヒタキシャル層、４．４１・・・
・Ｐ型高濃度不純物領域、５・・・・・・Ｎ型高１＃度
不純物領域、６゜７・・・・・・陽極および陰極の電極
、８・・・・・Ｐ型低濃度不純物領域
第 ｆ 図
８Ｚ凶
３７さしＪ
箭３ 図
Ｚとり多ひ肴FIGS. 1(a) and (b) are a plan view and a vertical cross-sectional view of an embodiment of the present invention, FIG.
Figures (a) and (b) are a plan view and a vertical cross-sectional view of a conventional improved subsurface Zener die. embedded layer,
3...N-type epitaxial layer, 4.41...
・P-type high concentration impurity region, 5...N-type high 1# impurity region, 6゜7...Anode and cathode electrodes, 8...P-type low concentration impurity Area No. f Figure 8
Claims (1)
た他の導電型の半導体層と、該半導体層内に形成された
前記一導電型の高濃度不純物領域と、該一導電型の高濃
度不純物領域の表面を覆う様に形成された前記他の導電
型の高濃度不純物領域とを有し、前記他の導電型の高濃
度不純物領域および前記一導電型の高濃度不純物領域を
前記半導体基板に埋込んだ前記一導電型の埋込み領域よ
り前記半導体層内に形成されたＰウェル領域の中に形成
したことを特徴とする定電圧ダイオード。A semiconductor substrate of one conductivity type, a semiconductor layer of another conductivity type formed on the semiconductor substrate, a high concentration impurity region of the one conductivity type formed in the semiconductor layer, and a high concentration impurity region of the one conductivity type formed in the semiconductor layer. a high concentration impurity region of the other conductivity type formed to cover the surface of the concentration impurity region, and the high concentration impurity region of the other conductivity type and the high concentration impurity region of the one conductivity type are connected to the semiconductor. A constant voltage diode, characterized in that the constant voltage diode is formed in a P-well region formed in the semiconductor layer from the buried region of one conductivity type buried in the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7780985A JPS61236170A (en) | 1985-04-12 | 1985-04-12 | Constant-voltage diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7780985A JPS61236170A (en) | 1985-04-12 | 1985-04-12 | Constant-voltage diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61236170A true JPS61236170A (en) | 1986-10-21 |
Family
ID=13644343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7780985A Pending JPS61236170A (en) | 1985-04-12 | 1985-04-12 | Constant-voltage diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61236170A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016035950A (en) * | 2014-08-01 | 2016-03-17 | 新電元工業株式会社 | Semiconductor device |
-
1985
- 1985-04-12 JP JP7780985A patent/JPS61236170A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016035950A (en) * | 2014-08-01 | 2016-03-17 | 新電元工業株式会社 | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950006479B1 (en) | Laieral transistor | |
| US6570229B1 (en) | Semiconductor device | |
| JPH0336311B2 (en) | ||
| US4652895A (en) | Zener structures with connections to buried layer | |
| JP2000077663A (en) | Field-effect semiconductor device | |
| EP0082331B1 (en) | Subsurface avalanche breakdown zener diode | |
| US20040164376A1 (en) | Semiconductor device and method for manufacturing the same | |
| US6563169B1 (en) | Semiconductor device with high withstand voltage and a drain layer having a highly conductive region connectable to a diffused source layer by an inverted layer | |
| CN100502035C (en) | Semiconductor device and method for producing it | |
| JPS61236170A (en) | Constant-voltage diode | |
| KR900000826B1 (en) | Semiconductor ic manufacturing method | |
| JP2817247B2 (en) | Semiconductor device | |
| JPH0371673A (en) | Vertical mosfet | |
| US11444074B2 (en) | Semiconductor device and method for manufacturing same | |
| KR100216733B1 (en) | Integrated injection logic bipolar transistors | |
| KR900000818B1 (en) | Complemental transistor manufacturing method | |
| KR20050000001A (en) | Semiconductor device and manufacturing method thereof | |
| JP2655403B2 (en) | Power MOS field effect transistor | |
| JPH079385Y2 (en) | Semiconductor integrated circuit device | |
| JPH01194364A (en) | Longitudinal type high dielectric strength semiconductor device | |
| KR100275755B1 (en) | High power bipolar transistor and method for fabricating thereof | |
| JP2604793B2 (en) | Semiconductor device | |
| JP2650405B2 (en) | Bipolar transistor | |
| JPH0474478A (en) | Diode | |
| JPH0713969B2 (en) | Vertical PNP transistor |