JPS61234551A - Resin sealed type semiconductor device - Google Patents

Resin sealed type semiconductor device

Info

Publication number
JPS61234551A
JPS61234551A JP60077088A JP7708885A JPS61234551A JP S61234551 A JPS61234551 A JP S61234551A JP 60077088 A JP60077088 A JP 60077088A JP 7708885 A JP7708885 A JP 7708885A JP S61234551 A JPS61234551 A JP S61234551A
Authority
JP
Japan
Prior art keywords
marking
substrate
semiconductor device
resin
mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60077088A
Other languages
Japanese (ja)
Inventor
Tomio Matsui
松井　富雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60077088A priority Critical patent/JPS61234551A/en
Publication of JPS61234551A publication Critical patent/JPS61234551A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Abstract

PURPOSE:To satisfy both laser marking property and adhesion to a substrate simultaneously in a flat-mounting-type resin-sealed semiconductor device, by forming a mirror surface as a marking surface and forming a satin finished surface as a surface, which is in contact with the substrate, for the surface finishing state of a resin molded layer. CONSTITUTION:Of four kinds of planes of a resin molded layer, a marking surface f1 is made to be a mirror surface, and a contact surface f2 to a substrate is made to be a satin finished surface. In order to facilitate the manufacture of a metal mold, an upper side surface f3 is made to be a mirror surface, which is the same as the marking surface f1. A lower side surface f4 is made to be a satin finished surface, which is the same as the contact surface f2. Since the marking surface f1 is the mirror surface, excellent contrast of a laser mark is obtained. Since the contact surface f3 to the substrate is the satin finished surface, excellent adhesion is obtained in mounting the layer on a printed wiring board 3 through a bonding agent layer 4.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は樹脂封止型半導体装置に関し、特に平面実装タ
イプになる樹脂封止型半導体装置外囲器の改良に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device, and more particularly to an improvement in a resin-sealed semiconductor device envelope of a flat-mount type.

〔発明の技術的背景〕[Technical background of the invention]

平面実装タイプの樹脂封止型半導体装置は第１図（Ａ）
（Ｂ）に示す外観形状を有している。同図（Ａ＞は正面
図、同図（Ｂ）は側面図である。Figure 1 (A) shows a flat-mount type resin-sealed semiconductor device.
It has the external shape shown in (B). The same figure (A> is a front view, and the same figure (B) is a side view.

これらの図において、１は樹脂モールド層である。In these figures, 1 is a resin mold layer.

該樹脂モールド層１の内部には、図示しない半導体チッ
プが封止されている。また、樹脂モールド１！１１の側
壁からはリードピン２・・・が延出されている。これら
夫々のリードピン２・・・は、樹脂モールド層１の内部
で前記半導体チップの端子と電気的に接続されている。A semiconductor chip (not shown) is sealed inside the resin mold layer 1. Furthermore, lead pins 2... extend from the side walls of the resin mold 1!11. These respective lead pins 2 are electrically connected to the terminals of the semiconductor chip inside the resin mold layer 1.

そして、各リード２・・・は図示のように平面実装用に
リードフォーミングされている。なお、樹脂モールド層
１には一般に頂面ｆ１、底°面ｆ２、上側側面ｆ３、下
側側面ｆ４が存在する（第１図（Ｂ）図示）。これらの
各面の表面仕上げ状態としては、鏡面、梨地面の二種類
があり、何れの仕上げ状態になるかは樹脂モールド８１
の形成に用いられるモールド金型内壁面の状態によって
決まる。そして、従来の樹脂封止型半導体装置の場合に
はｆ１〜ｆ４の何れの面も同じ表面仕上げになっている
。Each lead 2 . . . is lead-formed for planar mounting as shown. Note that the resin mold layer 1 generally has a top surface f1, a bottom surface f2, an upper side surface f3, and a lower side surface f4 (as shown in FIG. 1(B)). There are two types of surface finish for each of these surfaces: a mirror surface and a satin surface, and the finish condition depends on the resin mold 81.
It is determined by the condition of the inner wall surface of the mold used to form the mold. In the case of a conventional resin-sealed semiconductor device, all of the surfaces f1 to f4 have the same surface finish.

上記第１図（Ａ）（Ｂ）の樹脂封止型半導体装置は、第
２図に示す状態でプリント配線基板３上に実装される。The resin-sealed semiconductor device shown in FIGS. 1A and 1B is mounted on the printed wiring board 3 in the state shown in FIG.

その際、樹脂モールド層１の底面ｆ１は図示のように接
着剤層４を介して基板３に接着固定される。At this time, the bottom surface f1 of the resin mold layer 1 is adhesively fixed to the substrate 3 via the adhesive layer 4 as shown in the figure.

また、樹脂モールド層１の頂面ｆ１には品名、ロット番
号等のマークが付され、このマークはレーザ光照射によ
り行なわれる。Further, a mark such as a product name, lot number, etc. is attached to the top surface f1 of the resin mold layer 1, and this mark is made by laser beam irradiation.

〔背景技術の問題点〕[Problems with background technology]

樹脂モールド層表面の二種類の仕上げ状態のうち、鏡面
はレーザマーキング性に優れている反面、基板３に対す
る接着性が弱い問題かめる。他方、梨地面は基板に対す
る接着性には優れているが、レーザマークを実施した場
合のコントラストが悪く、マークが識別し難い問題があ
る。Of the two finishing states of the surface of the resin mold layer, the mirror surface has excellent laser marking properties, but has the problem of weak adhesion to the substrate 3. On the other hand, although the satin surface has excellent adhesion to the substrate, there is a problem in that the contrast is poor when a laser mark is applied, making it difficult to identify the mark.

従って、樹脂モールド層の全表面を同一の表面仕上げ状
態にしていた従来の樹脂封止型半導体装置では、レーザ
マーキング性と基板に対する接着性の両者を同時に満足
させることができず、その何れかを犠牲にせざるを得な
い問題があった。Therefore, in conventional resin-sealed semiconductor devices in which the entire surface of the resin mold layer has the same surface finish, it is not possible to satisfy both laser marking properties and adhesion to the substrate at the same time. There was a problem that I had no choice but to sacrifice.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、平面実装タ
イプの樹脂封止型半導体装置におけるレーザマーキング
性および基板に対する接着性の両者を同時に満足させる
ことを目的とするものである。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to simultaneously satisfy both laser marking properties and adhesiveness to a substrate in a flat-mount type resin-sealed semiconductor device.

〔発明の概要〕[Summary of the invention]

本発明は、平面実装タイプの樹脂封止型半導体装置にお
いて、樹脂モールド層の表面仕上げ状態をマーキング面
は鏡面とし、基板に接する面は梨地面としたことを特徴
とするものである。The present invention is a flat-mount type resin-sealed semiconductor device characterized in that the surface finish of the resin mold layer is such that the marking surface is mirror-finished and the surface in contact with the substrate is satin-finished.

上記のように、マーキング面はレーザマーキング性に優
れた鏡面仕上げとする一方、基板に対する接着面は接着
性に優れた梨地面とすることで、レーザマーク性能およ
び実装時の基板に対する接着性の何れをも同時に満足す
ることができる。As mentioned above, the marking surface has a mirror finish with excellent laser marking properties, while the adhesive surface to the board has a matte surface with excellent adhesion, which improves both laser marking performance and adhesion to the board during mounting. can be satisfied at the same time.

〔発明の実施例〕[Embodiments of the invention]

第１図（Ａ）（Ｂ）と同一の外形を有する平面実装タイ
プの樹脂封止型半導体装置について、本発明を適用した
。The present invention was applied to a flat-mount type resin-sealed semiconductor device having the same external shape as in FIGS. 1(A) and 1(B).

即ち、この実施例では第１図（Ｂ）に示した樹脂モール
ド層の四種類の平面のうち、マーキング面ｆ１を鏡面と
し、基板に対する接着面ｆ２を梨地面とした。また、モ
ールド金型の製作を容易にするために、上側側面で３は
マーキング面で１と同じ鏡面、下側側面ｆ４は接着面ｆ
２と同じ梨地面とした。That is, in this example, among the four types of planes of the resin mold layer shown in FIG. 1(B), the marking surface f1 was a mirror surface, and the adhesive surface f2 to the substrate was a satin surface. In addition, in order to facilitate the production of the mold, 3 on the upper side is the marking surface, which is the same mirror surface as 1, and the lower side f4 is the adhesive surface f.
The same pear surface as 2 was used.

上記実施例の樹脂封止型半導体装置では、マーキグ面ｆ
１が鏡面であるためレーザマークの良好なコントラスト
が得られる。また、基板に対する接着面ｆ３は梨地面で
あるため、第２図のように接着剤層４を介してプリント
配線基板３に実装する際にも良好な接着性が得られる。In the resin-sealed semiconductor device of the above embodiment, the marking surface f
Since 1 is a mirror surface, good contrast of the laser mark can be obtained. Further, since the adhesive surface f3 to the substrate is a satin surface, good adhesiveness can be obtained even when mounting on the printed wiring board 3 via the adhesive layer 4 as shown in FIG.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明にＫよれば平面実装タイプ
の樹脂封止型半導体装置に優れたレーザマーキング性を
付与でき、且つプリント配線基板上に実装する際の接着
性をも向上できる等、顕著な効果が得られるものである
。As detailed above, according to the present invention, it is possible to impart excellent laser marking properties to a flat-mount type resin-sealed semiconductor device, and it is also possible to improve adhesiveness when mounting it on a printed wiring board. , a remarkable effect can be obtained.

置を示す正面図であり、同図（Ｂ）はその側面図、第２
図は第１図（Ａ）（Ｂ）の樹脂封止型半導体装置を配線
基板上に平面実装した状態を示す図である。FIG.
The figure shows a state in which the resin-sealed semiconductor device of FIGS. 1A and 1B is planarly mounted on a wiring board.

１・・・樹脂モールド層、２・・・リード、３・・・配
線基板、４・・・接着剤層。DESCRIPTION OF SYMBOLS 1... Resin mold layer, 2... Lead, 3... Wiring board, 4... Adhesive layer.

Claims (1)

【特許請求の範囲】[Claims] 平面実装タイプの樹脂封止型半導体装置において、樹脂
の表面状態をマーキング面は鏡面とし、基板に接する面
は梨地面としたことを特徴とする樹脂封止型半導体装置
。1. A resin-sealed semiconductor device of a flat mount type, characterized in that the marking surface of the resin is a mirror surface, and the surface in contact with a substrate is a matte surface.
JP60077088A 1985-04-11 1985-04-11 Resin sealed type semiconductor device Pending JPS61234551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60077088A JPS61234551A (en) 1985-04-11 1985-04-11 Resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60077088A JPS61234551A (en) 1985-04-11 1985-04-11 Resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPS61234551A true JPS61234551A (en) 1986-10-18

Family

ID=13624022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60077088A Pending JPS61234551A (en) 1985-04-11 1985-04-11 Resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPS61234551A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218055A (en) * 1990-01-23 1991-09-25 Matsushita Electron Corp Resin sealed semiconductor package
JP2020152625A (en) * 2019-03-23 2020-09-24 株式会社新興製作所 Epitaxial compound composite substrate and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218055A (en) * 1990-01-23 1991-09-25 Matsushita Electron Corp Resin sealed semiconductor package
JP2020152625A (en) * 2019-03-23 2020-09-24 株式会社新興製作所 Epitaxial compound composite substrate and method for manufacturing the same

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