JPS61234057A - Ic package - Google Patents

Ic package

Info

Publication number
JPS61234057A
JPS61234057A JP7572185A JP7572185A JPS61234057A JP S61234057 A JPS61234057 A JP S61234057A JP 7572185 A JP7572185 A JP 7572185A JP 7572185 A JP7572185 A JP 7572185A JP S61234057 A JPS61234057 A JP S61234057A
Authority
JP
Japan
Prior art keywords
package
leads
lead wire
conductor
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7572185A
Other languages
Japanese (ja)
Inventor
Masahiro Ouchi
大内　雅弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7572185A priority Critical patent/JPS61234057A/en
Publication of JPS61234057A publication Critical patent/JPS61234057A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve the high frequency characteristics of an IC package by adding the second leads corresponding by 1:1 to the first leads of the package inside the package from the first leads, thereby enabling to match at a point near an IC chip. CONSTITUTION:The first leads 2 are electrically connected with a conductor pattern 4 in an IC package body 1, and formed in a FLAT shape, and the second leads 3 are formed in a PGA type. It is necessary to strengthen the first leads 2 and the mounting strengths to increase in a structure to a pitch of 1/10 or 1/20 inch. However, since the second leads 3 are not used to secure the IC itself, they can be considerably reduced in size, and mounted near the central portion of the IC body. The leads 2 are soldered to a conductor 11, which is further connected with a matching resistor 9 of 50OMEGA formed by a thin film, and a resistor 9 is further connected with a conductor 10. The conductor 10 is eventually connected with a power source (e.g., GND) of low impedance.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路を搭載する為のパッケージ（以
下ＩＣパッケージと称す）に関し、特に高周波特性の優
れたＩＣパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for mounting a semiconductor integrated circuit (hereinafter referred to as an IC package), and particularly to an IC package with excellent high frequency characteristics.

〔従来の技術〕[Conventional technology]

従来ｒｃパッケージはＤＩＰ型、ＦＬＡＴ型、ＰＧＡ型
、ＬＣＣ型等各種の形状を有するものが開発されている
。ＩＣパッケージの主目的は、ＩＣを外部環境から保護
することであり、その為にＩＣはボンディングワイヤー
によりＩＣパッケージのステッチにボンディングされか
つ外部に信号を引き出す為のリードにステッチは接続さ
れている。第６図にＦＬＡＴ型の平面図、第７図に断面
図を示す。同図で２がリード線でステッチ、ボンディン
グワイヤーを介してＩＣに信号もしくは電源を供給して
いる。リード線の構造、強度、ピッチ等の機械的寸法は
、使用される条件で決定さｎるのが通常である。この中
で強度については主にハンダ付によりプリント基板、セ
ラミック基板等に付けられる事を考慮すると、寸法はあ
る程度の大きさが必要になる。また標準化が考慮された
ＩＣパッケージにおいては、リード線のピッチは１／１
０インチ又は１７２０インチが採用されている。Conventionally, rc packages having various shapes such as DIP type, FLAT type, PGA type, and LCC type have been developed. The main purpose of an IC package is to protect the IC from the external environment, and for this purpose the IC is bonded to the stitches of the IC package by bonding wires, and the stitches are connected to leads for extracting signals to the outside. FIG. 6 shows a plan view of the FLAT type, and FIG. 7 shows a sectional view. In the figure, 2 is a lead wire that is stitched and supplies signals or power to the IC via a bonding wire. The structure, strength, pitch, and other mechanical dimensions of the lead wire are usually determined by the conditions under which it will be used. In terms of strength, considering that it is mainly attached to printed circuit boards, ceramic boards, etc. by soldering, a certain degree of size is required. In addition, in IC packages designed for standardization, the pitch of lead wires is 1/1.
0 inch or 1720 inch is adopted.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のＩＣパッケージでは、多数の信号線を扱
う様な場合、そのリード線の本数は多くな抄その結果Ｉ
Ｃパッケージの大きさも大きくなる。この為に、ＩＣパ
ッケージのリード線からＩＣまで信号線長も長くなり、
特に高周波を扱うようなＩＣにおいては、不整合に伴う
反射が問題にになる。ＳＳＩレベルのＩＣでは、ＩＣ内
部に整合用終端抵抗を設けるのが通常であるが多ピンの
ＩＣでは、終端抵抗部による発熱が大きくなり、例えば
論理ＩＣでは、本来論理動作をする為の回路数（ゲート
数）が少なくなり集積度の点から非常に不利になる。In the conventional IC package described above, when handling a large number of signal lines, the number of lead wires is large.
The size of the C package also increases. For this reason, the signal line length from the IC package lead wire to the IC becomes longer.
Especially in ICs that handle high frequencies, reflections caused by mismatching become a problem. SSI level ICs usually have a matching termination resistor inside the IC, but in multi-pin ICs, the termination resistor generates a lot of heat.For example, in logic ICs, the number of circuits required to perform logic operations is (number of gates) is reduced, which is very disadvantageous from the point of view of integration.

また、終端抵抗をＩＣパッケージのリードの真近に付は
九としてもＩＣパッケージ内部の導体パターンからステ
ッチにいたるまでの不整合を正すことはできない。Further, even if the terminating resistor is placed close to the leads of the IC package, it is not possible to correct misalignment from the conductor pattern to the stitching inside the IC package.

以上水したように多ビンの高周波用のＩＣにおいては、
ＩＣチップの性能は良くてもパッケージによりそのＩＣ
の性能が制約を受けるという欠点６　　　　　　　があ
る。As mentioned above, in multi-bin high frequency ICs,
Even if the performance of an IC chip is good, the IC chip may be affected by the package.
There is a drawback6 that the performance is limited.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のＩＣパッケージは、第１のリード線にｌ対ｌに
対応する第２のリード線が第１のリード線よりもパッケ
ージの内側に存在しかつ第１のリード線と第２のリード
線は電気的に接続されている事を特徴とする。In the IC package of the present invention, the second lead wire corresponding to the first lead wire is present inside the package than the first lead wire, and the first lead wire and the second lead wire are are characterized by being electrically connected.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の実施例の平面図である。ｌはＩＣパッ
ケージ本体、２は第１のリード線、３は第２のリード線
である。第１のリード線はＩＣパッケージ本体の中で導
体パターンにより電気的に接続さｎている。本実施例で
は、第２図の断面図に示す様に第１のリード線はＦＬＡ
Ｔｆｉをしておし第２のリード線はＰＧＡｆｉの様にな
っている。FIG. 1 is a plan view of an embodiment of the invention. 1 is an IC package body, 2 is a first lead wire, and 3 is a second lead wire. The first lead wire is electrically connected by a conductive pattern within the IC package body. In this embodiment, the first lead wire is FLA as shown in the cross-sectional view of FIG.
The second lead wire is similar to PGAfi.

また、本実施例のＩＣパッケージは、２なるリード線を
ハンダ付した時の強度でＩＣ自体を固定することを前提
にしている。したがりて２のリード線は、取り付は強度
を強くする必要があり構造的にも大きくなり標準的には
１／１０インチ又は１７２０インチのピッチになる。し
かし、第２のリード線３はＩＣ自体を固定する目的には
使用しないからかなり小さくできＩＣ本体の中心部分に
近い所に取りつけることができる。この為にステッチの
近傍にリードがでている事になる。第３図に詳しい断面
図を示す。２なるリード線から入った信号は、４なる導
体パターンを介してステッチ７、ボンディングワイヤー
６を通りＩＣチップ５に達する。４なる導体パターンは
ステッチの近傍で３なる第２のリード線に分枝している
。導体パターン４は、高周波用ＩＣパッケージでは、ス
トリップライン、コープレーナ型等５θΩ系に整合を取
っている。本実施例でも５０Ωに整合がとら几ている。Further, the IC package of this embodiment is based on the premise that the IC itself is fixed with the strength when the two lead wires are soldered. Therefore, the lead wires 2 need to be attached with strong strength and are structurally large, and the standard pitch is 1/10 inch or 1720 inch. However, since the second lead wire 3 is not used for the purpose of fixing the IC itself, it can be made considerably smaller and can be attached near the center of the IC body. For this reason, a lead appears near the stitch. A detailed sectional view is shown in FIG. The signal input from the lead wire No. 2 passes through the stitch 7 and the bonding wire 6 via the conductor pattern No. 4, and reaches the IC chip 5. The conductor pattern 4 branches into a second lead 3 near the stitch. The conductor pattern 4 is matched to a 5θΩ system such as a strip line or a coplanar type in a high frequency IC package. In this embodiment as well, matching to 50Ω is achieved.

本実施例では、第１、第２のリード線は同一面に配置さ
れているが、第１のリード線は第２のリード線と反対の
面もしくは、ＬＣＣ構造のようにＩＣパッケージ本体の
側面にあってもかまわない。In this embodiment, the first and second lead wires are arranged on the same surface, but the first lead wire is arranged on the opposite surface to the second lead wire, or on the side of the IC package body as in the LCC structure. It doesn't matter if it's in

次に本発明によるＩＣパッケージの実装方法について説
明する。第４図は、本発明によるＩＣパッケージをセラ
ミック基板８に実装した例である。Next, a method for mounting an IC package according to the present invention will be explained. FIG. 4 shows an example in which an IC package according to the present invention is mounted on a ceramic substrate 8.

第１のリード線２はセラミック基板８にハンダ付されこ
の部分で強度をもたせ固定している。また第２のリード
線３はセラミック基板に開けられた穴を通して基板の反
対面へ出ている。さらにＩＣが取り付けられている反対
面を第５図に示しているが同図に示す様に第２のリード
線は１１なる導体にハンダ付されさらに導体は、９なる
薄膜により形成された５０Ωの整合用抵抗に接続され、
さらに９なる抵抗は、１０なる導体に接続されている。The first lead wire 2 is soldered to the ceramic substrate 8 to provide strength and fixation. Further, the second lead wire 3 extends to the opposite side of the ceramic substrate through a hole made in the ceramic substrate. Furthermore, the opposite side where the IC is attached is shown in Figure 5, and as shown in the same figure, the second lead wire is soldered to a conductor numbered 11, and the conductor is a 50Ω conductor made of a thin film numbered 9. connected to a matching resistor,
Furthermore, resistor number 9 is connected to conductor number 10.

１０なる導体は最終的には低インピーダンスの電源（例
えばＧＮＤ）に接続される。The conductor 10 is ultimately connected to a low impedance power source (eg, GND).

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＩＣパッケージに第１の
リード線に°１対１に対応する第２のリード線を第１の
リード線よりもＩＣパッケージの内側に付加することに
より、ＩＣチップの近傍で整合を取ることが可能になる
。As explained above, the present invention provides an IC chip by adding a second lead wire that corresponds one-to-one to the first lead wire to the IC package inside the IC package than the first lead wire. It becomes possible to achieve matching in the vicinity of .

この為にＩＣパッケージ内部の不整合がなくなり、パッ
ケージを含めて高周波特性のよい半導体集積回路装置を
製造できる効果がある。Therefore, there is no mismatch inside the IC package, and it is possible to manufacture a semiconductor integrated circuit device including the package with good high frequency characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明によるＩＣパッケージの平面図、第２図
は断面図、第３図は断面図をさらに詳しく示したもの、
第４図は本発明によるＩＣパッケージをセラミック基板
に実装した例、第５図はＩＣパッケージを実装したセラ
ミック基板の裏面の例、第６図は従来のＩＣパッケージ
の１例の平面図、第７図は断面図である。 同図において、１・・・・−Ｉ　Ｃパッケージ本体、２
・・・・・・第１のリード線、３・・・・・・第２のリ
ード線、４・、、　＋＋＋　Ｉ　Ｃ、＜ッケージ内部の
導体パターン、５・旧・・ＩＣチップ、６・・・・・・
ボンディングワイヤー、７・・・・・・ステッチ、８・
・・・・・セラミック基板、９・・・・・・５０Ω薄膜
抵抗、１０・・・・・・導体パターン、１１・・・・・
・導体パターンである。 竿　Ｉ　国 ＄　２　図 一第　３ＴＩＪ σ 第　４１！０ 茅　５　図 ＄　Ｚ　圀 滓　７ｒｓｌFIG. 1 is a plan view of an IC package according to the present invention, FIG. 2 is a sectional view, and FIG. 3 is a sectional view showing the sectional view in more detail.
FIG. 4 is an example of an IC package according to the present invention mounted on a ceramic substrate, FIG. 5 is an example of the back side of a ceramic substrate on which an IC package is mounted, FIG. 6 is a plan view of an example of a conventional IC package, and FIG. The figure is a sectional view. In the same figure, 1...-IC package body, 2
...First lead wire, 3...Second lead wire, 4... +++ I C, <Conductor pattern inside the package, 5. Old...IC chip, 6.・・・・・・
Bonding wire, 7...Stitch, 8.
... Ceramic substrate, 9 ... 50Ω thin film resistor, 10 ... Conductor pattern, 11 ...
・It is a conductor pattern. Rod I Country $ 2 Figure 1 3TIJ σ No. 41! 0 Kaya 5 Figure $ Z Country 7rsl

Claims (1)

【特許請求の範囲】[Claims] 　半導体集積回路装置を搭載する為のパッケージにおい
て、第１のリード線に１対１に対応する第２のリード線
が前記第１のリード線よりもパッケージの内側に存在し
、かつ第１のリード線と第２のリード線は電気的に接続
されている事を特徴とするパッケージ。In a package for mounting a semiconductor integrated circuit device, a second lead wire corresponding to the first lead wire on a one-to-one basis is present inside the package than the first lead wire, and A package characterized in that the wire and the second lead wire are electrically connected.
JP7572185A 1985-04-10 1985-04-10 Ic package Pending JPS61234057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7572185A JPS61234057A (en) 1985-04-10 1985-04-10 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7572185A JPS61234057A (en) 1985-04-10 1985-04-10 Ic package

Publications (1)

Publication Number Publication Date
JPS61234057A true JPS61234057A (en) 1986-10-18

Family

ID=13584409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7572185A Pending JPS61234057A (en) 1985-04-10 1985-04-10 Ic package

Country Status (1)

Country Link
JP (1) JPS61234057A (en)

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