JPS61233851A - Address conversion system - Google Patents

Abstract

PURPOSE:To attain high speed address convertion by using addition/subtraction only without using multiplication in read/write of picture element information constituting a graphic from or the like. CONSTITUTION:In reading/writing picture element information constituting a graphic form or the like normally to a memory element, the memory elements in connected position relation are subjected to continuous read/write in many cases. Whether or not a memory element G(i,j) read/written present in a step 101 is connected to a memory element G(I,J) read/written just before or not is checked and when they are connected, 9 kinds of connecting states are identified form the values of (i-I) and (j-J) are identified according to table 105 in a step 104, and an address conversion equation corresponding to the said connecting state is decided by using the result. The linear memory address of the memory element G(i,j) is obtained from the content of a variable A by using the said address conversion equation and stored in a variable A by using the said address conversion equation and stored in a variable (a). Since no multiplication is included in each conversion formula included a table 105, the equation are all computed in high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to the case where a one-dimensionally addressed memory is treated as a two-dimensional array of memory elements and controlled for processing image data, etc. of.

This relates to a method for converting two-dimensional coordinate values into one-dimensional memory addresses.

[Conventional technology]

Figure 2 shows the memory address one-dimensionally from address 0 to mXn-1 (m and rl are positive integers, each representing the number of columns and two rows of a two-dimensional array, which will be described later). FIG. 3 is a diagram showing the relationship between one element and an address. In the figure, M
C&) represents the element at address a in this memory (0≦a≦
mXn-1 and breath is an integer).

Here, when the above memory is used for processing image data, etc., the above memory corresponds to the pixel array of the image. It is necessary to control it by treating it as a two-dimensional array of memory elements.

FIG. 3 is a diagram showing the structure of the above memory when it is regarded as a two-dimensional memory element array of n rows by m columns. In the figure, G(1,j) represents a memory element located in the j-th row, column 1 (0≦l≦m-1゜0≦j≦n-1 and 1.
j is an integer).

By the way, in FIGS. 2 and 3, the memory element M (&
) and memory element G (i, j) are the same memory element, that is, if the one-dimensional meso element whose address is a is located at the coordinates (1, j) in the two-dimensional array In this case, the following relationship (1) holds between the one-dimensional memory address a and the two-dimensional coordinates (1, j).

, Yol + j X m...
・(1) Next, assume 1 (0≦i, 6m-1:0≦j, t≦n-1) for %4 integers i and J, and between these, the following formula and When formula 131 holds true at the same time, it is said that memory element G(l,j) and memory element G(k,t) are connected in the two-dimensional array.

1l-kl=o or 1 (2) lj
-Ll=o or 1 In a memory configuration such as 131 or more, when pixel development of one figure, etc. is performed and written to the above two-dimensional memory element array, the above is written for each memory element corresponding to these pixels. According to formula (1), calculate the conversion from two-dimensional coordinates to one-dimensional memory address,
Depending on the result, it is necessary to write to the memory element corresponding to the pixel.

[Problem that the invention seeks to solve]

In the conventional address conversion method, it is necessary to perform the multiplication by jXm in equation (1) above every time one memory element is converted, and when a microprocessor with a slow multiplication speed is used, the address conversion process There is a problem that it takes a lot of time to write the pixel information to the mesori element, and as a result, writing of pixel information to the mesori element becomes slow. A similar problem also exists regarding reading out pixel information from memory elements.

The present invention was made in order to solve such problems, and an object of the present invention is to perform address conversion at high speed by using only addition and subtraction, without using multiplication when reading and writing pixel information constituting one figure, etc.

[Means for solving problems]

The address conversion method according to the present invention includes means for holding the two-dimensional coordinates of the memory element read and written just before, and the one-dimensional memory address of the memory element, and the memory element to be read and written next Calibrates whether or not the memory element is in a connected position, and if it is in a connected position, the next read/write is performed by adding or subtracting a specific value to the one-dimensional memory address of the memory element read and written just before It consists of means for determining the one-dimensional memory address of the memory element to be processed.

[Effect]

Normally, when reading and writing pixel information constituting a figure, etc. to a memory element, it is often read and written continuously to memory elements that are in a connected positional relationship.
According to the present invention, in many cases, address conversion can be performed simply by adding or subtracting a specific value to the one-dimensional memory address of the memory element read or written just before, without using multiplication. Speed address conversion becomes possible.

〔Example〕

FIG. 1 is a flowchart showing one embodiment of the present invention, and shows the operation of the address conversion system according to the present invention in a mesostructure as shown in FIG. 2 and FIG. 3. Next K,
FIG. 4 shows an embodiment of the hardware configuration of the present invention. In FIG. 1, 10 is a processing unit that executes the processing shown in FIG. 1, 20 is a one-dimensionally addressed memory, and 30 is a currently controlled A register that holds the one-dimensional memory address a of the memory element to be controlled, 4G is the memory element 1 that was controlled just before.
The registers that hold the dimensional memory address, so and go, are registers that hold the two-dimensional coordinate value 1 or FiJ of the memory element that was controlled immediately before. Alternatively, it may be implemented as a wired logic configuration.

In step 101 in Figure 1, the two-dimensional coordinates of the element to be read or written are set in the variable (1, j), and the memory containing the last read/write is set in the variable CI, J). The two-dimensional coordinates of the elements are held.

Here, in step 101, it is determined whether the memory element G (1, j) that is currently being read or written is connected to the mesori element G (I, J) that was read or written just before using the equation (21 and (Calibrate according to formula 31.

As a result, if they are not connected, in step 102, address conversion is performed in accordance with equation (1) as before, to obtain the one-dimensional memory address of memory element G(i, j), and store it in variable a. Next, in step 103, in preparation for address conversion for the primary memory element, the current two-dimensional coordinates are held in variables (1, J), and the current one-dimensional memory address is held in variable A.
Finishes address translation for the current memory element.

On the other hand, as a result of the calibration in step 101 of FIG. 1, the two memory elements G(i,,j) and G(I,J
) are connected, proceed to step 104. In step 104, the one-dimensional memory address of the memory element G (I, J) that was just read or written is stored in the variable.

Here, in step 104, nine types of connection states are identified from the values of i-I and j-J, and the address conversion formula corresponding to the above-mentioned connection state is determined from Table 105 using the results. That is, since the above two memory elements G(1,j) and G(I,J) are connected, 1-I and j
The value of -J is as shown in the following equations (41 and (5)), and there are nine combinations of the values of i-I and j-J. Therefore, the values of i-I and j-J Nine types of connection states can be identified.

1-I=-1 or 0 or 1 (4)j
-J=-1! 9 is O or 1 (5; Then, use the above address conversion formula to find the one-dimensional mesori address of the element G (1, j) from the contents of the variable A,
Store in variable a.

For example, when 1-I=O and j-J=1, memory element G
The one-dimensional memory address of (1,j) is.

The number of horizontal elements m in the two-dimensional memory element array is added to the contents of the variable person.
It is calculated as the sum of

Here, since each conversion formula included in Table 1 105 does not include multiplication, it is possible to calculate all of them at high speed.

Next, in step 103, the variable (
I, J) and variables are set, and address conversion for the current memory element is completed.

〔Effect of the invention〕

In this invention, as explained above, 9. By using the connectivity between the memory element that was read or written just before and the memory element that is currently being read or written, it is possible to simply add or subtract a specific value to the one-dimensional memory address of the memory element that was read or written just before, without using multiplication. This has the effect of allowing address translation to be performed at high speed.

[Brief explanation of the drawing]

Fig. 1 is a flowchart showing an embodiment of the present invention, Fig. 2 is an explanatory diagram showing the structure of a one-dimensionally addressed mesori, and Fig. 3 assumes that the above memory is a two-dimensional memory element array. FIG. 4 is a block diagram showing an embodiment of the hardware structure of the present invention. In the figure, M(a) is the memory element at address a, G (l, j
) is a memory element located in the 5th row and 1st column, 10 is a processing unit, 20 is a memory, and 30.40.50.6 (1!: register). Note that the same reference numerals in each figure are the same or similar. Parts shown. Patent applicant Mitsubishi Electric Corporation Ov---M e 口Σ II Oy (y O- White

Claims (1)

[Claims] One-dimensionally addressed memory is divided into two memory elements.
In an address conversion method from two-dimensional position coordinates to a one-dimensional memory address when the control is performed by treating the first memory element as a two-dimensional array, coordinate values representing the position of the first memory element that has just been converted in the two-dimensional array, and 1 corresponding to the coordinate value
A temporary storage means for holding a dimensional memory address, detects that a second memory element to be currently converted is in a connected positional relationship with the first memory element in the two-dimensional array, and and an arithmetic processing means for calculating a specific value corresponding to the connected positional relationship of the second memory element, and when the second memory element is in the connected positional relationship with the first memory element, . An address conversion method characterized in that the one-dimensional memory address of the second memory element is determined by adding or subtracting the specific value to the one-dimensional memory address of the first memory element.