JPS61230584A - Double density scanning circuit - Google Patents

Abstract

PURPOSE:To obtain a double density scanning circuit being prevented from the occurrence of a line flicker without deteriorating vertical resolution by providing a field memory and executing properly a scanning line interpolation in consideration of the information of the previous field. CONSTITUTION:A television signal is inputted to an input terminal 1 and a 1 line memory 18 delays the signal by one line. An adder 7 and a 1/2 attenuator 8 calculate the average of the inputted signal and the 1 line delay signal. By comparing the inputted signal with the 1 line delay signal and the delay signal of previous one field, an interpolation signal deciding circuit 21 selects either one out of the signals inputted to a switch 22 as an interpolation signal. Regarding write to two line memories, it is assumed that the television signal delayed by one line is written at one line of the first half and the interpolation signal is written at one line of the last half and the switching of an address is alternately performed by every one sampling. A switch 26 is closed to the line memory of a reading side by the output of a line memory control circuit 11 and a double density scanning signal is outputted at an output terminal 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the change in the high-purchase 1L signal of color television broadcasting, and particularly to a double@travel circuit suitable for digital television.

[Background of the invention]

Due to advances in high-speed and large-scale LSI technology.

It has now become possible to digitally process the WK image and whistle signals on TV, which previously had been processed analogously.

Along with this, attempts are being made in various places to make the TV fI issue, which uses the staring contest method, more like an Oka painting.

One of these is a technology that uses memory to double the amount of distance traveled. In order to reduce the transmission band, the current television broadcasting system uses interlaced scan f (interlaced scan f) to eliminate scanning source disturbances and line 7 errors that occur due to non-interlaced scanning. A circuit that uses this is called a double-density scanning circuit, and an example of this is disclosed in Japanese Patent Laid-Open No. 79578/1983.

Figure 2 is a sketch showing the basic idea.
is an input terminal, 2 is a switch, 3 to 5 are 1 running memory (line memory), 6 is a switch, 7 is an adder, 8 is '
/@translator, 9 is a switch, 10 is an output terminal, 11 is a line memory control circuit, 12 to 14 are continuation/convolution control signals (Le V side control signals), 15 is a switching signal, 15 and 17 are selections This is the line memory output.

Next, we will clarify this operation. It is assumed that one of the five primary color KGB signals (for example, R9!-1'j-) is input to the input terminal 1. If line memories 3 to 5 are A, H, and C, respectively, the valley memory is the third one.
Perform l1lfj: at the timing shown in the figure. For example, when line memory 3 is in the incubation period V), other line memory 4. The line memory 5 is in the continuous output period CR). Also,
Successive output from each line memory is performed at a speed of 2Wt.

Therefore, as shown in FIG. 5, pages are printed twice in one line period. . This R/W (7) i control is based on the A/F control signals 12 to 12 output from the line memory control circuit 11.
14. First, when a signal is input to the input terminal 1, the switch 2 is connected to the three line memories 3 to 5 every line cycle, and the 0 convolution input to the line memory is connected to the three line memories 3 to 5 for one convolution period. Once it's over, it will move on to the continuous release period, where 4K < 9 will be released one after another during the chill line review.

The successively outputted signals are input to the switch 6 by the switching signal 15 from the line memory control circuit wr11.

Data in the line memory is selected and output at the timings shown at 1+6 and 17 in FIG. Outputs 16 and 17 from switch 6 are averaged by adder 7 and AIR attenuator 8 and input to switch 9.

The switch 9 is switched every line, and the output terminal 10 alternately outputs the original signal and the averaged interpolation signal as shown in Fig. 3, so that the signal input at twice the speed is outputted alternately. can be superior to

However, as mentioned above, current television signals perform interlaced scanning, so the newly interpolated position of the previous field and the temporary field f7
161 will be ground alternately. Therefore, the above-mentioned method has a great effect on eliminating f#f# visits.

ii in the previous field! In order to uniformly perform average interpolation without taking into account ruts, line 7 Ritsuka cannot remove all 11C of 5e. This was calculated using Figure 4.

In Figure 4,! 1 to 1- This is a set menu at a specific position on the back side, and in Figure 1, scanning is performed in a direction perpendicular to the paper surface and the field progresses from left to right. The fugi circles are actual Li1Ii lines, and the training circles are pixels newly created by scanning and interpolation. Now, let's set running f taste 11 to white running 31:M, and 4 and 4.
Assume that the image is a black scan, and the luminance changes greatly between the thresholds of 11 and 11. Now, scanning the first field @
l, tt, run 3! l:s's and 7. Since it is the average of , it is gray as shown in Figure 1. Even if the k & 2 field and the 3rd field are busy, the same interpolation method is applied to line 5. In this case, if we layer the scanning fsls, we will alternately repeat white and gray for each field, so line 7 will be reduced. but.

It won't go away completely. Also, gray legs! Since the rocks are interpolated, areas near the boundaries are removed, which also has the disadvantage of deteriorating the vertical resolution.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned conventional point of entry. The object of the present invention is to provide a double close-travel circuit which prevents the source of line 7 loss without deteriorating the resolution.

[Summary of the invention]

In order to achieve this purpose, I am using a misfiring BAcg.

For double run fill path due to line memory configuration.

By adding new field memory.

The interpolation signal of the scanning fil is determined within the 3iit field, also taking into consideration the image information of the previous field.

As a result, the image quality of the reservoir is not deteriorated.

Completely removing line 7 Ritsuka is q# mold.

It was. When determining the interpolation signal, the upper and lower running distances of the current Fieldon and the running distance of the previous field are used.
II! It is necessary to perform a j-based comparison, but this comparison is performed after the line memory is extracted at double speed, and high-speed hardware is required, leading to an increase in the price of the device. Therefore.

The interpolation signal is determined not after reading out the line memory 'ft but before inputting it to the line memory. Explain using. Figure 1 shows double @7I according to the present invention! In the figure, 18 is a 1-line memory 119 is a 1-field memory, 20 is a synchronization separation circuit, and 21 is an interpolation signal determination circuit M.
, 22-23 are switches, 24-25 are 2-line memories, and 26 is a switch. In addition, parts that are the same as those in the accompanying article are designated with the same sign.

Next, the operation of this example WA will be described with reference to the timing chart in FIG. 5, FIGS. 6 and 7. The TV signal shown in Figure 5 (α) is input to the human power layer IIK-.Here, the circled line III indicates the line W.
Th1 field (front field) and brown 2 field (
The current name of Fieldon is P'1FdJυ). Note that the negative sign before the previous number indicates that it is the scanning line one field before. Furthermore, the darashi 1 value g@1 is.

Let's read below 5. Set meal created by interpolation
It shows that. Now, 1 line memory 18 is 1m
Delay the input signal by one line as shown in E (b). In addition, the m calculator 7 and the subtractor 8 are connected to the input No. 4 and its 1
This is for finding the average of the line delay signal. Therefore, the switch 22 receives the input television signal, Part 1.
The line-delayed Jr II signal and the average signal thereof are inputted to the field memory 19.
produces a signal that delays the input television signal by one field. Like internal cause v1.

After outputting the read data (TV signal one field before) obtained from the address added by h1.

New data (TV N-1j in desk field) is folded into Oka's address.

The input signal and its one line delay M-'! , and as an interpolated signal by comparing with the delayed signal one field before.

One of the J@ numbers input to the switch 22 is selected. This interpolation signal fixing circuit 21 has been modified from the Keika shown in FIG. Namely.

27 is a foot attack ratio IIR device that compares the desk field foot f Maro and accumulates the result, 28 is a foot speed ratio IIR device that compares the current field and previous field speed fM and calculates the difference. ,2
9 is a decoder. Therefore, in Figure 7, it is #5.
L field foot acupuncture X.

Y, =My E/l/TonoshojtmZ ItC vs. Shi, a=l X-4'l and β=1λ-Zl Struggle Comparator 27. 28, and as a result, the decoder 29
determines which terminal of the switch 22 should be closed from α and β.
, 2, then both α and β are small, so the decoder 29 controls the switch 22 to use the average value of X and Y, that is, white, as the interpolation signal. As shown in the next diagram (b), if X and Z are white and Y is black, α is large and β is small, so
In this case, the output of the 11i memory 18 is interpolated 11R. In other words, the interpolated signal becomes white. 11 evil (as in C1, X is white, Y' and Z are stupid money, and α and β are large, so the input signal itself becomes an interpolated signal. In this case, it is a bear. The circuit 21 performs these five operations and determines an interpolation signal by comparing the run f of the bowl field with the run !- of the 10 field.

Now, let's return to the explanation of the first factor and FIG. 5.

The synchronization circuit 20 separates the synchronization signal of the input television signal and sends it to the line memory control circuit 11.The main memory control circuit 11 controls the switches 23 and 26 and also reads out the 2-line memos 924 and 25. and convolutional CR
/W) on a line-by-line basis. When one line memory is convolutional, the switch 23 is closed to that side, and when the other line memory is in the indulgence period, the switch 26 is closed to that side.

The writing and reading of the two-line meshes 24 and 25 will be explained below. Regarding convolution into the 2nd line mesh,
One line in the first half has a delayed TV signal, and one line in the second half has a delayed TV signal.

An interpolation signal g'4I knee W is input, and the addresses are alternately switched for each sample. In other words, as shown in FIG. 5(C), if the switch 22 is controlled mtt and the output of the 1-line memory 18 is folded into the first address of the first half (■)
Before the primary data is output.

Add the address to the first address in the second half and switch 22
Convolve the interpolated signal obtained from (■').

In the same way, 1 is alternately placed in the front and rear half of the 2-line memory 24.
The output of the line memory 18 and the interpolation signal are stored. In addition,
In this case, % 2 line memory 24 duty fj:i! all
Needless to say, K is twice the operating speed of the 1-line memory 18. During the read period performed on the next primary line, the stored one-line memory output (■) and the interpolated g1 number σ can be output by sending the next address to the two-line memory 24&C through the first half and the second half.

Of course, in this case as well, the address of the two-line memory 24 needs to be transferred to row 5 at twice the speed of the one-line memory 18.

The same applies to the 2-line memory 25.

! 11(d), when the 2-line memory 24 is convoluted, reading is performed, and when it is read, convolution is performed.

The switch 26 closes the line memory of the bladder outlet by the output of the line memory control circuit 11, and outputs the signal fIH'ij:f: shown in the same section to the output terminal 10.

If such a method is followed, as shown in Fig. 7, it is possible to perform the interpolation that takes into account the set meal Ill of the previous field, so that the line flicker can be completely eliminated without deteriorating the can be excluded.

〔Effect of the invention〕

As described above, according to the present invention, by storing the field memory, information in the previous field can also be taken into consideration.
IJi Yishu, to perform fd interpolation.

5 without deteriorating the vertical resolution as much as the conventional one.

It becomes possible to completely eliminate line 7.

In addition, the interpolation signal is determined from row 5 onward for the 1x vB set meal, and the interpolation signal is generated in advance, stored in memory, and then repeated in 2x cycles to perform the double density set meal. , the configuration of the adder circuit 7 and the complementary/open signal determining circuit 21 becomes easier.

[Brief explanation of the drawing]

Figure 2 is a block diagram showing the first part of the present invention.
The figure is a block diagram showing a conventional double-density scanning circuit. Figure 3 is the timing chart, Figure 42 is the interpolation (i
! An explanatory diagram showing the concept, FIG.
Timing chart of Keru Tani G-go. Figure 6 is a block diagram showing the interpolation signal determination circuit, and Figure m7 is an explanatory diagram showing the interpolation signal. 1...Input terminal 7...Adder 8°°°/!
Station equipment 10...Output terminal 11...Line memory control circuit 18...1 line memory 19.-1 field memory 20...Synchronization separation circuit 21...Interpolation signal determination circuit 22, 25...・Switch 24, 25
・・・2 line memory 26・-Switch Patent attorney Katsuo Ogawa 1. Figure 2. Figure 2. Figure 3. Figure 3. Figure 5. Figure 1■ -■'

Claims (1)

[Claims] 1) A line memory is provided, and by line interpolation, 2:1
In a double-density scanning circuit that converts an interlaced television signal into a non-interlaced television signal, a first means for obtaining information on two adjacent scanning lines in the current field; a second means for obtaining scanning line information corresponding to the scanning line information in the previous field; a third means for obtaining the difference between the two scanning line information in the current field; and a third means for obtaining scanning line information corresponding to the scanning line information in the previous field; fourth means for taking the difference from corresponding scan line information; and fifth means for determining an interpolated signal within the current field by the output from each of the third and fourth means;
A double-density scanning circuit comprising: sixth means for storing the obtained interpolated signal and input television signal; and seventh means for reading out the stored interpolated signal and television signal. 2) The sixth means has a storage capacity for two scanning lines, and stores the input television signal in the first half and the interpolation signal in the second half. double-density scanning circuit. 3) The sixth means is a double-density system according to claim 1, characterized in that there are two memories each having a storage capacity for two scanning lines, and writing and reading are performed alternately. scanning circuit.