JPS61229365A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS61229365A JPS61229365A JP6899185A JP6899185A JPS61229365A JP S61229365 A JPS61229365 A JP S61229365A JP 6899185 A JP6899185 A JP 6899185A JP 6899185 A JP6899185 A JP 6899185A JP S61229365 A JPS61229365 A JP S61229365A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- polycrystalline silicon
- gate electrode
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 239000010408 film Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 9
- 239000011521 glass Substances 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000005554 pickling Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000002253 acid Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体素子に係り、特に絶縁基板上に形成する
薄膜トランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a thin film transistor formed on an insulating substrate.
従来の薄膜トランジスタは、上記文献に記載のように、
多結晶品質のシリコン薄膜を用いて。Conventional thin film transistors, as described in the above literature,
Using polycrystalline quality silicon thin film.
ＭＯＳトランジスタを形成し、特にソース、ドレン領域
は、イオン打込み法等により不純物のドーパントを拡張
させ、低抵抗の領域を形成し、上記低抵抗領域の一部に
、電極、配線材料を接続布せでいた。In forming a MOS transistor, especially in the source and drain regions, impurity dopants are expanded by ion implantation or the like to form a low resistance region, and electrodes and wiring materials are connected to a part of the low resistance region. It was.
一般に薄膜トランジスタは、ガラス竺の基板の上に形成
されるが、比較的安価に入手できるガラスを用いると、
ガラスの歪温度が低いため、例えば、はうけい酸ガラス
では５８０℃、高温での熱処理ができなくなる。そのた
め、イオン打込み後にドパーントを活性化するための熱
処理を、低温で長時間はどこす必要がある。また、長時
間かけて熱処理したとしても単結晶シリコンの場合とは
異なり、逆阻止電圧の高いＰｎ接合を作ることはできず
、オフ状態での高抵抗の確保は、半導体薄膜の固有抵抗
によらねばならない、また、不純物をドーピングした領
域のシート抵抗も、単結晶シリコンにドーピングした場
合よりも大きくなり、配線領域として用いようとすると
、非常に大きな配線対抗となってしまう。Generally, thin film transistors are formed on a glass substrate, but if glass is available at a relatively low price,
Since the strain temperature of glass is low, for example, silicate glass cannot be heat treated at a high temperature of 580°C. Therefore, after ion implantation, it is necessary to perform heat treatment at low temperature for a long time to activate the dopant. Furthermore, even if heat treatment is performed for a long time, it is not possible to create a Pn junction with a high reverse blocking voltage, unlike in the case of single crystal silicon, and ensuring high resistance in the off state depends on the specific resistance of the semiconductor thin film. In addition, the sheet resistance of the region doped with impurities is also larger than that in the case of doping single crystal silicon, and if an attempt is made to use it as a wiring region, there will be a very large resistance to the wiring.
上記に示したように、シリコン薄膜中に不純物をドーピ
ングする方法では、プロセスが長くなりコスト増加の原
因になるのみでなく、低抵抗の領域が得られないという
欠点がある。As described above, the method of doping impurities into a silicon thin film not only requires a long process and increases costs, but also has the disadvantage that a region of low resistance cannot be obtained.
本発明の目的は、薄膜トランジスタのソース、ドレン領
域をイオン打込み等の不純物ドーピングすることなしに
、低抵抗の領域を形成することにある。An object of the present invention is to form low-resistance regions without doping the source and drain regions of a thin film transistor with impurities such as ion implantation.
一般に薄膜トランジスタは、オフ状態での抵抗を半導体
薄膜の固有抵抗でもたせており、接合を作る必要がない
ことに着目し、ソース、ドレン領域を金属シリサイド膜
のみで低抵抗化することである。In general, thin film transistors have off-state resistance based on the specific resistance of a semiconductor thin film, and focusing on the fact that there is no need to create a junction, the idea was to lower the resistance of the source and drain regions by using only metal silicide films.
本発明の実施例を第１図によって説明する。第１図は、
薄膜トランジスタの断面図である。An embodiment of the present invention will be explained with reference to FIG. Figure 1 shows
FIG. 2 is a cross-sectional view of a thin film transistor.
ガラス基板１の上に、島状に形成された多結晶シリコン
の領域２がある。このシリコン領域２は高抵抗の層であ
る。シリコン領域の両端に例えば白金シリサイド等の、
金属シリサイド領域６．８が形成されている。この部分
がソース、ドレン領域であり、ＰＳＧの膜等のパッシベ
ーション膜９の開孔部を通して、電極１０．１１が接続
している。多結晶シリコン領域２の中央部分の表面上に
：ゲート絶縁膜としての５ｉｎ２膜を介してゲート電極
４が形成されている。上記ゲート電極の表面領域にも、
金属シリサイド膜１１が形成されている。On a glass substrate 1, there is a polycrystalline silicon region 2 formed into an island shape. This silicon region 2 is a high resistance layer. Platinum silicide, etc., on both ends of the silicon region.
A metal silicide region 6.8 is formed. These portions are source and drain regions, and electrodes 10 and 11 are connected through the openings of the passivation film 9 such as a PSG film. A gate electrode 4 is formed on the surface of the central portion of the polycrystalline silicon region 2 via a 5in2 film serving as a gate insulating film. Also in the surface area of the gate electrode,
A metal silicide film 11 is formed.
ソース、ドレン間に電圧を印加しても、ゲート電圧がｏ
ｖであれば多結晶シリコン領域２の固有抵抗が高いため
ほとんど電流は流れない、ゲートデン電圧を高くすると
、ゲート電極４の下の多結晶シリコン領域にチャネル１
２が形成され、ソース、ドレン間に電流が流れ出す。Even if a voltage is applied between the source and drain, the gate voltage is
If the voltage is V, almost no current will flow because the specific resistance of the polycrystalline silicon region 2 is high.If the gate voltage is increased, the channel 1 will flow in the polycrystalline silicon region under the gate electrode 4.
2 is formed, and current begins to flow between the source and drain.
次に本発明の形成プロセスを第２図の断面図により説明
する。Next, the formation process of the present invention will be explained with reference to the cross-sectional view of FIG.
（ａ）、ガラス基板１の上に、第１の多結晶又は非晶質
のシリコン薄膜２（以下多結晶シリコン膜と呼ぶ）を形
成し、ホットエツチング技術により。(a) A first polycrystalline or amorphous silicon thin film 2 (hereinafter referred to as polycrystalline silicon film) is formed on a glass substrate 1 by hot etching technology.
島状に加工する。Process into islands.
（ｂ）、ゲート絶縁膜として、５ｉ０２膜３をＣＶＤ法
で形成し、その上に第２の多結晶シリコンＩ！Ｉｉ４を
形成する。(b) As a gate insulating film, a 5i02 film 3 is formed by the CVD method, and a second polycrystalline silicon I! Form Ii4.
（Ｃ）、ホトエツチング技術により、上記５ｉ０２膜お
よび多結晶シリコンｌｌ１４を除去し、薄膜トランジス
タのゲート電極をを形成する。(C) The 5i02 film and the polycrystalline silicon 114 are removed by photoetching to form a gate electrode of a thin film transistor.
（ｄ）、白金、その他の金属膜５をスパッタ法等で形成
する。(d) A platinum or other metal film 5 is formed by sputtering or the like.
（ｅ）、熱処理をする。金属膜５と多結晶シリコン膜２
，４が反応し、シリサイドＩ！ｉ６が形成される。その
場合、５ｉ０２膜３のエツチング側面では、金属膜５は
反応されずに残る６次に王水等の酸で洗浄する。未反応
の金属層は酸と反応して溶け、シリサイド膜６，７，８
は残る。(e) Heat treatment. Metal film 5 and polycrystalline silicon film 2
, 4 reacts and silicide I! i6 is formed. In that case, on the etched side of the 5i02 film 3, the metal film 5 remaining unreacted is washed with an acid such as aqua regia. The unreacted metal layer reacts with acid and melts, forming silicide films 6, 7, 8.
remains.
その結果、シリサイド膜６，７．８は。As a result, the silicide films 6, 7.8.
５ｉＯｚ膜３の側面で分離され、各々電気的分離された
領域になる。The regions are separated by the side surfaces of the 5iOz film 3 and are electrically isolated from each other.
（５）、次にＰＳＧ膜等のパッシベーション膜９を形成
し、その一部に開孔を設け、電極１０゜１１を形成する
。(5) Next, a passivation film 9 such as a PSG film is formed, a hole is provided in a part of the passivation film 9, and an electrode 10.degree. 11 is formed.
その結果リース電極１０．ドレン電極１１、ゲート電極
４のＭＯＳトランジスタが構成されφ。As a result, the lease electrode 10. A MOS transistor with a drain electrode 11 and a gate electrode 4 is configured with φ.
ソース、ドレンの抵抗領域は、シリサイド層６゜８で形
成され、この領域はゲート電極５の直下まで延びており
、ゲート電極をマスクとしたいわゆるセルファライン構
造と同じ効果を示している。The source and drain resistance regions are formed of a silicide layer 6°8, and extend directly below the gate electrode 5, exhibiting the same effect as a so-called self-line structure using the gate electrode as a mask.
本発明によれば、ソース、ドレンの領域を、イオン打ち
込み、長時間アニールの工程の代りに、金属膜形成、ア
ニールの工程で形成することができる。プロセスの所要
時間使用装置の価格等で比較すれば、後者の方が、より
安価のプロセスになる。According to the present invention, the source and drain regions can be formed by metal film formation and annealing steps instead of ion implantation and long-time annealing steps. If you compare the time required for the process and the price of the equipment used, etc., the latter will be a cheaper process.
また、形成された領域のシート抵抗を比較する。Also, the sheet resistances of the formed regions are compared.
発明者らの実験によれば、多結晶シリコンにリンをイオ
ン打ち込みし、５００℃、２０時間のアニールをした時
のシート抵抗は、１００〜６００Ω／口であったのに対
し、多結晶シリコンに白金をスパッタし、５００℃、１
０分間のアニールしたときのシリサイドのシート抵抗は
、５〜２０Ω／口であった。According to experiments conducted by the inventors, when polycrystalline silicon was ion-implanted with phosphorus and annealed at 500°C for 20 hours, the sheet resistance was 100 to 600 Ω/hole; Sputter platinum, 500℃, 1
The sheet resistance of the silicide when annealed for 0 minutes was 5 to 20 Ω/hole.
このように、低ソシート抵抗のシリサイド層が得られる
ことにより、ソース、ドレン領域の内部抵抗を減らすこ
とができる。また、ソース又はドレン領域を、長く引き
延ばすことにより、配線を減らせることもできる。In this way, by obtaining a silicide layer with low resistance, the internal resistance of the source and drain regions can be reduced. Furthermore, by extending the source or drain region, the number of wirings can be reduced.
例えば、薄膜トランジスタを、液晶平面ディスプレイの
ドライブ用素子に用いる場合も考える。For example, consider the case where thin film transistors are used as drive elements for liquid crystal flat displays.
この場合、ドレンには、透明電極を接続する必要がある
。透明電極は、一般にシート抵抗は、５０〜５００Ω／
口と高く、これを配線に用いると配線抵抗が高くなる。In this case, it is necessary to connect a transparent electrode to the drain. The transparent electrode generally has a sheet resistance of 50 to 500Ω/
If this is used for wiring, the wiring resistance will be high.
そのために、配線用に他の金属を用いる場合がある。そ
の場合、シリサイド層を設けた多結晶シリコン領域を配
線用に用いれば、配線用金属を別に形成する必要がなく
、プロセスは省略できる。Therefore, other metals may be used for wiring. In that case, if a polycrystalline silicon region provided with a silicide layer is used for wiring, there is no need to separately form metal for wiring, and the process can be omitted.
第１図は本発明の実施例の構造を示す断面図。
第２図は１本発明の素子を形成する工程を説明する断面
図である。
１・・・絶縁物基板、２・・・半導体薄膜、３・・・ゲ
ート絶縁膜、４・・・ゲート電極、５・・・金属膜、６
・・・金属シリサイド、７・・・金属シリサイド、８・
・・金属シリサイド、９・・・絶縁膜、１０・・・電極
。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a step of forming an element of the present invention. DESCRIPTION OF SYMBOLS 1... Insulator substrate, 2... Semiconductor thin film, 3... Gate insulating film, 4... Gate electrode, 5... Metal film, 6
...Metal silicide, 7...Metal silicide, 8.
...Metal silicide, 9...Insulating film, 10...Electrode.
Claims (1)
薄膜を形成し、上記半導体薄膜の表面にゲート絶縁膜を
介してゲート電極を設け、その両端にリース、ドレン領
域を設けるＭＯＳ形薄膜トランジスタにおいて、上記リ
ース、ドレン領域に不純物ドーピングをせず、金属シリ
サイド領域を設けることを特徴とした薄膜トランジスタ
。1. Form an island-shaped polycrystalline or amorphous semiconductor thin film on an insulating substrate, provide a gate electrode on the surface of the semiconductor thin film via a gate insulating film, and provide lease and drain regions at both ends of the gate electrode. A MOS type thin film transistor characterized in that the lease and drain regions are not doped with impurities and are provided with metal silicide regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6899185A JPS61229365A (en) | 1985-04-03 | 1985-04-03 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6899185A JPS61229365A (en) | 1985-04-03 | 1985-04-03 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61229365A true JPS61229365A (en) | 1986-10-13 |
Family
ID=13389635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6899185A Pending JPS61229365A (en) | 1985-04-03 | 1985-04-03 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61229365A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5008218A (en) * | 1988-09-20 | 1991-04-16 | Hitachi, Ltd. | Method for fabricating a thin film transistor using a silicide as an etch mask |
-
1985
- 1985-04-03 JP JP6899185A patent/JPS61229365A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5008218A (en) * | 1988-09-20 | 1991-04-16 | Hitachi, Ltd. | Method for fabricating a thin film transistor using a silicide as an etch mask |
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