JPS6122869B2 - - Google Patents
Info
- Publication number
- JPS6122869B2 JPS6122869B2 JP14173880A JP14173880A JPS6122869B2 JP S6122869 B2 JPS6122869 B2 JP S6122869B2 JP 14173880 A JP14173880 A JP 14173880A JP 14173880 A JP14173880 A JP 14173880A JP S6122869 B2 JPS6122869 B2 JP S6122869B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- mesa
- gate
- cathode
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 19
- 239000012212 insulator Substances 0.000 claims description 5
- 238000003466 welding Methods 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000003223 protective agent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42308—Gate electrodes for thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
本発明は、メサ型構造を有する半導体装置に係
り、特に周辺部に多数のメサ型構造を備えた半導
体装置に適用して好適な半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a mesa structure, and particularly to a semiconductor device suitable for application to a semiconductor device having a large number of mesa structures in its peripheral portion.
周辺部に多数のメサ型構造を有する半導体装置
として、たとえばゲート・ターンオフ・サイリス
タ（以下GTOと呼ぶ）のあることは周知であ
る。このGTOには、アノード電極およびカソー
ド電極を圧接方式で取出す方式がある。その一例
を第１図に示す。この図はGTOとして当業者に
おいて周知のもので説明するまでもない構造であ
るが、アノードとなるｐ形シリコン層１上に順次
ｎ形，ｐ形，n+形半導体層２，３，４を設け、
n+半導体層４を放射状に多数のメサ型構造カソ
ードを形成し、この各カソード上にアルミニユー
ム電極５を設け、この電極５上にその電極５と均
一に接触させるように同じ材質の薄い電極板６を
設ける。この電極板６およびアノード１上にそれ
ぞれ熱伝導率の良い電極板７，８，９，１０を強
く押し付けることによつて、電極４，１と電極板
７，８，９，１０との間の熱抵抗を十分に小さく
し、GTO素子１１で発生した熱を電極板６，
７，８，９，１０を介して積極的に放熱させて熱
容量の増大化を図つた構造になつている。 It is well known that a gate turn-off thyristor (hereinafter referred to as GTO), for example, is a semiconductor device having a large number of mesa-type structures in its peripheral portion. This GTO has a method in which the anode electrode and cathode electrode are removed by pressure contact. An example is shown in FIG. This figure shows a structure that is well known to those skilled in the art as a GTO and does not need to be explained, but n-type, p-type, and n +-type semiconductor layers 2, 3, and 4 are sequentially formed on a p- type silicon layer 1, which will serve as an anode. established,
A large number of mesa-shaped structure cathodes are formed radially on the n + semiconductor layer 4, and an aluminum electrode 5 is provided on each cathode, and a thin electrode plate made of the same material is placed on the electrode 5 so as to be in uniform contact with the electrode 5. 6 will be provided. By strongly pressing the electrode plates 7, 8, 9, and 10 having good thermal conductivity onto the electrode plate 6 and the anode 1, the distance between the electrodes 4, 1 and the electrode plates 7, 8, 9, and 10 is reduced. By making the thermal resistance sufficiently small, the heat generated in the GTO element 11 is transferred to the electrode plate 6,
7, 8, 9, and 10, the structure is such that heat is actively dissipated to increase the heat capacity.
ところが、圧接によつてメサ型構造カソード４
から電極を取出すとき、多数のカソード４に均一
に接触するために設けられた薄い電極板６が、メ
サ型構造の谷部に設けられるゲート電極１２の特
に比較的広い中央部のゲート電極と接触する場合
が多く、このためゲート電極１２とカソード電極
５間の短絡となり、GTOとしての機能を失つて
しまう場合が多い。したがつて通常、ゲート電極
１２を含むメサ型構造の谷部表面にCVD（ケミ
カル・ベイパード・ポジシヨン）SiO2膜やポリ
イミド樹脂などの絶縁物層１３を付けて絶縁を図
つている。 However, due to pressure welding, the mesa structure cathode 4
When taking out the electrode from the electrode, the thin electrode plate 6 provided to uniformly contact a large number of cathodes 4 comes into contact with the gate electrode in the relatively wide central part of the gate electrode 12 provided in the valley of the mesa structure. This often results in a short circuit between the gate electrode 12 and the cathode electrode 5, and the function as a GTO is often lost. Therefore, an insulation layer 13 such as a CVD (Chemical Vapor Position) SiO 2 film or polyimide resin is usually applied to the valley surface of the mesa structure including the gate electrode 12 for insulation.
しかしながら、上記SiO2膜やポリイミド樹脂
などの絶縁物質１３は、製造工程中のピンセツト
の先などの鋭角なもので傷が付き易い。特に、メ
サ型構造のカソード４が放射状に形成されている
ので、中央部は広い範囲カソード４のないゲート
領域となり、この部分で傷が付き易く、傷が付く
とゲート電極１２がむき出しになつて上記の様な
ゲート・カソード間が短絡してしまう。この現象
による不良が量産時に約50％も発生し、製品の製
造上において大きな問題であつた。 However, the insulating material 13 such as the SiO 2 film or polyimide resin is easily scratched by sharp objects such as the tips of tweezers during the manufacturing process. In particular, since the mesa-shaped cathode 4 is formed in a radial pattern, the central part becomes a wide gate area without the cathode 4, and this part is easily scratched, and if scratched, the gate electrode 12 will be exposed. A short circuit occurs between the gate and cathode as described above. This phenomenon caused approximately 50% of defects during mass production, and was a major problem in product manufacturing.
本発明は上記事情に鑑みてなされたもので、そ
の目的とするところは、メサ型構造谷部の底部に
相当する半導体層の領域が比較的広い部分は電極
を設けず、上記半導体層上に絶縁体層を設けた構
造にすることにより、上記広い部分での短絡防止
を図つたメサ型構造を有する半導体装置を提供す
ることにある。 The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide no electrode in the relatively wide area of the semiconductor layer corresponding to the bottom of the mesa-type structure valley, and to It is an object of the present invention to provide a semiconductor device having a mesa-type structure that prevents short circuits in the wide area by providing a structure with an insulating layer.
すなわち本発明は、たとえば放射状に配列した
メサ型構造カソードを圧接するGTOに適用した
場合、カソードの比較的ない中央部のゲート領域
の広い部分にゲート電極を設けないで、この広い
部分のゲート層上に絶縁体層、たとえばSiO2の
絶縁体層を形成することにより、カソード・ゲー
ト間における短絡を防止するようにしたものであ
る。 That is, when the present invention is applied to, for example, a GTO in which cathodes with a mesa-type structure arranged radially are pressed into contact, the gate electrode is not provided in a large part of the central gate region where there is relatively no cathode, and the gate layer in this wide part is By forming an insulating layer, for example, an insulating layer of SiO 2 on top, short circuits between the cathode and the gate are prevented.
以下、本発明の一実施例について第２図を参照
して説明する。なおこの実施例は、たとえば圧接
構造を有するメサ型GTOに適用した場合であ
る。 An embodiment of the present invention will be described below with reference to FIG. Note that this embodiment is applied to, for example, a mesa-type GTO having a press-contact structure.
まず、pnpn構造のシリコンウエハを使用す
る。すなわち、ｐ形拡散層をアノード２１として
用いる。このアノード２１のｐ形拡散層にｎ形拡
散層を形成してベース２２を構成する。このベー
ス２２のｎ形拡散層にｐ形拡散層を形成してゲー
ト２３を構成する。このゲート２３のｐ形拡散層
上にn+形拡散層を設けてカソード２４を構成す
る。このカソード２４は、第３図に示すように放
射状に形成されるようにマスタを用いてメサエツ
チングを行う。このメサエツチングしたウエハを
熱処理してメサ表面に酸化膜、すなわちSiO2膜
２５を形成する。次に、メサ型構造の頂部に相当
するカソード電極を形成する部分、およびメサ型
構造谷部の底部に相当するゲート電極を形成する
部分のSiO2膜２５を選択的にエツチングする。
このとき、ゲート領域２３の中央部２６における
SiO2膜２５は除去せずに残す。 First, a silicon wafer with a pnpn structure is used. That is, the p-type diffusion layer is used as the anode 21. An n-type diffusion layer is formed on the p-type diffusion layer of the anode 21 to constitute the base 22. A p-type diffusion layer is formed on the n-type diffusion layer of the base 22 to constitute the gate 23. An n + type diffusion layer is provided on the p type diffusion layer of this gate 23 to constitute a cathode 24 . This cathode 24 is formed by mesa etching using a master so that it is formed radially as shown in FIG. The mesa-etched wafer is heat-treated to form an oxide film, that is, a SiO 2 film 25, on the mesa surface. Next, the SiO 2 film 25 is selectively etched in a portion corresponding to the top of the mesa structure where the cathode electrode will be formed and a portion corresponding to the bottom of the mesa structure valley where the gate electrode will be formed.
At this time, in the central part 26 of the gate region 23
The SiO 2 film 25 is left without being removed.
次に、アノード２１のアノード電極を形成す
る。これは周知の技術であり、第１図に示すよう
に（第１図ではアノード１）ウエーハを補償板と
なるように、たとえばモリブデン（Mo）をアル
ミニウム（Al）、シリコン（Si）で合金化したモ
リブデン板をアノード電極９として設ける。次
に、反対側のカソード２４を表面にゲート電極お
よびカソード電極の電極材料層、たとえばアルミ
ニウム層を蒸着し、この材料層を選択的にエツチ
ングしてゲート電極２７およびカソード電極２８
を形成する。このとき、ゲート電極２７の薄いゲ
ート領域の中央部の比較的広い領域のゲート電極
は形成せず、Al蒸着層は選択エツチングにより
取り除かれる。このようにしてカソード電極２８
およびゲート電極２７を形成した後、CVD SiO2
膜やポリイミド樹脂からなる絶縁体層２９を形成
し、カソード電極２８上の絶縁体層２９を選択的
にエツチングを行う。このように形成したウエハ
により従来の方法で半導体素子、すなわちGTO
素子で発生した熱を放散させるように電極板７，
８，１０を圧接しGTO素子を構成する。この
GTO素子の周縁は形状を整えられて表面保護剤
１４が塗られる。 Next, the anode electrode of the anode 21 is formed. This is a well-known technique, and as shown in Figure 1 (anode 1 in Figure 1), a wafer is alloyed with, for example, molybdenum (Mo) with aluminum (Al) and silicon (Si) to serve as a compensation plate. The obtained molybdenum plate is provided as an anode electrode 9. Next, an electrode material layer for the gate electrode and the cathode electrode, for example, an aluminum layer, is deposited on the surface of the cathode 24 on the opposite side, and this material layer is selectively etched to form the gate electrode 27 and the cathode electrode 28.
form. At this time, a relatively wide gate electrode in the center of the thin gate region of the gate electrode 27 is not formed, and the Al deposited layer is removed by selective etching. In this way, the cathode electrode 28
After forming the gate electrode 27, CVD SiO 2
An insulator layer 29 made of a film or polyimide resin is formed, and the insulator layer 29 on the cathode electrode 28 is selectively etched. Using the wafer thus formed, semiconductor devices, namely GTOs, can be fabricated using conventional methods.
Electrode plate 7, so as to dissipate the heat generated in the element.
8 and 10 are pressed together to form a GTO element. this
The periphery of the GTO element is shaped and coated with a surface protective agent 14.
このようなGTO素子は、多数の電極に均一に
接触させるように薄い電極板６を用いても、比較
的ゲート領域の広い部分にはゲート電極を形成せ
ず、絶縁体層のみであるので、従来の広いゲート
領域でのゲート・カソード間の短絡不良を除去で
きる。さらに、広いゲート領域での短絡不良を回
避可能な構造にしたため、作業がやり易くなるな
どの作用効果が得られる。 In such a GTO element, even if a thin electrode plate 6 is used to uniformly contact a large number of electrodes, the gate electrode is not formed in a relatively wide part of the gate region, and only an insulator layer is formed. It is possible to eliminate short-circuit defects between the gate and cathode that occur in the conventional wide gate area. Furthermore, since the structure is designed to avoid short-circuit defects in a wide gate region, it is possible to obtain effects such as easier work.
なお上記実施例では、補償板９としてモリブデ
ン（Mo）を用いた場合について説明したが、タ
ングステンを用いてもよい。さらに上記実施例で
は、GTOに適用した場合について説明したが、
多数のメサ型構造を有し、このメサ型構造が部分
的に少ない領域を有する半導体装置であれば適用
でき、上記実施例と同様な作用効果が得られる。 In the above embodiment, the case where molybdenum (Mo) is used as the compensating plate 9 has been described, but tungsten may also be used. Furthermore, in the above embodiment, the case where it is applied to GTO was explained, but
The present invention can be applied to any semiconductor device that has a large number of mesa-type structures and in which the mesa-type structure has a partially small area, and the same effects as those of the above embodiments can be obtained.
以上詳述したように本発明によれば、メサ型構
造谷部の底部に相当する半導体層の領域が比較的
広い部分は電極を設けず、上記半導体層上に絶縁
体層を設けた構造にすることにより、上記広い部
分での短絡防止を図り、常に所定の機能を発揮し
得るメサ型構造を有する半導体装置を提供でき
る。 As described in detail above, according to the present invention, electrodes are not provided in the relatively wide area of the semiconductor layer corresponding to the bottom of the valley of the mesa-type structure, and an insulator layer is provided on the semiconductor layer. By doing so, it is possible to provide a semiconductor device having a mesa-type structure that can prevent short circuits in the wide area and always exhibit a predetermined function.
第１図は従来のGTO素子の構造説明図、第２
図は本発明半導体装置の一実施例を説明するため
の断面図、第３図は第２図のゲート電極およびカ
ソード電極の配列状態を説明するための平面図で
ある。
２１……アノード、２２……ベース、２３……
ゲート、２４……カソード、２７……ゲート電
極、２８……カソード電極、２５……SiO2膜、
２９……CVDSiO2膜・ポリイミド樹脂。
Figure 1 is an explanatory diagram of the structure of a conventional GTO element, Figure 2
The figure is a sectional view for explaining one embodiment of the semiconductor device of the present invention, and FIG. 3 is a plan view for explaining the arrangement of the gate electrode and cathode electrode in FIG. 2. 21...Anode, 22...Base, 23...
Gate, 24... cathode, 27... gate electrode, 28... cathode electrode, 25... SiO 2 film,
29...CVDSiO 2 film/polyimide resin.
Claims (1)
出す半導体装置において、前記メサ型構造谷部の
底部に相当する半導体層の領域が比較的広い部分
は電極を設けず、前記半導体層上に絶縁体層を設
けたことを特徴とするメサ型構造を有する半導体
装置。 ２ 複数のメサ型構造はゲート・ターンオフ・サ
イリスタのカソードを放射状に形成したものであ
り、中央部のゲート電極は形成しないものである
特許請求の範囲第１項記載の半導体装置。[Claims] 1. In a semiconductor device having a plurality of mesa structures and from which electrodes are taken out by pressure welding, no electrodes are provided in a relatively wide area of the semiconductor layer corresponding to the bottom of the valley of the mesa structure, A semiconductor device having a mesa structure, characterized in that an insulator layer is provided on the semiconductor layer. 2. The semiconductor device according to claim 1, wherein the plurality of mesa-type structures are formed by forming cathodes of gate turn-off thyristors radially, and a gate electrode in the center is not formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14173880A JPS5766667A (en) | 1980-10-09 | 1980-10-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14173880A JPS5766667A (en) | 1980-10-09 | 1980-10-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5766667A JPS5766667A (en) | 1982-04-22 |
| JPS6122869B2 true JPS6122869B2 (en) | 1986-06-03 |
Family
ID=15299049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14173880A Granted JPS5766667A (en) | 1980-10-09 | 1980-10-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5766667A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60132366A (en) * | 1983-12-21 | 1985-07-15 | Toshiba Corp | Semiconductor device |
-
1980
- 1980-10-09 JP JP14173880A patent/JPS5766667A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5766667A (en) | 1982-04-22 |
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