JP2000058814A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain reliability in environment where a temperature change is large and to improve the cutoff capacity. SOLUTION: In the semiconductor element of a surface gate SI thyristor, more than two unit elements 66 are installed in parallel and slit-like segments 11 are formed. A plurality of segments 11 are radially arranged in a semiconductor element 10. The width t1 of a circumferential direction in the semiconductor element 10 of the segment 11 is set to be 50 μm-500 μm. The respective unit elements 66 constituting the segment are made in slit forms, and the length t2 of a long side in the unit element 66 is 50 times as large as the length of a short side in the unit element. An interlayer insulating film 65 is formed between a gate electrode 63 and a cathode electrode 64 in the segment. A p-- type diffusion layer is formed by ion implantation so that it covers respective n-type emitter layers 47 and a normally-off semiconductor element is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a large capacity press contact type surface gate SI thyristor (normally off type).

[0002]

2. Description of the Related Art A generally known large-capacity pressure contact type semiconductor element has a large element area and is constituted by electrically connecting a plurality of unit elements in parallel. If at least one defective unit element exists among the unit elements, the defective unit element affects the characteristics of the entire element, resulting in defective characteristics of the entire element. Therefore, it is necessary to separate the defective unit element from the circuit.

In addition, since a large-capacity pressure-contact type semiconductor element needs to efficiently (effectively) remove heat generated during operation, most of both end faces of the element are electrodes, and the surface of the electrode is , A metal block is provided so as to be in contact with all of them, and the metal block is pressed from both end surface directions of the element and covered with a semiconductor case.

FIG. 4A is a schematic plan view for explaining an electrode structure in an amplification gate type thyristor (pellet, cathode side). In FIG. 4A, reference numeral 41 denotes a pellet-shaped semiconductor element (amplifying gate thyristor). A cathode electrode 42 having a desired shape is provided on one end surface of the semiconductor element 41, that is, on the cathode surface side.
Are provided radially. Each of these cathode electrodes 4
2, a gate electrode 43 is provided between each of the gate electrodes 43. Each of the gate electrodes 43 is provided at a central portion on the cathode surface side of the semiconductor element 41 (electric extraction portion: hereinafter, referred to as a central gate electrode). 44. The detailed description on the anode side of the semiconductor element 41 is omitted.

FIG. 4B is a partial cross-sectional structure diagram (cathode side: using a metal block) of the semiconductor device shown in FIG. 4A along the line aa. 4A are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 4B, reference numeral 45
Represents a semiconductor substrate 45 made of a relatively low-concentration n-type semiconductor (hereinafter, referred to as an n ^- type semiconductor substrate) 45,
A gate layer (hereinafter, referred to as a p-type gate layer) 46 made of a p-type semiconductor is formed on one end surface side (hereinafter, referred to as an upper surface side) of the n ⁻ type semiconductor substrate 45.

On the upper surface side of the p-type gate layer 46, a plurality of emitter layers (hereinafter, referred to as n-type emitter layers; n-type cathode layers) 47 made of an n-type semiconductor are formed at predetermined intervals. Is done. Reference numeral 48 is a metal block
(Cathode electrode: molybdenum disk), and its metal block 48 is connected to each cathode electrode 42 via an auxiliary metal plate 49. Reference numeral 41a
Reference numeral 43a denotes an auxiliary thyristor unit, and reference numeral 43a denotes a gate electrode of the auxiliary thyristor unit 41a;
Reference numeral 7a denotes a diffusion layer (hereinafter, referred to as an n-type diffusion layer) made of an n-type semiconductor in the auxiliary thyristor section 41a. Further, the auxiliary metal plate 49 is provided with the gate electrode 43.
(And 43a) are removed (gate pattern).

FIG. 5 is a schematic plan view showing an example of a pellet pattern in a GTO thyristor (pellet shape). In FIG. 5, reference numeral 51 denotes a semiconductor element (GTO thyristor), and reference numeral 52 denotes a slit-shaped cathode electrode. The cathode electrode 52 is provided for each of a plurality of unit elements formed radially with respect to the semiconductor element 51.

In the large-capacity thyristor as shown in FIGS. 4A, 4B and 5, the respective cathode electrodes and the respective gate electrodes are provided at predetermined intervals.
When a unit element (one or more) configured in a large-capacity thyristor becomes defective, the electrode (cathode electrode) of the defective unit element is removed, and the part from which the electrode has been removed and other good parts are removed. Provide a step (details will be described later with reference to FIG. 6) between the electrode and the unit element of
The defective unit element can be prevented from contacting the metal block. As a result, the defective unit element can be separated from the circuit.

However, since a semiconductor element such as an SI thyristor utilizes an electrostatic induction effect, the distance between each unit element is several μm to several tens μm, and the electrode of a defective unit element among the unit elements is It is difficult to remove only. In the case of a buried-gate type SI thyristor, a plurality of unit elements (slits) are juxtaposed (bundled) and a plurality of segments (slits) are used.

A cathode electrode is provided on each of the segments. When a segment including a defective unit element exists in each segment, the defective unit element can be separated from the circuit by removing the cathode electrode of the segment. In the case of a large capacity pressure contact type surface gate SI thyristor, similarly to the buried gate type SI thyristor, when using a plurality of segments each having a plurality of unit elements arranged in parallel, the surface of the segment is A cathode electrode is provided.

FIG. 6 is a partial sectional structural view of the segment (cathode side). The same components as those shown in FIGS. 4A and 4B are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 6, a plurality of n-type emitter layers 47 are formed at predetermined intervals on the upper surface side of n ⁻ -type semiconductor substrate 45. p-type gate layer 46
Is the upper surface of the n ⁻ type semiconductor substrate 45,
It is formed at a predetermined distance from the mold emitter layer 47.

Reference numeral 61 denotes a diffusion layer made of a p-type semiconductor having a relatively low concentration (hereinafter referred to as a p ^- type diffusion layer). The p-type gate layer 46 and each of the n-type emitter layers 47 are provided.
Is formed so as to cover each of the n-type emitter layers 47. Reference numeral 62 denotes an oxide film (for example, a silicon oxide film) formed in a desired shape (a pattern in which a contact hole having a desired shape is formed). Gate electrodes 63 formed in a desired shape are provided in portions of the oxide film 62 where the p-type gate layer 46 is located. Reference numeral 64 denotes a cathode electrode, and an interlayer insulating film 65 is interposed between the cathode electrode 64 and each of the gate electrodes 63. Note that reference numeral 66
Indicates a unit element.

[0013]

In the large-capacity thyristor configured as described above, when high-frequency operation or intermittent energization or the like is performed, each component (cathode) in the semiconductor case is increased as the element temperature rises and falls. (Electrodes, etc.)
Expands and contracts. Since the respective components have different coefficients of thermal expansion, stress is generated at the contact surface between the metal block and the segment. Surface gate S having a structure in which a plurality of segments composed of a plurality of unit elements are pressed and pressed.
In the case of a semiconductor device such as an I-thyristor, a portion located directly below a metal electrode (cathode electrode) used to cover the surface of each segment has a fine structure, and therefore, there is a problem that the fine structure portion is easily broken. is there.

FIG. 7 is a partial sectional structural view of a pellet-shaped surface gate SI thyristor (cathode side). Note that the same components as those shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 7, each component in the surface gate SI thyristor is radiated from the center of the element (from the center of the element to the outer periphery of the element; (In the direction of the arrow), the stepped portion 71 of each component formed in a direction perpendicular to the radiation direction of the element is a stepped portion of each component formed in a direction parallel to the radiation direction of the element. Stress concentration is more likely to occur as compared with the part (not shown).

In a semiconductor device such as an SI thyristor, since a p-type gate layer and an n-type emitter layer are close to each other,
If the interlayer insulating film is destroyed (or deformed) due to stress concentration occurring near the end of the contact hole for the n-type emitter layer, the p-type gate layer and the n-type emitter layer may come into contact and short-circuit. There is.

The present invention has been made on the basis of the above-mentioned problems, and has a semiconductor element in which the shape of a segment comprising a plurality of unit elements and the position of the segment arranged with respect to the semiconductor element are improved. To provide.

[0017]

According to a first aspect of the present invention, a buffer layer made of an n-type semiconductor is provided on one main surface side of a relatively low-concentration n-type semiconductor substrate. To form an anode layer made of a p-type semiconductor,
On the other main surface side of the n-type semiconductor substrate, a plurality of emitter layers made of an n-type semiconductor are formed at predetermined intervals, and the emitter layers are made of a p-type semiconductor at a predetermined interval from the emitter layers. Forming a gate layer, an anode electrode on the anode layer, a cathode electrode on the emitter layer, a gate electrode on the gate layer, and a large-capacity pressure-contact type semiconductor device comprising a plurality of unit elements; A slit-shaped segment is formed by arranging two or more unit elements in parallel, and a plurality of the segments are arranged radially with respect to the semiconductor element.

In a second aspect based on the first aspect, the circumferential width of the semiconductor element in the segment is 50%.
It is characterized in that it is not less than μm and not more than 500 μm.

According to a third aspect of the present invention, in the first or second aspect, each unit element constituting the segment has a slit shape, and the length of the long side of each unit element is equal to the length of the short side of each unit element. It is characterized in that it is 50 times or more of the length.

A fourth aspect of the present invention is the first, second, or third aspect.
In the invention, an interlayer insulating film is formed between the gate electrode and the cathode electrode in the segment.

In a fifth aspect based on the first, second, third or fourth aspect, a relatively low level is provided between the gate layer and each emitter layer in the segment so as to cover each emitter layer. A diffusion layer made of a p-type semiconductor with a high concentration is formed by ion implantation to form a normally-off type surface gate SI thyristor.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. The surface gate SI thyristor according to the embodiment of the present invention is shown in FIG. 2 (details will be described later).
It has been formed through the manufacturing process shown in FIG.

FIG. 1A is a plan view of a segment of the surface gate SI thyristor according to the first embodiment of the present invention, and FIG. 1B is an enlarged view near the end of the segment shown in FIG. 1A. is there. Note that the same components as those shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. 1A and 1B, reference numeral 11 denotes a segment (slit shape), and the segment 11 has two or more unit elements 66 (in FIG. 1A and FIG.
).

The width of the segment 11 (segment 11
(The distance of the short side t ₁ ; width in the element circumferential direction) is such that when the unit element 66 in the segment 11 is defective, the cathode electrode of the segment 11 including the defective unit element 66 can be removed with a needle or the like. (50 μm or more).

When there is a segment including a defective unit element in the surface gate SI thyristor due to the segment as shown in FIGS. 1A and 1B, the cathode electrode in the segment is removed and the defective unit element is easily separated from the circuit. It becomes possible.

The unit elements 66 formed in the segments 11 are arranged side by side so as to be parallel to the radial direction of the semiconductor element (surface gate SI thyristor; pellet) 10. As shown in the plan view of 1C, each segment 11 is formed so as to be radially arranged with respect to the semiconductor element 10. The length of a step portion formed directly below the metal electrode (cathode electrode) in the segment 11 arranged as shown in FIG. 1C and formed in the radial direction of the semiconductor element 10 (the radial length of the unit element: Long side t ₂ )
Is 50 times or more the length of the step formed in the element circumferential direction (the length of the unit element in the circumferential direction: short side t ₁ ).

As described above, in order to form a normally-off type surface-gate SI thyristor capable of easily separating the segment from the circuit by removing the cathode electrode in the segment including the defective unit element, FIG.
(The details will be described later).

FIG. 2 shows a manufacturing process diagram of the surface gate SI thyristor. Note that the same components as those shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 2, step S1 shows an anode layer forming step, in which a p-type anode layer 21 is formed on the anode side of a disk-shaped n ⁻ type semiconductor substrate 45. Reference numeral 22 denotes a buffer layer made of an n-type semiconductor (hereinafter, referred to as an n-type buffer layer).

Step S2 is a step of forming a p ^- type diffusion layer, in which the silicon oxide film 23a formed into a desired pattern is used to form a central portion of the n ^- type semiconductor substrate 45 with respect to the cathode side. A p ^- type diffusion layer 61 is formed.
Thereafter, in the p-type gate layer formation step of step S3, a silicon oxide film 23b that is formed into a desired pattern, the n ^- cathode side in a middle portion of the type semiconductor substrate 45 (p
^A p-type gate layer 46 (including a p-type diffusion layer) and a field limiting ring (hereinafter referred to as a p-type guard ring layer) 24 made of a p-type semiconductor on the cathode side at the end of the n ⁻ -type semiconductor substrate 45. Each is formed.

Step S4 is a step of forming an n-type emitter layer. The silicon formed in a desired pattern is separated from the p ^- type diffusion layer 61 at a predetermined distance from the p-type gate layer 46 on the cathode side. The n-type emitter layer 47 is formed using the oxide film 23c. Step S5 is a step of forming a gate electrode, in which a gate electrode 63 is provided on the p-type gate layer 46 using the silicon oxide film 23d having a desired pattern. Thereafter, in an interlayer insulating film forming step shown in step S6, an interlayer insulating film 65 is provided so as to cover the gate electrode 63.

Step S7 shows a cathode electrode forming step, in which each n in the silicon oxide film 23d is formed.
Contact holes are formed in advance at portions where the mold emitter layer 47 is located, and a cathode electrode 64 is formed so as to fill the contact holes and cover the interlayer insulating film 65.

As described above, according to the first embodiment of the present invention, only the end of the unit element is located where the stress generated by the operation of the semiconductor element is concentrated, and the probability that the unit element is broken is Can be reduced.

Next, a second embodiment of the present invention will be described. FIG. 3 is a plan view of a surface-gate SI thyristor (pellet) according to the second embodiment of the present invention. In FIG. 3, reference numeral 31 denotes a segment, and the segment 11 shown in FIG.
2 (three in FIG. 2) and are arranged radially with respect to the semiconductor element 30. The width of the segment 31
(Circumferential width) is 500 μm or less in order to reduce the gate resistance in the segment 31.

The segments 31 are smaller than the segments 11, and the segments 31 are formed so as to be arranged uniformly (at regular intervals) with respect to the semiconductor element 30. Therefore, the area utilization ratio is improved as compared with the semiconductor device 10 shown in FIG. 1C.

As described above, according to the surface gate SI thyristor of the second embodiment of the present invention, the resistance of the p-type gate layer in each segment is larger than that of the surface gate SI thyristor of the first embodiment. Can be reduced. Therefore, at the time of turn-off,
It is possible to increase the allowable value of di / dt of the current commutating from the cathode region to the gate region in the segment, and to increase the blocking resistance of the semiconductor element.

[0036]

As described above, according to the present invention, it is possible to easily remove a cathode electrode in a segment including a defective unit element, and to easily disconnect the defective unit element from a circuit. Become. In addition, concentration of stress generated by expansion and contraction due to operation of the semiconductor element can be prevented.

Therefore, it is possible to reduce defects of the semiconductor element due to an operation accompanied by a temperature change such as a high-frequency operation of the element, and to maintain high reliability even in an environment where the temperature change is large. In addition, the breaking tolerance of the semiconductor element can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a segment and a layout diagram of the segment in a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a normally-off type surface gate SI thyristor according to an embodiment of the present invention.

FIG. 3 is a layout diagram of segments according to a second embodiment of the present invention.

FIG. 4 is a plan view and a partial cross-sectional structural view (aa) of a generally known amplification gate thyristor.

FIG. 5 is a plan view of a generally known GTO thyristor.

FIG. 6 is a partial cross-sectional structural view of a generally known surface gate SI thyristor.

FIG. 7 is a partial cross-sectional structural view during operation of a generally known surface gate SI thyristor.

[Explanation of symbols]

10, 30, 41 semiconductor element 11, 31 segment 21 p-type anode layer 22 n-type buffer layer 23a to 23d oxide film 24 p-type guard ring layer 45 n ^- type semiconductor substrate 46 p-type gate Layer 47 n-type emitter layer 61 p ^- type diffusion layer 63 gate electrode 64 cathode electrode 65 interlayer insulating film 66 unit element

Claims (5)

[Claims] An anode layer made of a p-type semiconductor is formed on one main surface side of a relatively low-concentration n-type semiconductor substrate with a buffer layer made of an n-type semiconductor interposed therebetween. On the other main surface side, a plurality of emitter layers made of an n-type semiconductor are formed at predetermined intervals, and a gate layer made of a p-type semiconductor is formed at a predetermined interval from these emitter layers. An anode electrode on the anode layer, a cathode electrode on the emitter layer, and a gate electrode on the gate layer, and a large-capacity pressure-contact type semiconductor device comprising a plurality of unit devices; A semiconductor element, wherein a plurality of segments are arranged in parallel to form a slit-shaped segment, and a plurality of the segments are arranged radially with respect to the semiconductor element. 2. The semiconductor device according to claim 1, wherein a circumferential width of the semiconductor device in the segment is 50 μm or more and 500 μm or less. 3. The device according to claim 1, wherein each of the unit elements constituting the segment has a slit shape, and the length of the long side of each unit element is at least 50 times the length of the short side of each unit element. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein an interlayer insulating film is formed between the gate electrode and the cathode electrode in the segment. 5. The semiconductor device according to claim 1, wherein a relatively low concentration of p is provided between the gate layer and each emitter layer in the segment so as to cover each emitter layer.
A semiconductor device comprising a normally-off type surface gate SI thyristor in which a diffusion layer made of a type semiconductor is formed by ion implantation.