JPS6122864B2 - - Google Patents
Info
- Publication number
- JPS6122864B2 JPS6122864B2 JP55004361A JP436180A JPS6122864B2 JP S6122864 B2 JPS6122864 B2 JP S6122864B2 JP 55004361 A JP55004361 A JP 55004361A JP 436180 A JP436180 A JP 436180A JP S6122864 B2 JPS6122864 B2 JP S6122864B2
- Authority
- JP
- Japan
- Prior art keywords
- base
- integrated circuit
- gold
- welding
- welded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000003466 welding Methods 0.000 claims description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 description 12
- 238000007747 plating Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000002952 polymeric resin Substances 0.000 description 4
- 229920003002 synthetic resin Polymers 0.000 description 4
- 238000005219 brazing Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Casings For Electric Apparatus (AREA)
- Optical Couplings Of Light Guides (AREA)
Description
【発明の詳細な説明】
この発明は、超高信頼性を要求される半導体あ
るいは、集積回路のハーメチツク・シール用パツ
ケージの改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in hermetically sealed packages for semiconductors or integrated circuits that require ultra-high reliability.
従来、集積回路に用いられる気密パツケージは
高分子樹脂(一般にはエポキシ系樹脂)でモール
ドするプラスチツク・パツケージあるいは金属製
ハーメチツク用パツケージのヘツダとキヤツプを
プロジエクシヨン溶接あるいはシーム溶接をして
いた。この高分子樹脂材料を使用する場合の工事
は比較的簡単で安価であるが、高分子樹脂材料は
湿気あるいは水分を透過及び吸収する性質がある
ので超高信頼性を要求する装置に使用できない。
また、プロダクシヨン溶接によるハーメチツクシ
ールは工事が簡単で安価である被溶接物であるヘ
ツダとキヤツプの接触部分に瞬間的な大電流を流
すため、誘導電流により半導体あるいは集積回路
が悪影響を受けやすい。さらに溶接面積が大きい
場合、溶接が不可能であるか、溶接したとしても
ヘツダとキヤツプの接触面積にハラツキが生じや
すく溶接粒が発生しやすい。この溶接がパツケー
ジ内に封入されると半導体あるいは集積回路装置
の信頼性を劣化しやすい。このためプロジエクシ
ヨン溶接の実用寸法は、直径15mm以下のパツケー
ジに限られる。一方、シーム溶接機によるハーメ
チツク・シールは二つの相対する電極を同時に均
一に接触させる必要があるため、プロジエクシヨ
ン溶接機を使用する場合に比べて大型のパツケー
ジの溶接は可能であるが、円形又は矩形の簡単な
形状で円形の場合直径30mm以下、矩形の場合一辺
が30mm以下の比較的小型のパツケージにしか使用
することが出来ない欠点があつた。 Conventionally, airtight packages used for integrated circuits have been made of plastic packages molded with polymeric resin (generally epoxy resin) or metal hermetic packages, and the headers and caps are welded by projection welding or seam welding. Construction work when using this polymeric resin material is relatively simple and inexpensive, but since the polymeric resin material has the property of permeating and absorbing moisture, it cannot be used in devices that require ultra-high reliability.
In addition, hermetic seals by production welding are easy and inexpensive to construct, and because a large instantaneous current flows through the contact area between the header and the cap, which are objects to be welded, semiconductors or integrated circuits may be adversely affected by the induced current. Cheap. Furthermore, if the welding area is large, welding is impossible, or even if welding is done, the contact area between the header and the cap tends to be uneven and weld grains are likely to be generated. If this welding is encapsulated in a package, the reliability of the semiconductor or integrated circuit device is likely to deteriorate. For this reason, the practical size of projection welding is limited to packages with a diameter of 15 mm or less. On the other hand, hermetic sealing using a seam welding machine requires two opposing electrodes to be in uniform contact at the same time, so it is possible to weld larger packages compared to when using a projection welding machine; Another disadvantage is that it can only be used in relatively small package cages with a simple rectangular shape, with a diameter of 30 mm or less in the case of a circle, and a side of 30 mm or less in the case of a rectangle.
この発明の目的は、以上の考察に基づいて、比
較的安価でかつ大きさに制限されず、しかも円形
あるいは矩形の溶接形状だけでなくより複雑な形
状のパツケージでも溶接軌跡を制御することによ
り安易に溶接可能なレーザ溶接機を用いてハーメ
チツク・シール工事ができるようにした集積回路
用ハーメチツクシール・パツケージを提供するこ
とにある。 Based on the above considerations, it is an object of the present invention to provide a method that is relatively inexpensive, is not limited by size, and is easy to use by controlling the welding trajectory not only for circular or rectangular welding shapes but also for packages with more complex shapes. To provide a hermetic seal package for an integrated circuit in which hermetic sealing work can be performed using a laser welding machine capable of welding.
以下図面により本発明を詳細に説明する。 The present invention will be explained in detail below with reference to the drawings.
第1図は本発明の実施例のヘツダの斜視図、第
2図は第1図の拡大断面図、第3図は本発明の実
施例の部分破砕斜視図である。図中、1はベー
ス、2はリード3を封入するガラスである。ま
た、4はコバールなどの材料によりベース1をつ
くるべース母材、5はこの母材4上の下地鍍金
層、6は金鍍金属である。下地鍍金としては一般
に光択のないニツケル鍍金が用いられる。さら
に、7は集積回路基板、8はロウ材、9は金細
線、10はキヤン(容器ケース)を示す。また、
キヤン10はコバールなどの材料にニツケル鍍金
したものである。この場合、ベース1とキヤン1
0とを重ね合める部分およびベースの外周部11
が金鍍金されていないことに特徴がある。 FIG. 1 is a perspective view of a header according to an embodiment of the present invention, FIG. 2 is an enlarged sectional view of FIG. 1, and FIG. 3 is a partially exploded perspective view of an embodiment of the present invention. In the figure, 1 is a base, and 2 is a glass that encloses the leads 3. Further, 4 is a base material from which the base 1 is made of a material such as Kovar, 5 is a base plating layer on this base material 4, and 6 is a gold-plated metal. As the base plating, nickel plating, which has no optical selection, is generally used. Furthermore, 7 is an integrated circuit board, 8 is a brazing material, 9 is a thin gold wire, and 10 is a can (container case). Also,
Can 10 is made of nickel plated material such as Kovar. In this case, base 1 and can 1
0 and the outer periphery of the base 11
It is distinctive in that it is not plated with gold.
高信頼性半導体あるいは集積回路の場合、ダイ
ボンデイングに金系ロウ材(例えば、Au/Si,
Au/Ge,Au/Snなど)を用いるため、ヘツダ
ーの金鍍金6の部分でダイ・ボンデイングを行
う。又高信頼性半導体あるいは集積回路の表面導
体層は金で構成されているので、配線材として金
細線9を用いヘツダの金鍍金6の部分とリード3
との間をワイヤ・ボンデイングする。一方、ハー
メチツク・シールする場合、ヘツダの下地鍍金層
5とキヤン10の重ね合わせた部分を矢印12の
方向からレーザ溶接機を用いて溶接する。この際
ベース1とキヤン10との重ね合わせ部分を金鍍
金が施されていないので、レーザ光をほとんど反
射せずに、効率よく吸収し溶接が可能となる。 In the case of high-reliability semiconductors or integrated circuits, die bonding uses gold-based brazing materials (e.g. Au/Si,
(Au/Ge, Au/Sn, etc.), die bonding is performed on the gold plating 6 part of the header. In addition, since the surface conductor layer of a highly reliable semiconductor or integrated circuit is made of gold, a thin gold wire 9 is used as the wiring material to connect the gold plated portion 6 of the header and the lead 3.
Wire bonding between. On the other hand, in the case of hermetically sealing, the overlapping portion of the base plating layer 5 of the header and the can 10 is welded in the direction of arrow 12 using a laser welder. At this time, since the overlapping portion of the base 1 and the can 10 is not plated with gold, the laser beam is hardly reflected and is efficiently absorbed, making it possible to weld.
以上説明したように、レーザ溶接機を用いて部
分的に金鍍金を施してない金属から成るヘツダ1
とキヤン10を溶接するため、高分子樹脂材料を
用いた半導体あるいは集積回路装置のように湿気
あるいは水分を透過することがないので超高信頼
度用集積回路気密パツケージとなり、その上レー
ザ溶接機を効果的に用いることができるので数値
制御機構を加味することにより、複雑な形状でし
かも大きさにも制限されぬ気密パツケージを形成
できる。 As explained above, the header 1 made of metal that is not partially plated with gold is manufactured using a laser welding machine.
In order to weld the Can 10 with the Can 10, it does not allow moisture to pass through unlike semiconductors or integrated circuit devices using polymeric resin materials, making it an ultra-high reliability integrated circuit airtight package. Since it can be used effectively, by adding a numerical control mechanism, an airtight package with a complicated shape and size is not limited.
第1図は本発明の実施例のヘツダーの斜視図、
第2図は第1図ヘツダーの溶接部の断面拡大図、
第3図は本発明の実施例のヘツダを用いた集積回
路装置の部分破砕斜視図である。図において
1……ベース、2……ガラス、3……リード、
4……ベース母材、5……下地鍍金層、6……金
鍍金層、7……集積回路基板、8……ロウ材、9
……金細線、10……キヤン、11……外周部、
12……矢印。である。
FIG. 1 is a perspective view of a header according to an embodiment of the present invention;
Figure 2 is an enlarged cross-sectional view of the welded part of the header in Figure 1.
FIG. 3 is a partially exploded perspective view of an integrated circuit device using a header according to an embodiment of the present invention. In the diagram: 1...Base, 2...Glass, 3...Lead,
4... Base base material, 5... Base plating layer, 6... Gold plating layer, 7... Integrated circuit board, 8... Brazing material, 9
...Gold wire, 10...Kyan, 11...Outer periphery,
12...Arrow. It is.
Claims (1)
数のリード端子を有するベースと、このベースを
覆うキヤン部材とからなり、前記ベースの半導体
あるいは集積回路基板と溶接される個所を金鍍金
し、前記ベースの前記キヤン部材と溶接される個
所およびその近傍の外周部を非光択性鍍金し、前
記ベースと前記キヤン部材とをレーザ溶接にて溶
接したことを特徴とする集積回路用気密パツケー
ジ。1 Consisting of a base on which a semiconductor or integrated circuit board is mounted and has a predetermined number of lead terminals, and a can member that covers this base, the parts of the base to be welded to the semiconductor or integrated circuit board are plated with gold, and the base is An airtight package for an integrated circuit, characterized in that a portion to be welded to the can member and an outer circumferential portion thereof are non-photoselectively plated, and the base and the can member are welded by laser welding.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP436180A JPS56101761A (en) | 1980-01-18 | 1980-01-18 | Airtight package for integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP436180A JPS56101761A (en) | 1980-01-18 | 1980-01-18 | Airtight package for integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56101761A JPS56101761A (en) | 1981-08-14 |
JPS6122864B2 true JPS6122864B2 (en) | 1986-06-03 |
Family
ID=11582231
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP436180A Granted JPS56101761A (en) | 1980-01-18 | 1980-01-18 | Airtight package for integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56101761A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989003123A1 (en) * | 1987-09-25 | 1989-04-06 | Aegis, Inc. | Microcircuit package with corrosion resistant pins and methof of making |
JPH079953B2 (en) * | 1988-04-13 | 1995-02-01 | 株式会社東芝 | Method for manufacturing semiconductor device |
-
1980
- 1980-01-18 JP JP436180A patent/JPS56101761A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS56101761A (en) | 1981-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6080931A (en) | Semiconductor package | |
US5028987A (en) | High current hermetic package having a lead extending through the package lid and a packaged semiconductor chip | |
US6677674B2 (en) | Semiconductor package having two chips internally connected together with bump electrodes and both chips externally connected to a lead frame with bond wires | |
US6028356A (en) | Plastic-packaged semiconductor integrated circuit | |
US4877756A (en) | Method of packaging a semiconductor laser and photosensitive semiconductor device | |
US5105536A (en) | Method of packaging a semiconductor chip in a low inductance package | |
JPS6122864B2 (en) | ||
KR930017154A (en) | Semiconductor package | |
JPH03280453A (en) | Semiconductor device and manufacture thereof | |
JP2689621B2 (en) | Semiconductor device and manufacturing method thereof | |
JPS6222456B2 (en) | ||
JPH08139241A (en) | Lead frame and semiconductor integrated circuit device using it | |
JPH09172033A (en) | Semiconductor device and manufacture thereof | |
JPH0812896B2 (en) | Semiconductor device | |
JPH04155949A (en) | Resin-sealed semiconductor device | |
KR100214857B1 (en) | Multi-chip package | |
JPS638620B2 (en) | ||
JPS63122250A (en) | Semiconductor device | |
JP2512829B2 (en) | Semiconductor element | |
KR0167285B1 (en) | Blp package | |
JPH05251620A (en) | Semiconductor device | |
JPS5932156A (en) | Cap mounting structure for semiconductor device | |
JPS62120053A (en) | Manufacture of resin-sealed semiconductor device | |
JP2004096029A (en) | Manufacturing method of power semiconductor device | |
JPH03169057A (en) | Semiconductor device |