JPS6122654A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPS6122654A JPS6122654A JP59143003A JP14300384A JPS6122654A JP S6122654 A JPS6122654 A JP S6122654A JP 59143003 A JP59143003 A JP 59143003A JP 14300384 A JP14300384 A JP 14300384A JP S6122654 A JPS6122654 A JP S6122654A
- Authority
- JP
- Japan
- Prior art keywords
- package
- width
- cap
- semiconductor device
- metallized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、セラミック基体を用いた半導体装置用パッケ
ージに関する、
〔従来技術〕 −
セラミック基体を用いた半導体装置の従来のパッケージ
の構造について説明すると、第３図および第４図に図示
された形状のもので、先ずセラミック基板に半導体装置
部５．電極部４．封止部（メタライズパターン）２およ
び、これらと外部リード６との接続部すなわち電気的導
通をとるための引き回し配線部のパターンを、タングス
テンなどを用いてメタライズ印刷して、１枚のセラミッ
ク基板ができる。つぎに、これらのセラミック基板を３
〜４層積層し、焼成することにより、セラミック基体１
が形成される。このセラミック基体ｌに、外部リード６
、キャップ封止用金具３をＡｇ’−Ｃｕ合金などの鑞材
を用いて鑞付して、半導体用パッケージが成形され、ま
た必要によりＡｕなどのメッキが施される。[Detailed Description of the Invention] [Technical Field] The present invention relates to a package for a semiconductor device using a ceramic substrate. [Prior Art] - To explain the structure of a conventional package for a semiconductor device using a ceramic substrate, With the shape shown in FIG. 4 and FIG. Electrode part 4. The sealing part (metallized pattern) 2 and the connection part between these parts and the external lead 6, that is, the pattern of the routing wiring part for establishing electrical continuity, are printed with metallization using tungsten or the like, and one ceramic substrate is formed. can. Next, these ceramic substrates are
By laminating ~4 layers and firing, the ceramic base 1
is formed. An external lead 6 is attached to this ceramic base l.
A semiconductor package is formed by brazing the cap sealing fitting 3 with a brazing material such as Ag'-Cu alloy, and plating with Au or the like as necessary.
封止部におけるメタライズ部分のはみ出し幅ｄは、鑞材
でメニスカス（新月形）を形成するため、金具の厚みｈ
と同程度キャップ封止用金具３の幅よりも広くすること
が行なわれていた。The protruding width d of the metallized part in the sealing part is determined by the thickness h of the metal fitting because the solder material forms a meniscus (new moon shape).
The width of the metal fitting 3 for sealing the cap has been made to be approximately the same as that of the metal fitting 3 for sealing the cap.
このように形成されたパッケージを用いて、先ず半導体
素子載置部５に半導体素子を固定する。First, a semiconductor element is fixed to the semiconductor element mounting portion 5 using the package formed in this manner.
つぎに、この半導体素子上の電極部とパッケージの電極
部４とを金属細線によって接続すると、これによって、
半導体素子と、外部リード６との電気的導通がとられる
。つぎに金属キャップを抵抗溶接により封着して、半導
体装置が完成する。Next, when the electrode section on this semiconductor element and the electrode section 4 of the package are connected with a thin metal wire, this results in
Electrical continuity is established between the semiconductor element and the external leads 6. Next, a metal cap is sealed by resistance welding to complete the semiconductor device.
このようにして形成された従来のセラミック基体を用い
た半導体装置においては、金属キャップ到着の際の抵抗
溶接の際の発熱により、金属キャップが伸縮し、この伸
縮による張力が大きくなるとキャップ封着後、セラミッ
ク基体とキャップ封止用金具との間の鑞付部が剥離し、
気密性が維持できなくなる。また、たとえ封着直後は気
密性を維持していても、それ以後の取り扱いにおいて、
熱的ヒシテリシス、物理的衝撃などがかかるため剥離の
危険性を孕んでいる。このセラミック基体と、キャップ
封止用金具の鑞付は強度は、セラミック基体の焼成条件
や鑞付けの条件などに左右され、またキャップ封止用金
具にかかる張力は、キャップ封止の条件に左右される。In a semiconductor device using a conventional ceramic substrate formed in this way, the metal cap expands and contracts due to the heat generated during resistance welding when the metal cap arrives, and if the tension due to this expansion and contraction becomes large, after the cap is sealed, the metal cap expands and contracts. , the brazed part between the ceramic base and the cap sealing fitting peels off,
Airtightness cannot be maintained. In addition, even if airtightness is maintained immediately after sealing, during subsequent handling,
There is a risk of peeling due to thermal hysteresis and physical shock. The strength of brazing the ceramic base and the cap-sealing metal fitting depends on the firing conditions of the ceramic base and the brazing conditions, and the tension applied to the cap-sealing metal fitting depends on the cap-sealing conditions. be done.
従来のセラミック基体を用いた半導体装置では、この鑞
付は強度を確保するため、前記各工程において、製造条
件を厳密に管理しており、そのため管理工数の増大およ
び生産性の低下を来し、コストアップの要因となってい
る。In semiconductor devices using conventional ceramic substrates, manufacturing conditions are strictly controlled in each of the steps mentioned above to ensure brazing strength, which results in an increase in management man-hours and a decrease in productivity. This is a factor that increases costs.
また、製造条件の微妙な変化によって、鑞付けの強度が
低下する危険性を常に孕んでいる。Furthermore, there is always a risk that the strength of the brazing may decrease due to subtle changes in manufacturing conditions.
本発明の目的は、セラミック基体のメタライズ部分に、
キャップ封止用金具を鑞付してなる半導体装置用パッケ
ージにおいて、前記従来技術の欠点を除去し、鑞付部の
強度を改善するとともに、生産にあたってはコストアッ
プの要因を除去した、安価で信頼性の高いセラミック基
体を用いた半導体装置用パッケージを提供することにあ
る。The object of the present invention is to provide a metallized portion of a ceramic substrate with
In a semiconductor device package in which a cap sealing fitting is brazed, the disadvantages of the conventional technology are eliminated, the strength of the brazed part is improved, and the factors that increase production costs are eliminated, making it inexpensive and reliable. An object of the present invention is to provide a package for a semiconductor device using a ceramic substrate with high properties.
本発明は、セラミック基体のメタライズ部分に、キャッ
プ封止用金具を鑞材を用いて鑞付けしてなる半導体装置
用パッケージにおいそ、前記セラミック基体に形成され
た前記メタライズ部分の幅を、前記キャップ封止用金具
の幅よりも大きく形成し、該メタライズの幅のはみ出し
量を、該キャップ封止用金具の厚みの少なくとも２倍に
形成することによって構成される。The present invention provides a semiconductor device package in which a cap sealing fitting is brazed to a metallized portion of a ceramic base using a soldering material, and the width of the metallized portion formed on the ceramic base is adjusted to The metallization is formed to have a width larger than the width of the cap-sealing metal fitting, and the amount of protrusion of the width of the metallization is at least twice the thickness of the cap-sealing metal fitting.
つぎに本発明の実施例を図面によって説明する。第１図
および第２図は、本発明の実施例を示す図面で、セラミ
ック基体１１に対し、キャップ封止用金具１３を、鑞材
を用いて、鑞付するメタライズパターン１２のメニスカ
スの幅ｄを、従来方法に比較して拡げ、キャップ封止用
金具の高さｈの少なくとも２倍から、約７．１倍の範囲
、これを角度で表現すると、メタライズパターン１２の
メニスカスの幅ｄと、キャップ封止用金具の高さｈのな
す角をθとして、メニスカスの幅ｄの範囲をｊａｎ２Ｂ
’ ３４’からｔａｎ８’の範囲に設定したものである
。メタライズパターンの幅は広いほど、セラミック基体
とキャップ封止用金具の接合強度が増すが、キャップ封
止時の抵抗溶接用ローラー電極の角度、経済性を考慮し
た場合、上記ｔａｎθが０＝２６°３４′からθ＝８°
の範囲が最適である。Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are drawings showing an embodiment of the present invention, in which a meniscus width d of a metallized pattern 12 is soldered to a ceramic base 11 using a solder material. is expanded compared to the conventional method, and ranges from at least twice to about 7.1 times the height h of the cap sealing metal fitting, and when expressed in terms of angle, the width d of the meniscus of the metallized pattern 12, The angle formed by the height h of the cap sealing fitting is θ, and the range of the meniscus width d is jan2B
It is set in the range from '34' to tan8'. The wider the width of the metallized pattern, the greater the bonding strength between the ceramic substrate and the cap sealing metal fitting.However, when considering the angle of the roller electrode for resistance welding during cap sealing and economic efficiency, the above tanθ is 0 = 26°. θ=8° from 34′
The range of is optimal.
本発明により、従来の半導体パッケージに比較して、キ
ャップ封止用金具の鑞付強度が増し、パッケージおよび
半導体装置の製造条件における自由度を増大することが
でき、これにより管理工数の低減、生産性の向上が図ら
れること、鑞付強度の増加により気密性が向上し、信頼
性の高い半導体装置を提供することができること、およ
び、メタライズ幅を拡げたことにより、抵抗溶接の際の
放熱性が良くなり、電流効率が俄善されるとともに過熱
によるキャップ表面の変色が避けられるなど、キャップ
封着の作業性が向上し、これらによって安価で信頼性の
高い、セラミック基体を用いた半導体装置用パッケージ
を提供することができる。According to the present invention, the brazing strength of the cap sealing metal fittings is increased compared to conventional semiconductor packages, and the degree of freedom in manufacturing conditions for packages and semiconductor devices can be increased, thereby reducing management man-hours and production. The increased brazing strength improves airtightness, making it possible to provide highly reliable semiconductor devices. Also, by expanding the metallization width, heat dissipation during resistance welding is improved. This improves the current efficiency and avoids discoloration of the cap surface due to overheating, which improves the workability of cap sealing. package can be provided.
第１図は、本発明の半導体装置用パッケージの上面図、
第２図は、第１図のキャップ封止用金具とメタライズパ
ターンのはみ出し部の側面図、第３図は従来の方法にお
ける半導体装置用パッケージの上面図、第４図は第３図
の側面図である。
１．１１・・・セラミック基体
２．１２・・・メタライズパターン
３．１３・・・キャップ封止用金具
４．１４・・・電極
５．１５・・・素子載置部
６．１６・・・外部リード
９・・・キャップ封止用金具鑞付部
ｄ・・・メタライズパターンのはみ出し部ｈ・・・キャ
ップ封止用金具の厚み
θ・・・ｄとｈとのなす角FIG. 1 is a top view of a package for a semiconductor device of the present invention;
FIG. 2 is a side view of the cap sealing fitting and the protruding part of the metallized pattern in FIG. 1, FIG. 3 is a top view of a semiconductor device package in the conventional method, and FIG. 4 is a side view of FIG. 3. It is. 1.11... Ceramic base 2.12... Metallized pattern 3.13... Cap sealing fitting 4.14... Electrode 5.15... Element mounting portion 6.16... External lead 9...Cap sealing metal fitting brazing part d...Protruding part of metallized pattern h...Thickness θ of cap sealing metal fitting...Angle between d and h
Claims (1)
金具を鑞材を用いて鑞付してなる半導体装置用パッケー
ジにおいて、前記セラミック基体に形成された前記メタ
ライズ部分の幅を、前記キャップ封止用金具の幅よりも
大きく形成し、該メタライズの幅のはみ出し量を、該キ
ャップ封止用金具の厚みの少なくとも２倍に形成したこ
とを特徴とする半導体装置用パッケージ。 ２、前記メタライズ部分のはみ出し量と、前記キャップ
封止用金具の厚みとのなす正接角が８°乃至２６°３４
’の範囲であることを特徴とする特許請求の範囲第１項
記載の半導体装置用パッケージ。[Claims] 1. In a semiconductor device package in which a cap sealing fitting is brazed to a metallized portion of a ceramic base using a soldering material, the width of the metallized portion formed on the ceramic base is A package for a semiconductor device, characterized in that the width of the metallization is larger than the width of the cap sealing metal fitting, and the amount of protrusion of the width of the metallization is at least twice the thickness of the cap sealing metal fitting. 2. The tangent angle between the amount of protrusion of the metallized portion and the thickness of the cap sealing fitting is 8° to 26°34.
The package for a semiconductor device according to claim 1, wherein the package is within the range of '.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59143003A JPS6122654A (en) | 1984-07-10 | 1984-07-10 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59143003A JPS6122654A (en) | 1984-07-10 | 1984-07-10 | Package for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6122654A true JPS6122654A (en) | 1986-01-31 |
| JPH0351102B2 JPH0351102B2 (en) | 1991-08-05 |
Family
ID=15328686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59143003A Granted JPS6122654A (en) | 1984-07-10 | 1984-07-10 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6122654A (en) |
-
1984
- 1984-07-10 JP JP59143003A patent/JPS6122654A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0351102B2 (en) | 1991-08-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |