JPS6122632A - Surface processing of substrate - Google Patents
Surface processing of substrateInfo
- Publication number
- JPS6122632A JPS6122632A JP10370885A JP10370885A JPS6122632A JP S6122632 A JPS6122632 A JP S6122632A JP 10370885 A JP10370885 A JP 10370885A JP 10370885 A JP10370885 A JP 10370885A JP S6122632 A JPS6122632 A JP S6122632A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- semiconductor substrate
- flatten
- coated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000007789 gas Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000000992 sputter etching Methods 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 31
- 239000000463 material Substances 0.000 abstract description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 abstract description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052801 chlorine Inorganic materials 0.000 abstract description 3
- 239000000460 chlorine Substances 0.000 abstract description 3
- 229910052731 fluorine Inorganic materials 0.000 abstract description 3
- 239000011737 fluorine Substances 0.000 abstract description 3
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 abstract description 2
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052794 bromium Inorganic materials 0.000 abstract description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 150000002894 organic compounds Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 15
- 239000011247 coating layer Substances 0.000 description 10
- 229920001721 polyimide Polymers 0.000 description 6
- 239000009719 polyimide resin Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000001771 vacuum deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- -1 0t3F Chemical compound 0.000 description 1
- MIZLGWKEZAPEFJ-UHFFFAOYSA-N 1,1,2-trifluoroethene Chemical compound FC=C(F)F MIZLGWKEZAPEFJ-UHFFFAOYSA-N 0.000 description 1
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置を製造する過程で、半導体基板の表
面を平坦化する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for planarizing the surface of a semiconductor substrate during the process of manufacturing a semiconductor device.
一般に半導体基板を用いて半導体装置を製造する場合、
半導体基板表面に不純物拡散、絶縁層形成、ホトエツチ
ングによる表面加工等の処理を施す。こ几らの処理を経
る間に第１図（ａ）に示すように、半導体基板１工の表
面は非常に大きな凹凸もしくは段差（以下まとめて凹凸
という）を生じる。Generally, when manufacturing a semiconductor device using a semiconductor substrate,
Processes such as impurity diffusion, formation of an insulating layer, and surface processing by photoetching are performed on the surface of the semiconductor substrate. During these processes, as shown in FIG. 1(a), the surface of the semiconductor substrate has very large irregularities or steps (hereinafter collectively referred to as irregularities).
この半導体基板１１の上に真空蒸着法、化学蒸着法やス
パッタリング法などによって導体層もしくは絶縁層（以
下形成層と略す）１２形成とすると第１図（ｂ）におい
て、Ａ、Ｂ部として示す如く、凹凸の底の部分において
形成層１２が薄くなったり、甚だしい場合は切れたシす
ることが多く、該形成層１２の信頼性を著しく低下させ
る。従来は半導体基板１１上のこのような凹凸もしくは
段差を除去する有効な方法はなく、形成層１２を厚りシ
タシする等の方法で必要最低限の信頼性を確保している
のが実情である。When a conductive layer or an insulating layer (hereinafter referred to as a forming layer) 12 is formed on this semiconductor substrate 11 by a vacuum evaporation method, a chemical vapor deposition method, a sputtering method, etc., as shown as parts A and B in FIG. 1(b). The forming layer 12 often becomes thinner or, in severe cases, breaks at the bottom of the unevenness, which significantly reduces the reliability of the forming layer 12. Conventionally, there is no effective method for removing such unevenness or steps on the semiconductor substrate 11, and the reality is that the minimum necessary reliability is secured by methods such as increasing the thickness of the forming layer 12. .
本発明の目的は上Ｗｅ従来の問題を解決し、基板の表面
を容易かつ確実に平担化する方法を提供することである
。An object of the present invention is to solve the problems of the conventional method and provide a method for easily and reliably flattening the surface of a substrate.
これに対して本発明は以上述べたような半導体基板表面
の凹凸を除去もしくは著しく減少させて、この上に形成
する層の信頼性を向上させる方法を提供するものである
。第２図によって本発明の詳細な説明する。ます、第２
図（ａ）に示す如く凹凸を有する半導体基板２１の表面
に塗布によって絶縁層もしくは導体層（以下塗布層と略
す）２３を形成した状態を示す。凹凸を有する半導体基
板２１の表面に塗布によって形成された塗布層２３は、
突起部Ｃや段差上部りなどには薄く被着するため、全体
として半導体基板２１の表面は平坦化となる。In contrast, the present invention provides a method for improving the reliability of a layer formed thereon by removing or significantly reducing the unevenness on the surface of a semiconductor substrate as described above. The present invention will be explained in detail with reference to FIG. Masu, 2nd
As shown in Figure (a), an insulating layer or a conductive layer (hereinafter abbreviated as a coating layer) 23 is formed by coating on the surface of a semiconductor substrate 21 having unevenness. The coating layer 23 formed by coating on the surface of the semiconductor substrate 21 having unevenness is
The surface of the semiconductor substrate 21 is flattened as a whole because it is thinly deposited on the protrusions C and the tops of the steps.
塗布層２３の材料としては、半導体基板２１のエツチン
グ速度と同程度のエツチング速度を有する材料を用いる
。エツチング速度は±５０％の差であｎは実用上好まし
く、特に±３０％の範囲が好ましい。As the material for the coating layer 23, a material having an etching rate comparable to that of the semiconductor substrate 21 is used. The difference in etching rate is ±50%, and n is practically preferable, and a range of ±30% is particularly preferable.
次にこのような半導体基板２１の表面をエツチングする
が、エツチング方法としてはＡｒガスを用いたスパッタ
エツチングが知られているが、Ａｒガスを用いた場合、
Ｓ ｒ ＋ Ｓ ｉ ０２や塗布膜のエッチ速度かたか
だが２００λ／ｍ ｉ ｎであって、エツチングに長時
間を要するという欠点がある。Next, the surface of such a semiconductor substrate 21 is etched. As an etching method, sputter etching using Ar gas is known, but when Ar gas is used,
The etch rate of S r + S i 02 and the coating film is approximately 200λ/min, which has the drawback of requiring a long time for etching.
そｎに対して本発明では塩素または臭素またはフッ素の
うちの少なくとも一部を含む有機系炭素化合物を用いる
。たとえばＯＦ４、ＯＨＦ ３、ｏ２Ｆ４、Ｃ２ＨＦ３
等の少なくとも一部ガスと最高２０％までの濃度での酸
素との混合ガスを用いてスパッタエツチングによってＳ
ｉもしくはＳ ＋ ０２ Ｋよる凹凸を有する半導体基
板２１上に０部几（東京応化製）やＫ Ｔ Ｆ ｌａ
（Ｋｏｄａｋ社製）、ＡＺ１３５０（５ｈｉｐ１ｅｙ）
、あるいは東京応化工業製の０ＦＰＲ１Ｏ８Ｒ，ＮＭ几
などのホトレジストやポリイミド樹脂などを塗布した表
面をエツチングする。またＡ７もしくはＡｔとＳｉある
いはＡｌとＳｉとＭｎの合金など、Ｓｌ、８ ｉ ０２
による凹凸が共存すル半導体基板２１４Ｃ対し、テハ０
０ ｔ３Ｆ、 ０Ｏｔ２Ｆ２、ＯＨＯｔＦ２など塩素と
フッ素の両方を含むガスに必要に応じて酸素を０〜２０
％の範囲で混合したガスを用いることが好ましい。以上
に述べた方法で半導体基板２１の表面をエツチングする
と、まず塗布層２３の上面が除去され、次いで第２図（
ｂ）−に示す如く塗布層２３と共に半導体基板２１の表
面の突起部Ｃや段差上部りなども同時に除去さｎ。In contrast, the present invention uses an organic carbon compound containing at least a portion of chlorine, bromine, or fluorine. For example OF4, OHF 3, o2F4, C2HF3
S by sputter etching using a gas mixture of at least some of the gases such as and oxygen at a concentration of up to 20%.
0 parts (manufactured by Tokyo Ohka) or K T F la is applied on the semiconductor substrate 21 having unevenness due to i or S
(manufactured by Kodak), AZ1350 (5hip1ey)
Alternatively, a surface coated with a photoresist such as 0FPR1O8R, NM (manufactured by Tokyo Ohka Kogyo Co., Ltd.) or polyimide resin is etched. Also, A7 or alloys of At and Si or Al, Si and Mn, etc., Sl, 8 i 02
For the semiconductor substrate 214C where unevenness coexists due to
If necessary, add 0 to 20% oxygen to a gas containing both chlorine and fluorine, such as 0t3F, 0Ot2F2, OHOtF2.
It is preferable to use a mixture of gases within a range of %. When the surface of the semiconductor substrate 21 is etched by the method described above, the upper surface of the coating layer 23 is first removed, and then the upper surface of the coating layer 23 is etched as shown in FIG.
As shown in b)--, along with the coating layer 23, the protrusions C and the tops of the steps on the surface of the semiconductor substrate 21 are also removed at the same time.
遂には第２図（Ｃ）に示すように塗布層２３と半導体基
板２１の一部または全部が除去されて表面は平坦化され
る。次いでこの半導体基板２１の表面に真空蒸着法や化
学蒸着法もしくはスパッタリング法によって形成層２２
を被着する。Finally, as shown in FIG. 2(C), part or all of the coating layer 23 and the semiconductor substrate 21 are removed and the surface is planarized. Next, a layer 22 is formed on the surface of the semiconductor substrate 21 by vacuum evaporation, chemical vapor deposition, or sputtering.
be coated with.
次に実施例によって本発明の詳細な説明する。 Next, the present invention will be explained in detail by way of examples.
実施例１゜
半導体基板として３ｉ基板を用いて半導体装置を製造す
る場合、通常−回収上の不純物拡散およびＳ ｒ ０２
膜の形成が行なわれる。これらの工程を経る間にＳｉ基
板表面には様々の形状の８ ＋ ０２による凹凸が形成
される。第３図（ａ）はその−例を示す。同図で、半導
体基板として用いたＳｉ基板３１上に熱酸化法や真空蒸
着法や化学蒸着法もしくはスパッタリング法で８１０□
膜３４が形成されている状態を示す。同図Ｅ部はたとえ
ば不純物拡散のために形成された開口に起因する凹凸を
、Ｆ部は厚い局所熱酸化によｊｌ Ｓ ｒ ０２膜を形
成する際に生じた突起を示す。通常８部の段差ｈ ｉｌ
ｊ ０．２〜０．７μ程度Ｆ部の高さｋは０．５〜１．
２μ程度である。このような半導体基板に対して第３図
（ｂ）の如く塗布によって、たとえば１．５μ程度の厚
さのＫＴＦＲ（商品名）ホトレジストの塗布層３３を形
成する。塗布層３３はＳ ｉ ０２膜３４の凹凸を埋め
るように形成され、その表面は平坦化される。Example 1 When manufacturing a semiconductor device using a 3i substrate as a semiconductor substrate, impurity diffusion and S r 02 during normal recovery
Formation of the film takes place. During these steps, 8 + 02 irregularities of various shapes are formed on the surface of the Si substrate. FIG. 3(a) shows an example thereof. In the same figure, 810□ is deposited on a Si substrate 31 used as a semiconductor substrate by a thermal oxidation method, a vacuum evaporation method, a chemical vapor deposition method, or a sputtering method.
A state in which a film 34 is formed is shown. Section E in the figure shows irregularities caused by, for example, openings formed for impurity diffusion, and section F shows protrusions generated when forming the jl S r 02 film by thick local thermal oxidation. Normally 8 parts height difference
j about 0.2 to 0.7μ, and the height k of the F section to about 0.5 to 1.
It is about 2μ. A coating layer 33 of KTFR (trade name) photoresist having a thickness of, for example, about 1.5 μm is formed on such a semiconductor substrate by coating as shown in FIG. 3(b). The coating layer 33 is formed to fill in the irregularities of the Si 02 film 34, and its surface is flattened.
次にたとえば０ＯＪ２Ｆ２ガスを用い真空度４×１０Ｔ
ｏｒｒ、高周波電力１．５ Ｗ ／ ｃｍ２（２）条件
テスパッタエッチングを行なう。上の条件下で、Ｓ １
０２のエッチ速度は約６００Ｘ／ｍｉｎ 、 ＫＴ Ｆ
Ｒノエッチ速度は５５０Ａであって両者は図３（ｃ）
に示す如＜ ｌ’ｔぼ一様にエツチングさｎる。約２５
ｍ１ｎのスパッタエツチングを行なうと、第３図（ｄ）
に示すように塗布層３３全体と５ｉｏ２膜３４の突出部
が除去されて、Ｓｉ基板３１上の８３０□膜３４表面は
平坦化される。この上にたとえば真空蒸着法や化学蒸着
法もしくはスパッタリング法で導体層や絶縁層３２を形
成すると、第１図（ｂ）に示した如き基板の凹凸部分で
形成層が薄くなったシ切断したりする欠陥は存在せずそ
の信頼性は従来法に比して著しく向上する。Next, for example, using 0OJ2F2 gas, the vacuum level is 4 x 10T.
orr, high frequency power 1.5 W/cm2 (2) condition test sputter etching is performed. Under the above conditions, S 1
Etch speed of 02 is about 600X/min, KTF
The R no etch speed is 550A, and both are shown in Fig. 3(c).
It is etched almost uniformly as shown in the figure. Approximately 25
When sputter etching of m1n is performed, the result is as shown in Fig. 3(d).
As shown in FIG. 3, the entire coating layer 33 and the protruding portions of the 5io2 film 34 are removed, and the surface of the 830□ film 34 on the Si substrate 31 is flattened. If a conductive layer or an insulating layer 32 is formed on this layer by, for example, a vacuum evaporation method, a chemical vapor deposition method, or a sputtering method, the formed layer may be thinned and cut due to uneven parts of the substrate as shown in FIG. 1(b). There are no defects, and its reliability is significantly improved compared to conventional methods.
なおホトレジストやポリイミド樹脂の種類によってエッ
チ速度に多少の変化が生ずるが、樹脂の方がエッチ速度
が小さいとき酸素を混合することでエッチ速度を８ ＋
０２や８ｉのそれと等しくなるよう調整できる。Note that the etch rate will vary slightly depending on the type of photoresist or polyimide resin, but when the etch rate of the resin is lower, mixing oxygen can increase the etch rate to 8 +
It can be adjusted to be equal to that of 02 and 8i.
実施例２゜
本発明は半導体基板上に形成されｆｃｌ、２μ厚のＡｊ
配線の側面形状をなだらかにする場合に適用できる。Embodiment 2゜The present invention is formed on a semiconductor substrate, fcl, 2μ thick Aj
It can be applied when making the side shape of the wiring smooth.
第４図（ａ）は半導体基板４１上にホトエツチング（よ
ってＡＡ配線４５を形成した状態を示す。配線側面の角
度は４５〜６５° となっており、この上に絶縁被膜を
形成するとＡｔ配線４５の端部で段切ｎが生じたりする
ことが多い。そこで第４図（ｂ）に示す如く、半導体基
板４’ｌ上に厚さ４０００Ａポリイミド樹脂の層４３を
塗布する。次いで００ｔ２Ｆガスに酸素を４％混入した
ガスを用い、ガス圧４ Ｘ １．０−２Ｔｏｒｔ、高周
波電力ＩＷ／Ｃｍ２でスパッタエツチングを行なう。こ
の条件でポリイミド樹脂のエッチ速度は約８００ Ａ
／ｍｉｎ 、 Ａ ｔのエツチング速度は約７５０＾／
ｍｉｎであった。従って第４図（Ｃ）に示す如く、Ａｊ
、ポリイミド樹脂は同時にエツチングされる。約８ｍ１
ｎのエツチングで第４図（ｄ）に示す如く、ポリイミド
樹脂はほぼ完全に除去され、Ａｊ配線もなだらかな形状
にエツチングされる（Ａｔ厚は約１μが残る）。また半
導体基板４１の表面の８ ｉ ０２のエッチ速度は約１
５′０＾／ ｍ ｌ ｎであって上記のエツチングでは
僅かしかエツチングされない。第４図（ｄｌの如き配線
形状は第１図（ｂ）で説明した如く、半導体集積回路の
製造において極めて望ましいものである。FIG. 4(a) shows a state in which an AA wiring 45 is formed on a semiconductor substrate 41 by photoetching.The angle of the side surface of the wiring is 45 to 65 degrees, and when an insulating film is formed on this, an At wiring 45 is formed. In many cases, a step n is formed at the edge of the semiconductor substrate 4'l.Therefore, as shown in FIG. Sputter etching is performed using a gas mixed with 4% of polyimide resin at a gas pressure of 4 x 1.0-2 Tort and a high frequency power of IW/Cm2. Under these conditions, the etch rate of the polyimide resin is approximately 800 A.
/min, the etching speed of At is about 750^/
It was min. Therefore, as shown in FIG. 4(C), Aj
, the polyimide resin is etched at the same time. Approximately 8m1
As shown in FIG. 4(d), as shown in FIG. 4(d), the polyimide resin is almost completely removed, and the Aj wiring is also etched into a gentle shape (about 1 μm of At thickness remains). Further, the etch rate of 8 i 02 on the surface of the semiconductor substrate 41 is approximately 1
5'0^/ml n, and the above etching etches only a small amount. The wiring shape as shown in FIG. 4 (dl) is extremely desirable in the manufacture of semiconductor integrated circuits, as explained in FIG. 1(b).
上記発明から明らかなように、本発明によれば、基板上
の凹凸を極めて容易かつ確実に平坦化することが可能で
あり、集積密度の高い半導体装置の形成に有用である。As is clear from the above invention, according to the present invention, unevenness on a substrate can be planarized extremely easily and reliably, and is useful for forming semiconductor devices with high integration density.
第１図は本発明の説明に供する従来法を示す断面図、第
２図は本発明を説明する断面図、第３図、第４図は本発
明の実施例を示す断面図。
第７の
（７２，）
（ｂ）
ＹＺ刀
（ｂ）
（こ）
第１
（こ）FIG. 1 is a sectional view showing a conventional method for explaining the present invention, FIG. 2 is a sectional view for explaining the present invention, and FIGS. 3 and 4 are sectional views showing embodiments of the present invention. 7th (72,) (b) YZ sword (b) (ko) 1st (ko)
Claims (1)
塗布被膜を形成して表面を平坦化する工程と、塩素、臭
素およびフッ素より成る群から選ばれた少なくとも１種
を含むガス状の有機化合物と酸素を含むガスを用いたス
パッタエッチングを行なって上記塗布被膜と上記基板の
突出部の少なくとも一部を同時に除去し上記表面を平坦
化する工程を含み、上記ガスを用いたスパッタエッチン
グに対する上記塗布被膜と上記基板のエッチング速度の
差は±５０％以内であることを特徴とする基板の処理方
法。A step of forming a coating film on a substrate having an uneven surface to fill the unevenness to flatten the surface, and a step of flattening the surface by forming a coating film on a substrate having an uneven surface; The step of performing sputter etching using a gas containing a compound and oxygen to simultaneously remove the applied film and at least a part of the protrusion of the substrate to flatten the surface, A method for processing a substrate, characterized in that the difference in etching rate between the applied film and the substrate is within ±50%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10370885A JPS6122632A (en) | 1985-05-17 | 1985-05-17 | Surface processing of substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10370885A JPS6122632A (en) | 1985-05-17 | 1985-05-17 | Surface processing of substrate |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4771576A Division JPS52131471A (en) | 1976-04-28 | 1976-04-28 | Surface treatment of substrate |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19538286A Division JPS6276520A (en) | 1986-08-22 | 1986-08-22 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6122632A true JPS6122632A (en) | 1986-01-31 |
| JPS641931B2 JPS641931B2 (en) | 1989-01-13 |
Family
ID=14361233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10370885A Granted JPS6122632A (en) | 1985-05-17 | 1985-05-17 | Surface processing of substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6122632A (en) |
-
1985
- 1985-05-17 JP JP10370885A patent/JPS6122632A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS641931B2 (en) | 1989-01-13 |
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