JPS61225878A - Manufacture of semiconductor photodetector - Google Patents
Manufacture of semiconductor photodetectorInfo
- Publication number
- JPS61225878A JPS61225878A JP60065064A JP6506485A JPS61225878A JP S61225878 A JPS61225878 A JP S61225878A JP 60065064 A JP60065064 A JP 60065064A JP 6506485 A JP6506485 A JP 6506485A JP S61225878 A JPS61225878 A JP S61225878A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- guard ring
- groove
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 125000005842 heteroatom Chemical group 0.000 abstract description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910001423 beryllium ion Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000031700 light absorption Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid group Chemical group S(O)(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 235000011149 sulphuric acid Nutrition 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 241000321817 Nasa Species 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は、ガード・リングを備え、アバランシェ増倍現
象を利用して動作するプレーナ型の半導体受光素子を製
造する場合に於いて、半導体基板上の一導電型増倍層を
メサ状にエツチングし、次いで、前記メサ状一導電型増
倍層を埋め込む同導電型且つ低不純物濃度である埋め込
み層を形成し、次いで、前記一導電型低不純物濃度埋め
込み層内に於けるガード・リング形成予定部分に倣う溝
を形成し、次いで、前記溝を介して反対導電型不純物の
拡散を行ってガード・リングを形成することに依り、機
能的に優れ且つ信頼性が高いガード・リングを有する半
導体受光素子を得られるようにするものである。[Detailed Description of the Invention] [Summary] The present invention provides a method for manufacturing a planar type semiconductor light receiving element that is equipped with a guard ring and operates using an avalanche multiplication phenomenon. The type multiplication layer is etched into a mesa shape, and then a buried layer of the same conductivity type and low impurity concentration is formed to bury the mesa-shaped one conductivity type multiplication layer, and then the one conductivity type low impurity concentration buried layer is etched. By forming a groove that follows the area in which the guard ring is to be formed, and then diffusing an opposite conductivity type impurity through the groove to form the guard ring, it is possible to achieve excellent functionality and reliability. This makes it possible to obtain a semiconductor light-receiving element having a high guard ring.
本発明は、プレーナ型アバランシェ・フォト・ダイオー
ド（ａｖａｌａｎｃｈｅ ｐｈｏｔ。The present invention relates to a planar avalanche photodiode (avalanche photodiode).
ｄｉｏｄｅ：ＡＰＤ）と呼ばれる半導体受光素子を製造
する方法の改良に関する。This invention relates to an improvement in a method of manufacturing a semiconductor light receiving element called a diode (APD).
現在、ｌ 〔μｍ〕帯の光通信用半導体受光素子として
、高感度であるｍ−ｖ族化合物半導体を用いたＡＰＤの
開発が盛んに行われている。Currently, APDs using high-sensitivity m-v group compound semiconductors are being actively developed as semiconductor light-receiving devices for optical communication in the l [μm] band.
第２図は従来のプレーナ型ＡＰＤの要部切断側面図を表
している。FIG. 2 shows a cutaway side view of essential parts of a conventional planar APD.
図に於いて、１はｎ＋＋１ｎＰ基板、２はｎ型Ｇａ１ｎ
Ａｓ光吸収層、３はｎ型Ｇａ１ｎＡｓＰへテロ・バリヤ
緩和層、４はｎ型１ｎＰ増倍層、５はｎ−型１ｎＰ埋め
込み層、６はｐ＋＋１ｎＰ受光領域、７はｐ型１ｎＰガ
ード・リング層、８は絶縁膜、９は電極をそれぞれ示し
ている。In the figure, 1 is an n++1nP substrate, 2 is an n-type Ga1n
As light absorption layer, 3 is n-type Ga1nAsP hetero barrier relaxation layer, 4 is n-type 1nP multiplication layer, 5 is n-type 1nP buried layer, 6 is p++1nP light receiving region, 7 is p-type 1nP guard ring layer , 8 indicates an insulating film, and 9 indicates an electrode.
図示例では、ｐ＋＋１ｎＰ受光領域６及びその直下に在
るｎ型１ｎＰ増倍層４に依って生成されているｐｎ接合
に於けるブレイク・ダウン耐圧を他の部分に於けるそれ
に対して相対的に低く維持する為、ｐ＋＋１ｎＰ受光領
域６及びｎ型１ｎＰ増倍層４をｎ−型１ｎＰ埋め込み層
５で囲むようにしたり、ｎ−型ＩｎＰ埋め込み層５中に
ｐ＋型型光光領域６接するようにｐ型１ｎＰガード・リ
ング層７を形成するようにしている。In the illustrated example, the breakdown voltage at the pn junction generated by the p++1nP light-receiving region 6 and the n-type 1nP multiplication layer 4 located directly below it is compared to that at other parts. In order to maintain a low level, the p++ 1nP light-receiving region 6 and the n-type 1nP multiplication layer 4 are surrounded by the n-type 1nP buried layer 5, or the p+-type light region 6 is placed in contact with the n-type InP buried layer 5. A p-type 1nP guard ring layer 7 is formed.
一般に、この種の半導体受光素子の信転性及び製造歩留
りを向上するにはプレーナ型にすることが望ましいが、
ブレーナ型半導体受光素子に於いては、第２図に関して
説明したようなブレイク・ダウン耐圧差を得る為の構成
、特に、ガード・リングを設ける構成は不可欠である。Generally, in order to improve the reliability and manufacturing yield of this type of semiconductor photodetector, it is desirable to use a planar type.
In the Brehner-type semiconductor light-receiving element, a structure for obtaining a breakdown voltage difference as explained with reference to FIG. 2, especially a structure in which a guard ring is provided, is essential.
ところで、第２図の半導体受光素子に関して説明したよ
うな構成、即ち、ｐ型ＩｎＰガード・リング層７を形成
するには、イオン注入法を適用することに依り、ベリリ
ウム（Ｂｅ）イオンを打ち込んでから熱処理を行って拡
散する技法を採用している。By the way, in order to form the structure explained with respect to the semiconductor light receiving element in FIG. 2, that is, the p-type InP guard ring layer 7, beryllium (Be) ions are implanted by applying an ion implantation method. We use a technique that involves heat treatment and diffusion.
ところが、Ｂｅイオンを注入した後、例えば温度５５０
（’Ｃ）で熱処理を行っても、ガード・リング７の深さ
は高々工 〔μｍ〕程度にしかならない。However, after implanting Be ions, for example, the temperature is 550°C.
Even if the heat treatment is performed in ('C), the depth of the guard ring 7 will only be about 10 μm.
このように、Ｂｅが深く拡散しないことは、ガード・リ
ング７の形状がＢｅイオンを注入したままの状態に於け
るそれと大差ないことを意味し、従って、ガード・リン
グ７で生成される接合面の周辺部分に於ける曲率はかな
り小さいものになっていて、当然、そこでの耐圧は低く
なってしまうから、充分なガード・リング効果が得られ
ないことになる。尚、現在、ＩｎＰをｐ＋型にするには
カドミウム（Ｃｄ）或いは亜鉛（Ｚｎ）など好ましい不
純物が知られているが、それよりも低濃度のｐ型にする
にはＢｅが最も良いとされでいる。In this way, the fact that Be does not diffuse deeply means that the shape of the guard ring 7 is not much different from that in the state in which Be ions are implanted, and therefore the junction surface created by the guard ring 7 The curvature in the peripheral portion of the ring is quite small, and the withstand voltage there is naturally low, so a sufficient guard ring effect cannot be obtained. Currently, preferred impurities such as cadmium (Cd) and zinc (Zn) are known to make InP p+ type, but Be is said to be the best impurity to make it p type at a lower concentration. There is.
本発明一実施例を説明する為の図である第１図を借りて
説明する。An explanation will be given with reference to FIG. 1, which is a diagram for explaining one embodiment of the present invention.
本発明に依る手段では、ｎ１型１ｎＰ基板１１（半導体
基板）上のｎ型１ｎＰ増倍層１４（−導電型増倍層）を
メサ状にエツチングし、次いで、前記メサ状ｎ型１ｎＰ
増倍層１４を埋め込むｎ−型１ｎＰ埋め込み層１５（同
導電型且つ低不純物濃度である埋め込み層）を形成し、
次いで、前記ｎ′″型１ｎＰ埋め込み層１５内に於ける
ガード・リング形成予定部分に倣う溝１５Ａを形成し、
次いで、前記溝１５Ａを介してｐ型不純物（反対導電型
不純物）の拡散を行ってガード・リング１６を形成する
工程を採っている。In the method according to the present invention, the n-type 1nP multiplication layer 14 (-conductivity type multiplication layer) on the n1-type 1nP substrate 11 (semiconductor substrate) is etched into a mesa shape, and then the mesa-shaped n-type 1nP
Forming an n-type 1nP buried layer 15 (a buried layer of the same conductivity type and low impurity concentration) that buries the multiplication layer 14,
Next, a groove 15A is formed in the n''' type 1nP buried layer 15 to follow the part where the guard ring is to be formed.
Next, a step is adopted in which a p-type impurity (opposite conductivity type impurity) is diffused through the groove 15A to form a guard ring 16.
前記手段に依ると、ガード・リング１６はｎ−型１ｎＰ
埋め込み層１５に予め形成された溝１５Ａを介してｐ型
不純物を拡散して形成されるものであるから、溝１５Ａ
を形成した分だけ深くなって、ｐｎ接合面の周辺に於け
る曲率は大きくなるので、その部分の耐圧は充分に高く
なり、ガード・リング効果は向上する。According to the above means, the guard ring 16 is of n-type 1nP.
Since the trench 15A is formed by diffusing p-type impurities through the trench 15A previously formed in the buried layer 15, the trench 15A is
The depth increases by the amount that is formed, and the curvature around the pn junction surface increases, so the withstand voltage at that portion becomes sufficiently high and the guard ring effect improves.
第１図（Ａ）及び（Ｂ）は本発明一実施例を解説する為
の工程要所に於ける半導体受光素子の要部切断側面図を
表し、以下、これ等の図を参照しつつ説明する。FIGS. 1(A) and 1(B) are cross-sectional side views of essential parts of a semiconductor light-receiving element at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. do.
第１図（Ａ）参照
＋ａ） 例えば液相成長（ｌｉｑｕｉｄ ｐｈａｓ
ｅｅｐｉｔａｘｙ：ＬＰＥ）法を適用することに依り、
ｎ＋＋１ｎＰ基板１１上にｎ型Ｇａ１ｎＡｓ光吸収層１
２、ｎ型ＧａＩｎＡＳＰヘテロ・バリヤ緩和層−１３、
ｎ型ＩｎＰ増倍層１４のそれぞれを成長させる。See Figure 1 (A) +a) For example, liquid phase growth (liquid phas growth)
By applying the eepitaxy:LPE) method,
n-type Ga1nAs light absorption layer 1 on n++1nP substrate 11
2, n-type GaInASP hetero barrier relaxation layer-13,
Each of the n-type InP multiplication layers 14 is grown.
この場合の各半導体層のデータを示すと次の通りである
。The data for each semiconductor layer in this case is as follows.
（１）ｎ型Ｇａ Ｉ ｎＡｓＡｓ光吸収層厚２厚約２〔
μｍ〕程度
不純物濃度： ｌ Ｘ Ｉ Ｑ” （ａｍ−’）（２）
ｎ型Ｇａ１ｎＡｓＰへテロ・バリヤ緩和層厚さ：約０．
５〔μｍ〕程度
不純物濃度： Ｉ Ｘ １０１６（ｃｍ−’）（３）ｎ
型１ｎＰ増倍層１４
厚さ：約２．５〔μｍ〕
不純物濃度７１〜２Ｘ １０” （ｃ！ｍ−’）（ｂ）
例えばプラズマＣＶＤ （ｐｌａｓｍａ ｃｈｅ
ｍｉｃａｌ ｖａｐｏｕｒ ｄｅｐｏｓｉｔｔｏｎ
）法を適用することに依り、窒化シリコン膜を形成し、
これを通常のフォト・リソグラフィ技術を適用すること
に依ってバターニングしてｎ型１ｎＰ増倍層１４の表面
を選択的に覆う保護膜とする。(1) N-type Ga I nAsAs light absorption layer thickness 2 thickness approx.
[μm] impurity concentration: l X I Q” (am-') (2)
N-type Ga1nAsP hetero barrier relaxation layer thickness: approx. 0.
About 5 [μm] Impurity concentration: I x 1016 (cm-') (3) n
Type 1nP multiplication layer 14 Thickness: Approximately 2.5 [μm] Impurity concentration 71~2X 10"(c!m-') (b)
For example, plasma CVD
medical vapor deposition
) method to form a silicon nitride film,
This is patterned by applying ordinary photolithography technology to form a protective film that selectively covers the surface of the n-type 1nP multiplication layer 14.
（Ｃ） 前記保護膜をマスクに、そして、エッチャン
トを硫酸と過酸化水素と水（Ｈ２ＳＯ４＋Ｈ２Ｏ２＋Ｈ
２０）の混合液とするウェット・エツチング法を適用す
ることに依り、ｎ型１ｎＰ増倍層１４のメサ・エツチン
グを行う。(C) Using the above protective film as a mask, etchant is sulfuric acid, hydrogen peroxide, and water (H2SO4+H2O2+H2SO4+H2O2+H
Mesa etching of the n-type 1nP multiplication layer 14 is performed by applying the wet etching method using the mixed solution of 20).
＋ｄ） メサ・エツチングのマスクとして用いた前記
窒化シリコンからなる保護膜を除去してから、再び、Ｌ
ＰＥ法を適用することに依り、ｎ−型ＩｎＰ埋め込み層
１５を形成する。尚、この場合、ｎ−型ＩｎＰ埋め込み
層１５の厚さは約２〔μｍ〕となる。+d) After removing the protective film made of silicon nitride used as a mesa etching mask, repeat the L etching process.
By applying the PE method, an n-type InP buried layer 15 is formed. In this case, the thickness of the n-type InP buried layer 15 is about 2 [μm].
（ｅ） 工程（ｂｌと同様にして窒化シリコンからな
り且つ溝状の開口を有している保護膜を形成してから、
それをマスクとして、受光領域形成予定部分を囲む深さ
約０．５〔μｍ〕程度、幅約２０〔μｍ〕の溝１５Ａを
形成する。(e) Step (After forming a protective film made of silicon nitride and having a groove-shaped opening in the same manner as in bl,
Using this as a mask, a groove 15A having a depth of approximately 0.5 [μm] and a width of approximately 20 [μm] is formed surrounding the portion where the light receiving region is to be formed.
尚、この場合のエッチャントとしては、例えば（Ｂｒ＋
ＨＢｒ＋Ｈ２０）混合液を用いることができる。In this case, the etchant is, for example, (Br+
A mixture of HBr+H20) can be used.
（ｆｌ 溝１５Ａを形成する為にマスクとして用いた
保護膜をそのまま残し、イオン注入法を適用すことに依
り、Ｂｅイオンの打ち込みを行い、熱処理を行って、ｐ
型ガード・リング１６を形成する。(fl By leaving the protective film used as a mask for forming the groove 15A as it is and applying the ion implantation method, Be ions are implanted, heat treatment is performed, and p
A mold guard ring 16 is formed.
Ｂｅイオンの注入を行う場合、
ドーズＮ： ｌ ｘ ｌ Ｑ １３（ａｍ−”）注入エ
ネルギ：１００（ＫｅＶ）
とし、また、熱処理は、
温度：５５０（”Ｃ）
時間＝６０〔分〕
とした。When implanting Be ions, the dose N: l x l Q 13 (am-"), the implantation energy: 100 (KeV), and the heat treatment was performed at the following temperature: 550 ("C) and time = 60 [minutes]. .
これに依り、ｐ型ガード・リング１６゛の深さは溝１５
Ａの底から約１ 〔μｍ〕程度になり、接合周辺の曲率
は充分になだらかなものとなって、耐圧向上に寄与する
ことができる。Accordingly, the depth of the p-type guard ring 16 is the groove 15.
The distance is about 1 [μm] from the bottom of A, and the curvature around the junction becomes sufficiently gentle, which can contribute to improving the breakdown voltage.
（幻 新たに適当なマスクを形成し、イオン注入法を適
用することに依り、Ｃｄイオン或いはＺｎイオンの打ち
込みを行ってｐ＋型ＩｎＰ受光領域１７を形成する。(Illusion) By forming a new appropriate mask and applying the ion implantation method, Cd ions or Zn ions are implanted to form the p+ type InP light-receiving region 17.
尚、この工程は、ｐ型ガード・リング１６を形成する一
連の工程以前、即ち、工程（ｅ）の前に行うこともでき
る。Note that this step can also be performed before the series of steps for forming the p-type guard ring 16, that is, before step (e).
第１図（Ｂ）参照
（ｈ） 通常の技法を適用するごとに依り、新たな窒
化シリコンからなる絶縁膜１８、電極１９及び２０など
を形成して完成する。尚、電極１９はＴ ｉ ／ Ｐ
ｔ ／ Ａ ｕ或いはＡｕ−Ｚｎ／Ａｕなどを、また、
電極２０としてはＡｕ−Ｇｅ合金を用いることができる
。Refer to FIG. 1(B) (h) A new insulating film 18 made of silicon nitride, electrodes 19 and 20, etc. are formed by applying the usual techniques to complete the process. Note that the electrode 19 is T i /P
t/Au or Au-Zn/Au, etc.
As the electrode 20, an Au-Ge alloy can be used.
本発明に依る半導体受光素子の製造方法では、半導体基
板上の一導電型増倍層をメサ状にエツチングし、次いで
、前記メサ状一導電型増倍層を埋め込む同導電型且つ低
不純物濃度である埋め込み層を形成し、次いで、前記一
導電型低不純物濃度埋め込み層内に於けるガード・リン
グ形成予定部分に倣う溝を形成し、次いで、前記溝を介
して反対導電型不純物の拡散を行ってガード・リングを
形成するようにしている。In the method for manufacturing a semiconductor light-receiving device according to the present invention, a multiplier layer of one conductivity type on a semiconductor substrate is etched into a mesa shape, and then a multiplier layer of the same conductivity type and with a low impurity concentration is etched to bury the mesa-shaped multiplier layer of one conductivity type. A certain buried layer is formed, and then a groove is formed in the low impurity concentration buried layer of one conductivity type to follow a portion where a guard ring is to be formed, and then an impurity of the opposite conductivity type is diffused through the groove. to form a guard ring.
このようにすると、ガード・リングは、溝を形成した分
だけ深（形成され、しかも、ｐｎ接合の周辺部分での曲
率を大きくして、なだらかに立ち上げることができるの
で、良好な傾斜接合が生成れ、高い耐圧、即ち、確実な
ガード・リング効果を得ることができるものであり、例
えば第２図に見られる従来例に於けるガード・リングの
耐圧が約１４０（Ｖ）であるのに対し、第１図に見られ
る本発明一実施例のそれは約２０（Ｖ）程度向上し、約
１６０（Ｖ）にも達した。In this way, the guard ring is formed as deep as the groove is formed, and the curvature at the peripheral part of the pn junction is increased so that it can rise gently, resulting in a good sloped junction. It is possible to obtain a high withstand voltage, that is, a reliable guard ring effect.For example, the withstand voltage of the guard ring in the conventional example shown in Fig. 2 is about 140 (V). On the other hand, that of the embodiment of the present invention shown in FIG. 1 was improved by about 20 (V), reaching about 160 (V).
第１図（Ａ）及び（Ｂ）は本発明一実施例を説明する為
の工程要所に於ける半導体受光素子の要部切断側面図、
第２図は従来例の要部切断側面図をそれぞれ表している
。
図に於いて、１１はｎ＋型１ｎＰ基板、１２はｎ型Ｇａ
Ｉ ｎＡｓ光吸収層、１３はｎ型Ｇａ１ｎＡｓＰへテ
ロ・バリヤ緩和層、工４はｎ型１ｎＰ増倍層、１５はｎ
−型！ｎＰ埋め込み層、１５Ａは溝、１６はｐ型１ｎＰ
ガード・リング、１７はｐ＋型ＩｎＰ受光領域、１８は
絶縁膜、１９及び２０は電極をそれぞれ示している。
（Ａ）
第１図
（Ｂ）
受光素子の要部切断側面図
第１図
従来例の要部切断側面図
第２図FIGS. 1A and 1B are cross-sectional side views of essential parts of a semiconductor light-receiving element at key points in the process for explaining one embodiment of the present invention;
FIG. 2 each shows a cutaway side view of the main part of the conventional example. In the figure, 11 is an n+ type 1nP substrate, 12 is an n-type Ga
13 is an n-type Ga1nAsP hetero barrier relaxation layer, 4 is an n-type 1nP multiplication layer, 15 is an nAs light absorption layer, 13 is an n-type Ga1nAsP hetero barrier relaxation layer,
-Type! nP buried layer, 15A is groove, 16 is p-type 1nP
A guard ring, 17 a p+ type InP light receiving region, 18 an insulating film, and 19 and 20 electrodes, respectively. (A) Fig. 1 (B) Cutaway side view of main parts of light receiving element Fig. 1 Cutaway side view of main parts of conventional example Fig. 2
Claims (1)
、 次いで、前記メサ状一導電型増倍層を埋め込む同導電型
且つ低不純物濃度である埋め込み層を形成し、 次いで、前記一導電型低不純物濃度埋め込み層内に於け
るガード・リング形成予定部分に倣う溝を形成し、 次いで、前記溝を介して反対導電型不純物の拡散を行っ
てガード・リングを形成する工程が含まれてなることを
特徴とする半導体受光素子の製造方法。[Claims] A multiplication layer of one conductivity type on a semiconductor substrate is etched into a mesa shape, and then a buried layer of the same conductivity type and with a low impurity concentration is formed to bury the multiplication layer of one conductivity type in the mesa shape. Next, a groove is formed in the low impurity concentration buried layer of one conductivity type to follow the part where a guard ring is to be formed, and then an impurity of the opposite conductivity type is diffused through the groove to form a guard ring. 1. A method for manufacturing a semiconductor light-receiving device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60065064A JPS61225878A (en) | 1985-03-30 | 1985-03-30 | Manufacture of semiconductor photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60065064A JPS61225878A (en) | 1985-03-30 | 1985-03-30 | Manufacture of semiconductor photodetector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61225878A true JPS61225878A (en) | 1986-10-07 |
Family
ID=13276149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60065064A Pending JPS61225878A (en) | 1985-03-30 | 1985-03-30 | Manufacture of semiconductor photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61225878A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09148618A (en) * | 1995-11-24 | 1997-06-06 | Hamamatsu Photonics Kk | Silicon avalanche photodiode |
-
1985
- 1985-03-30 JP JP60065064A patent/JPS61225878A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09148618A (en) * | 1995-11-24 | 1997-06-06 | Hamamatsu Photonics Kk | Silicon avalanche photodiode |
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