JP2736089B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a semiconductor device formed by Mg ion implantation, in particular, an avalanche photodiode (hereinafter, APD).
And a method for producing the same.

(Prior Art) An APD is a light receiving element that multiplies carriers by utilizing an avalanche multiplication effect accompanying breakdown of a PN junction. Planar AP
In D, a guard ring is provided around the light-receiving part to suppress local breakdown at the end of the PN junction. The guard ring effect is obtained by increasing. In InGaAs / InP APDs for receiving light in a long wavelength band such as a wavelength of 1.55 μm, a method is generally used in which impurities such as Cd and Zn are diffused into InP to form a light receiving portion, and Be is ion-implanted to form a guard ring. ing.

By the way, we have applied for a method of using Mg instead of Be as an impurity for forming a card ring (see JP-A-62-69689). This is because Mg forms a more gradual junction than Be, so that a larger breakdown voltage difference than Be can be obtained. Further, the applicant has filed an application in which the effect is further enhanced when Mg is diffused in the lateral direction using outward diffusion (see Japanese Patent Application No. 62-43567). However, even if Be or Mg is used for the guard ring, as long as another impurity is used for the light receiving portion, an overlapping portion must be formed in order to secure an alignment margin in the process. In such an overlapped portion, the inclined portion of the guard ring is covered with high-concentration impurities in the light receiving portion and approaches the stair junction, so that the electric field value applied to the hetero interface from this portion increases. , Our study has shown that dark current increases. To prevent this, the method proposed in Japanese Patent Application No. 63-8272 is effective. That is, when P is ion-implanted into a part of the region into which Mg is ion-implanted and annealed, the region into which P is implanted becomes Mg.
Diffusion is suppressed, and a stair junction is formed. In a region where P is not implanted, Mg is diffused to form an inclined junction. Therefore, the two regions can be connected without requiring the alignment margin as described above. Here, too, Japanese Patent Application No. 62-4356
It goes without saying that the method proposed in 7 is more effective.

(Problems to be solved by the invention) However, this method also has some problems to be solved. First, in this method, it is necessary to perform mask alignment at least three times with a region into which Mg is implanted, a region into which P is implanted, and a region utilizing out-diffusion.

Also, the PN junction that normally serves as a guard ring is formed deeper than the PN junction of the light receiving portion. If the difference in depth is too large, the dark current of the element is dominated by the guard ring.
Conversely, if the difference in depth is small or the guard ring is shallower, the effect of the guard ring is lost. That is, in the design of the APD, in addition to the design of the light receiving unit, the depth relationship between the light receiving unit and the guard ring must be optimally designed. This has the problem of increasing the design parameters and reducing the manufacturing yield.

The present invention has the problem described above, that is, it requires three mask alignments in order to manufacture an APD using Mg effectively, and furthermore, the usual guard ring structure has too many design parameters. It tries to solve the point.

[Configuration of the invention]

(Means for Solving the Problems) A semiconductor device according to the present invention is a III-V compound in which a low-concentration first n-type layer and a high-concentration second n-type layer are sequentially laminated from the surface side. In the semiconductor substrate, Mg is from 10 ¹⁸ cm ^-3 or more to 10 ¹⁵ cm ^-3
A step-shaped main PN junction formed by the p-type layer and the base, which are distributed steeply below the base; and Mg around the main PN junction from the surface side of the semiconductor base to a depth of 10 ¹⁶ cm ^-3.
Gradual distribution from above the table to below 10 ¹⁵ cm ^-3
A step-type sub PN junction formed by a mold layer and the base, wherein the depth of the sub PN junction is smaller than the depth of the main PN junction, and the depth of the sub PN junction is the first
The manufacturing method is characterized in that Mg and P are ion-implanted into one region of the main surface of a III-V compound semiconductor substrate. Forming a region, forming a mask layer on the main surface, providing an opening in the mask layer in a region wider than the ion-implanted region, and performing a heat treatment in a phosphorus atmosphere. Primary PN junction and secondary PN on semiconductor substrate
And a step of forming a junction.

Further, in the semiconductor element, the sub PN junction is
It is formed shallower than the PN junction and shallower than the depth of the first n-type layer.

(Operation) As described in detail in Japanese Patent Application No. 63-8272 related to the earlier application, when Mg and P are simultaneously injected into InP, Mg easily enters the In lattice position in the InP crystal. The diffusion of Mg into the substrate is suppressed, and a steep junction is formed. On the other hand, as described in detail in Japanese Patent Application No.
Since the vapor pressure is extremely high, if annealing is performed without attaching any mask to the substrate surface, Mg diffuses out of the substrate once and then diffuses back into the substrate. The profile of the re-diffused Mg is very gentle. Therefore, Mg and P
After ion implantation into the same area, a mask with a window only in the area where the guard ring is to be formed is attached to the substrate surface and annealing is performed. A ring is formed in one anneal.

In Japanese Patent Application No. 62-43567, a portion where Mg is ion-implanted,
A guard ring was formed with the portion where Mg was re-diffused by outward diffusion. However, later research showed that the light receiving part was Mg and P
It was found that the guard ring effect was sufficient only by outward diffusion of Mg when formed by ion implantation of This is the same regardless of the concentration of InP as long as the concentration is 10 ¹⁶ cm ⁻³ or less. In addition, since Mg and P are implanted into the same region, mask alignment only needs to be performed twice.

Furthermore, in the semiconductor element according to the present invention, the sub PN junction is formed shallower than the main PN junction and is made shallower than the depth of the first n-type layer, so that the withstand voltage is further improved and the guard ring is formed. Has a small effect on APD characteristics.
Therefore, the design of the guard ring can be ignored, and only the light receiving section can be optimally designed.

Embodiment An embodiment of the present invention applied to an InGaAs / InP APD will be described below with reference to FIG.

On the n-type InP substrate 1, the n-type InGaAs layer 2 is made to have a carrier concentration of 5 × 10 ¹⁵ cm ⁻³ and a layer thickness of 2 μm, and then the InGaAs layer 3 is made to have a carrier concentration of 8 × 10 ¹⁵ cm ⁻³ and a layer thickness of 0.3 μm. And even InP
Layer 4 is adjusted to a carrier concentration of 3 × 10 ¹⁶ cm ⁻³ and a layer thickness of 0.5 μm by using InP
The layer 5 is formed by sequentially laminating a carrier concentration of 8 × 10 ¹⁵ cm ⁻³ and a layer thickness of 0.6 μm (FIG. 1A). Next, an SiO ₂ film 6 serving as an ion implantation mask is deposited on the surface so as to have a film thickness of 8000 ° or more, and the mask is aligned to form an ion implantation window 7 having a diameter of 30 μm. Next, the ion implantation window 7
Mg and P through a dose of 1 × at an acceleration voltage of 150 KeV
10 ¹⁴ cm ^-2 and dose of 1 × 10 ^{14 at} 180 KeV acceleration voltage
Ions are implanted into cm ^-2 (FIG. 1 (b)). Next, a re-diffusion window 8 having a radius larger than that of the ion implantation window 7 by 5 μm is formed, and annealed at 750 ° C. for 35 minutes in a PH ₃ atmosphere to form a PN junction 9a of the light receiving portion and a PN junction 9b of the guard ring. It is formed (FIG. 1 (c)). Next, as in the manufacture of normal APD,
The InGaAs / InP APD is completed by mounting the passivation film 10, the P-side electrode 11p, and the N-side electrode 11n (FIG. 1 (d)).

A region in which Mg and P are implanted simultaneously, and Mg
FIG. 2 shows a comparison of the Mg profile after annealing with the region in which is diffused again. In the region where Mg and P are simultaneously implanted, Mg is steeply distributed from 10 ¹⁸ cm ^-3 or more to 10 ¹⁵ cm ^-3 or less, whereas Mg is re-diffused by out-diffusion. , Mg is gently distributed from 10 ¹⁶ cm ^-3 to 10 ¹⁵ cm ^-3 or less. Therefore, when the concentration of InP is 5 to 10 × 10 ¹⁵ c
If m− ³ , the PN junction 9b of the guard ring formed by re-diffusion of Mg is equivalent to the PN junction 9a of the light receiving unit, but forms a PN junction at a position shallower than that.

FIG. 3 shows the in-plane sensitivity distribution of the completed APD. It can be seen that the response at the guard ring portion is well suppressed, and multiplication occurs only at the light receiving portion. As described above, the effect of the present invention has been proved.

Note that the concentration and thickness of each growth layer, the Mg and P implantation conditions, the annealing conditions, and the like are not limited to those described above.
In particular, even if the concentration of the upper InP layer is 5 × 10 ¹⁵ cm ⁻³ or less, it functions effectively as an APD. However, at this time, the card ring is made deeper than the light receiving section,
One of the effects of the present invention of improving the degree of freedom in design is lost.

Further, the present invention is effective not only for InP but also for substrates having other compositions, and it is possible to apply impurities other than Mg and P without departing from the spirit of the present invention.

〔The invention's effect〕

According to the present invention, there is a remarkable advantage that an APD having a guard ring having a large effect can be easily manufactured with a small number of mask alignment steps. And this APD is a guard ring PN
Since the junction is formed shallower than the light receiving portion, there is an advantage that the degree of freedom in designing the light receiving portion is improved.

[Brief description of the drawings]

1 (a) to 1 (d) are sectional views showing a manufacturing method according to an embodiment of the present invention in the order of steps, FIG. 2 is a diagram showing a profile of Mg, and FIG. 3 is manufactured by the present invention. AP
FIG. 4 is a diagram showing an in-plane sensitivity distribution of D. 1 n-InP substrate, 2 n-InGaAs layer 3 n-InGaAsP layer 4, n-InP layer 5 n-InP layer, 9a PN junction of light-receiving part 9b guard PN junction of ring

Claims (2)

(57) [Claims] 1. A low-concentration first n-type layer and a high-concentration second n-type layer.
In the III-V compound semiconductor substrate in which the n-type layer is sequentially laminated from the surface side, Mg is from 10 ¹⁸ cm ^-3 or more to 10 ¹⁵ cm ^-3 or less from the surface side of the semiconductor substrate to the deep portion. A staircase-type main PN junction formed by a steeply distributed p-type layer and the base, and from the surface side of the semiconductor base to a depth of 10 ¹⁶ cm ⁻³ or more around the main PN junction around the main PN junction. 10 ¹⁵ cm ^-3
A step-type sub-PN junction formed by the p-type layer and the base, which are gently distributed to the base or lower, and
A semiconductor device, wherein the depth of the PN junction is smaller than the depth of the main PN junction, and the depth of the sub PN junction is smaller than the depth of the first n-type layer. 2. A step of forming an ion-implanted region by ion-implanting Mg and P into one region of a main surface of a III-V compound semiconductor substrate, and a step of forming a mask layer on the main surface. Providing an opening in the mask layer in a region wider than the ion-implanted region; and performing a heat treatment in a phosphorus atmosphere to form a main PN junction and a sub PN junction in the semiconductor substrate. A method of manufacturing a semiconductor device.