JPS61222139A - In alloy solder material for assembling semiconductor device having small residual thermal strain - Google Patents

In alloy solder material for assembling semiconductor device having small residual thermal strain

Info

Publication number
JPS61222139A
JPS61222139A JP6297785A JP6297785A JPS61222139A JP S61222139 A JPS61222139 A JP S61222139A JP 6297785 A JP6297785 A JP 6297785A JP 6297785 A JP6297785 A JP 6297785A JP S61222139 A JPS61222139 A JP S61222139A
Authority
JP
Japan
Prior art keywords
less
brazing
content
thermal strain
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6297785A
Other languages
Japanese (ja)
Inventor
Naoyuki Hosoda
細田　直之
Naoki Uchiyama
直樹 内山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Metal Corp
Original Assignee
Mitsubishi Metal Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Metal Corp filed Critical Mitsubishi Metal Corp
Priority to JP6297785A priority Critical patent/JPS61222139A/en
Publication of JPS61222139A publication Critical patent/JPS61222139A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To reduce residual thermal strain in a semiconductor element after brazing by containing 1-20wt% Ag and bringing oxygen content as an unavoidable impurity to 20ppm or less and the whole content of the unavoidable impurity to 50ppm or less. CONSTITUTION:An In alloy solder material has high creep deformability by bringing the content of Ag to 1-20wt%, the content of oxygen as an unavoidable impurity to 20ppm or less and the whole content of the unavoidable impurity to 50ppm or less. Accordingly, large differential thermal expansion between a semiconductor element and a lead frame generated on brazing on the assembly of a semiconductor device is absorbed sufficiently, thus remarkably reducing residual thermal strain in the semiconductor element after brazing.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置の組立て（アッセンブリー］に
用いられるろう材にかがり、特にＳｉなどの半導体素子
なＣｕ合戴などで形成されたリードフレームにろう付け
する際にろう材として用いるのに適したＩｎ合金ろう材
に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a brazing material used in the assembly of semiconductor devices, and particularly to a lead frame formed by combining Cu with a semiconductor element such as Si. The present invention relates to an In alloy brazing material suitable for use as a brazing material when brazing to.

〔従来の技術〕[Conventional technology]

従来、一般に、半導体装置としてトランジスタやＩＣ，
さらにＬＳ　Ｉ７ｉどが知られているが、この中で、例
えばＩＣは、 （ａ）　　まず、リードフレーム素材として板厚：０．
１〜０．３０を有する、例えばＱ合金の条材を用意し、 （ロ）　上記リードフレーム素材よりプレス打抜き加工
により製造せんとするＩＣの形状に適合したリードフレ
ームを形成し、 （０ついで、上記リードフレームの所定個所に　　　　
′高純度Ｓｔなどの半導体素子を、Ａｇペースドナどの
導電性樹脂を用いて加熱接着するか、あるいは上記半導
体素子をＡｕ−Ｓｉ合金ろう材などを介してリードフレ
ームの片面にろう付けし、 （イ）上記半導体素子と上記リードフレームとに渡って
Ａｕ極細線などによるワイヤボンディングを施し、 （ｅ）　　引続いて、上記半導体素子、結線、および半
導体素子が取付けられた部分のリードフレームを、これ
らを保護する目的で、プラスチックで封止し、 （Ｄ　最終的に、上記リードフレームにおける相互に連
なる部分を切除してＩＣを形成する、以上（ａ）〜（０
の主要工程によって製造されている。Conventionally, semiconductor devices generally include transistors, ICs,
Furthermore, LS I7i etc. are known, but among these, for example, IC is: (a) First, as a lead frame material, plate thickness: 0.
1 to 0.30, for example, a Q alloy strip, (b) form a lead frame suitable for the shape of the IC to be manufactured by press punching from the lead frame material, (0 then, At the specified location on the lead frame above.
'Semiconductor elements such as high-purity St are thermally bonded using conductive resin such as Ag paste or the above-mentioned semiconductor elements are brazed to one side of the lead frame via Au-Si alloy brazing material, etc. ) Wire bonding is performed using Au ultrafine wire or the like across the semiconductor element and the lead frame, (e) Subsequently, the semiconductor element, the wiring, and the lead frame in the area where the semiconductor element is attached are bonded. For the purpose of protection, the IC is sealed with plastic and (D) Finally, the interconnected parts of the lead frame are cut out to form an IC.
Manufactured using the following main processes.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このように半導体装置の製造に際し、半導体素子のリー
ドフレームへの接合に、ＡｇペーストやＡｕ−８ｉ合金
ろう材などが結合材として使用されているが、これらの
結合材は、加熱接合時にクリープ変形しに＜＜、かつ半
導体素子とリードフレームとの間には大′ｆ！な熱膨張
差があることと合まって、特に接合後の半導体素子には
大きな熱歪が残留するようになり、この結果半導体素子
に著しい反りが生じ、これが割れに発展する場合がしば
しば発生し、信頼性に問題のあるものである。さらに、
この傾向は、最近の６４ＫＤＲＡＭや２５６　ＫＤＲＡ
Ｍなどの超ＬＳＩなどの大型の半導体装置においては特
に顕著に現われるものである。In this way, when manufacturing semiconductor devices, Ag paste and Au-8i alloy brazing material are used as bonding materials to bond semiconductor elements to lead frames, but these bonding materials undergo creep deformation during heat bonding. However, there is a large distance between the semiconductor element and the lead frame. Combined with the large difference in thermal expansion, a large amount of thermal strain remains in the semiconductor device, especially after bonding, which often causes significant warpage in the semiconductor device, which often develops into cracks. , which has reliability problems. moreover,
This trend is reflected in the recent 64KDRAM and 256KDRAM.
This is particularly noticeable in large-sized semiconductor devices such as ultra-LSIs such as M.

〔問題点を解決するための手段〕[Means for solving problems]

そこで、本発明者等は、上述のような観点から、半導体
装置の製造に際し、半導体素子のリードフレームへのろ
う付けに適したろう材を開発すべく研究を行なつ几結果
、 Ａｇ：１〜２０重量％、 を含有し、残りがＩｎと不可避不純物からなる組成を有
し、かつ、 不可避不純物としての酸素含有量：２０ｐｐｍ以下、 不可避不純物の全含有量：５０ｐｐｍ以下、を満足する
Ｉｎ合金ろう材は、ろう付は時における半導体素子とリ
ードフレームの大きな熱膨張差を十分に吸収する高いク
リープ変形能を有し、したがって、このＩｎ合金ろう材
の使用によって、ろう付は後の半導体素子における残留
熱歪を著しく低減させることができるという知見を得た
のである。Therefore, from the above-mentioned viewpoint, the present inventors conducted research to develop a brazing filler metal suitable for brazing a semiconductor element to a lead frame when manufacturing a semiconductor device, and found that Ag: 1 to 20. % by weight, with the remainder being In and unavoidable impurities, and satisfying the following conditions: oxygen content as an unavoidable impurity: 20 ppm or less, total content of unavoidable impurities: 50 ppm or less The brazing material has a high creep deformability that can sufficiently absorb the large thermal expansion difference between the semiconductor element and the lead frame, and therefore, by using this In alloy brazing material, the brazing material has a high creep deformability that can sufficiently absorb the large thermal expansion difference between the semiconductor element and the lead frame. They found that thermal strain can be significantly reduced.

この発明は、上記知見にもとづいてなさｎたちのであり
、したがって、Ａｇめ含有量、酸素含有量、および不可
避不純物の全含有量が上記の範囲内にある場合に、ろう
材は高いクリープ変形能をもつようになるものであって
、これらのうちのいずれの成分でもこの発明の範囲を外
れると、所望のクリープ変形能を得ることができないば
かりでなく、接合強度や熱伝導性にも悪影響を及ぼ丁よ
うになることから、Ａｇの含有量を１〜２０重量％、不
可避不純物としての酸素含有量を２０ｐｐｍ以下、そし
て不可避不純物の全含有量を５０ｐｐｍ以下と定めたの
である。This invention was made based on the above findings, and therefore, when the Ag content, oxygen content, and total content of unavoidable impurities are within the above ranges, the brazing filler metal has a high creep deformability. If any of these components is outside the scope of the present invention, not only will it be impossible to obtain the desired creep deformability, but also the joint strength and thermal conductivity will be adversely affected. Therefore, the content of Ag was determined to be 1 to 20% by weight, the content of oxygen as an unavoidable impurity was determined to be 20 ppm or less, and the total content of unavoidable impurities was determined to be 50 ppm or less.

〔実施例〕〔Example〕

つぎに、この発明のＩｎ合笠ろう材を実施例により具体
的に説明する。Next, the In-gagasa brazing filler metal of the present invention will be specifically explained with reference to Examples.

通常の真空溶解炉を用い、それぞれ第１表に示される成
分組成をもった溶湯を調製し、インゴットに鋳造し、圧
延加工を施すことによって、幅＝１　ｕｓ　Ｘ厚さ：０
．１ｍの寸法をもったリボン状の本発明Ｉｎ合金ろう材
１〜６および比較Ｉｎ合金ろう材（＊印：本発明範囲外
〕 第　　１　　茨 １〜６をそれぞれ製造した。Using an ordinary vacuum melting furnace, prepare molten metals having the compositions shown in Table 1, cast them into ingots, and roll them to obtain a width of 1 us x thickness of 0.
．． Ribbon-shaped In alloy brazing materials 1 to 6 of the present invention and comparative In alloy brazing materials (marked with *: outside the scope of the present invention) having a size of 1 m were manufactured, respectively.

なお、比較Ｉｎ合金ろう材１〜６は、いずれも酸素含有
量または不可避不純物の全含有量がこの発明の範囲から
外れて多く含有するものである。The comparative In alloy brazing materials 1 to 6 all contain a large amount of oxygen or a total amount of unavoidable impurities outside the scope of the present invention.

ついで、この結果得られた本発明Ｉｎ合金ろう材１〜６
および比較Ｉｎｉ金ろう材１〜６を用い、平面：　５　
ｘｘ　Ｘ　６　ｌ１ｌ）厚さ：０．３ｍの寸法をもった
半導体素子としてのＳｉチップを、々メッキされたＣｕ
合蛍（ＣＤＡ１９４）製リードフレームにろう付けし、
ろう付は後の前記Ｓｉチップの上面に発生した反りを表
面粗さ計により測定し友。この測定結果を第１表に合せ
て示し友。Next, the resulting In alloy brazing materials 1 to 6 of the present invention
and comparative Ini gold brazing filler metals 1 to 6, plane: 5
xx
Brazed to a lead frame made by Goho (CDA194),
After brazing, the warpage that occurred on the top surface of the Si chip was measured using a surface roughness meter. The measurement results are shown in Table 1.

〔発明の効果〕 第１弐に示されるように、本発明Ｉｎｉ並ろう材１〜Ｇ
を用い几場合には、Ｓｉチップに発生する反Ｖはいずれ
も５μｍ以下であり、この程度の反フならば実用上何ら
問題のないものである。これに対して、比較Ｉｎ合金ろ
う゛材１〜６に見られるように、酸素含有量ま友は不可
避不純物全量がこの発明の範囲を越えて多いと、反りの
発生が著しくなシ、いずれの場合もＳｉチップの残留熱
歪は大きなものとなることから、使用中にＳｉチップに
割れが発生したシ、さらに接合強度および熱放散性も劣
るようになるものであった。[Effects of the invention] As shown in No. 12, the Ini-line brazing filler metals 1 to G of the present invention
When the Si chip is used, the anti-V generated in the Si chip is all 5 μm or less, and this level of anti-V causes no problem in practice. On the other hand, as seen in Comparative In alloy brazing materials 1 to 6, when the oxygen content and the total amount of unavoidable impurities exceed the scope of this invention, warpage occurs significantly. In this case, the residual thermal strain of the Si chip was also large, resulting in cracks occurring in the Si chip during use, and furthermore, the bonding strength and heat dissipation properties became poor.

上述のように、この発明のＩｎ合金ろう材は、高いクリ
ープ変形能を有するので、半導体装置の組立てに際して
、ろう付は時に発生する半導体素子とリードフレーム間
の大きな熱膨張差を十分に吸収し、この結果ろう付は後
の半導体素子における残留熱歪が著しく低くなるので、
これに発生する反りがきわめて少なく、割れ発生が皆無
となるばかりでなく、接合強度および熱伝導性にも丁ぐ
れていることから、信頼性の高い半導体装置の製造を可
能とするものである。As mentioned above, the In alloy brazing material of the present invention has high creep deformability, so when assembling semiconductor devices, brazing can sufficiently absorb the large thermal expansion difference that sometimes occurs between the semiconductor element and the lead frame. As a result, brazing significantly lowers the residual thermal strain in the subsequent semiconductor device.
Not only is there very little warpage and no cracking, but the bonding strength and thermal conductivity are also excellent, making it possible to manufacture highly reliable semiconductor devices.

Claims (1)

【特許請求の範囲】 Ａｇ；１〜２０重量％、 を含有し、残りがＩｎと不可避不純物からなる組成を有
し、かつ、 不可避不純物としての酸素含有量：２０ｐｐｍ以下、 不可避不純物の全含有量：５０ｐｐｍ以下、を満足する
ことを特徴とする残留熱歪の少ない半導体装置の組立て
用Ｉｎ合金ろう材。[Claims] Contains Ag: 1 to 20% by weight, the remainder is In and unavoidable impurities, and: Oxygen content as an unavoidable impurity: 20 ppm or less, Total content of unavoidable impurities : 50 ppm or less. An In alloy brazing filler metal for assembling semiconductor devices with little residual thermal strain.
JP6297785A 1985-03-27 1985-03-27 In alloy solder material for assembling semiconductor device having small residual thermal strain Pending JPS61222139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6297785A JPS61222139A (en) 1985-03-27 1985-03-27 In alloy solder material for assembling semiconductor device having small residual thermal strain

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6297785A JPS61222139A (en) 1985-03-27 1985-03-27 In alloy solder material for assembling semiconductor device having small residual thermal strain

Publications (1)

Publication Number Publication Date
JPS61222139A true JPS61222139A (en) 1986-10-02

Family

ID=13215923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6297785A Pending JPS61222139A (en) 1985-03-27 1985-03-27 In alloy solder material for assembling semiconductor device having small residual thermal strain

Country Status (1)

Country Link
JP (1) JPS61222139A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4976529A (en) * 1988-04-28 1990-12-11 Sigma Co., Ltd. Soldering material for spectacle frame and spectacle frame in which said soldering material is used
JP2013233577A (en) * 2012-05-10 2013-11-21 Sumitomo Metal Mining Co Ltd Pb FREE In SOLDER ALLOY

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4976529A (en) * 1988-04-28 1990-12-11 Sigma Co., Ltd. Soldering material for spectacle frame and spectacle frame in which said soldering material is used
JP2013233577A (en) * 2012-05-10 2013-11-21 Sumitomo Metal Mining Co Ltd Pb FREE In SOLDER ALLOY

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