JPS61196598A - Electronic component mounting structure - Google Patents

Electronic component mounting structure

Info

Publication number
JPS61196598A
JPS61196598A JP3793485A JP3793485A JPS61196598A JP S61196598 A JPS61196598 A JP S61196598A JP 3793485 A JP3793485 A JP 3793485A JP 3793485 A JP3793485 A JP 3793485A JP S61196598 A JPS61196598 A JP S61196598A
Authority
JP
Japan
Prior art keywords
electronic component
tin
brazing material
alloy
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3793485A
Other languages
Japanese (ja)
Other versions
JPH06105828B2 (en
Inventor
義博 細井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP3793485A priority Critical patent/JPH06105828B2/en
Publication of JPS61196598A publication Critical patent/JPS61196598A/en
Publication of JPH06105828B2 publication Critical patent/JPH06105828B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子部品の回路配線部材への実装構造に関し、
よシ詳細には両端に導通用電極を有するチップ型電子部
品を回路配線部材に実装するための構造に関するもので
あるう 〔従来の技術〕 近時、情報処理装置の高性能化、高速度化に伴ない、こ
れを構成する半導体素子も高密度、高集積化が急激に進
んでおり、これら半導体素子を回路基板や半導体パッケ
ージに搭載収納した場合、回路基板や半導体パッケージ
が有する回路配線間の容量や各配線導体の抵抗値のバラ
ツキが問題となり、半導体素子を誤動作させるという欠
点を有していた。そのため従来は回路基板や半導体バク
ケージ内に少なくとも二つの導通用電極を有するチップ
型の容量素子や抵抗素子を半田や金とケイ素あるいは金
とゲルマニウムから成るロウ材を介して取着し、半導体
パッケージ等の回路配線間の容量や各配線導体の抵抗値
を調整していた。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a mounting structure for electronic components on circuit wiring members,
More specifically, it relates to a structure for mounting a chip-type electronic component having conduction electrodes at both ends on a circuit wiring member. [Prior art] In recent years, information processing devices have been increasing in performance and speed. Along with this, the semiconductor elements that make up these devices are rapidly becoming denser and more highly integrated. Variations in capacitance and resistance values of each wiring conductor became a problem, and the semiconductor device had the disadvantage of causing malfunction. For this reason, conventionally, a chip-type capacitive element or resistive element having at least two conductive electrodes is attached to a circuit board or a semiconductor back cage through solder or a brazing material made of gold and silicon or gold and germanium, and semiconductor packages and the like are used. The capacitance between the circuit wiring and the resistance value of each wiring conductor were adjusted.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、この従来の容量素子等チップ型電子部品
の実装においては半田の融点が183℃と低ぐ、前記チ
ップ型電子部品を半導体パッケージの内部に実装する場
合、半導体バクケージの内部を気密封止する際のシール
温度(約350℃)や半導体素子を半導体パッケージに
取着する際のダイポンディング温度(約370℃)が高
いことから半田は溶融流出してしまい、その結果チップ
型電子部品の取着位置にズレや、取着強度に低下を生じ
チップ型電子部品の離脱事故を発生するという問題があ
る。また半田中の鉛はアルファカウントが高いため、メ
モリーなどの半導体素子はアルファ線の影響を受は易く
、該アルファ線によって誤動作するという欠点もある。
However, in the conventional mounting of chip-type electronic components such as capacitive elements, the melting point of the solder is as low as 183°C, and when the chip-type electronic components are mounted inside a semiconductor package, the inside of the semiconductor back cage must be hermetically sealed. Due to the high sealing temperature (approximately 350 degrees Celsius) and the high die bonding temperature (approximately 370 degrees Celsius) when attaching semiconductor elements to semiconductor packages, the solder melts and flows out, resulting in poor attachment of chip-type electronic components. There is a problem in that the chip-type electronic component may come off due to misalignment or a decrease in attachment strength. Furthermore, since the lead in the solder has a high alpha count, semiconductor devices such as memories are easily affected by alpha rays, and there is also the drawback that they may malfunction due to the alpha rays.

また一方、金とケイ素あるいは金とゲルマニウムとの合
金を用いて取着する場合、この合金の融点は356℃〜
370℃と高いこと、および硬度が高い(ブリネル硬さ
:60〜120 )ことから、半導体パッケージの内部
を気密封止する際等において合金に高温が印加されたと
しても、該合金は溶融流出することなくチップ型電子部
品を所望する個所に正確に取着することができるものの
、チップ型電子部品は回路配線部材に約300℃の高温
域で固定されることとなり、そのためチップ型電子部品
の常温への冷却(300℃→20℃)においてチップ型
電子部品と回路配線部材との熱収縮率の相違に伴ない、
チップ型電子部品に極めて大きな熱応力が発生してしま
い、その結果、チップ型電子部品にクラックや割れを発
生してしまうという欠点がある。
On the other hand, when an alloy of gold and silicon or gold and germanium is used for attachment, the melting point of this alloy is 356 °C ~
Because it is as high as 370°C and has high hardness (Brinell hardness: 60 to 120), even if high temperatures are applied to the alloy when hermetically sealing the inside of a semiconductor package, the alloy will melt and flow out. Although it is possible to accurately attach chip-type electronic components to the desired location without any heat loss, chip-type electronic components must be fixed to circuit wiring members at a high temperature range of approximately 300°C. Due to the difference in thermal contraction rate between chip-type electronic components and circuit wiring members when cooling to (300℃→20℃),
This has the disadvantage that extremely large thermal stress is generated in the chip-type electronic component, resulting in cracks and fractures in the chip-type electronic component.

〔発明の目的〕[Purpose of the invention]

本発明者は上記欠点に鑑み種々の実験の結果、少なくと
も二つの導通用電極を有するチップ型電子部品を回路配
線部材に対し、一つの電極は高融点の合金、すなわちゲ
ルマニウム、ケイ素および錫のうちの一種と金との合金
(融点280℃〜370℃)から成る第1ロウ材を介し
、その他の電極は錫もしくは錫と銀との合金から成る第
2ロウ材を介し取着すると、凝固に際し、先づ融点の高
い第1ロウ材が高温域で凝固してチップ型電子部品の一
つの電極が固定され、次いで融点の低い軟質な第2ロウ
材が凝固し、他の電極が固定されることがら熱収縮率の
相違に伴ない発生する熱応力を吸収すると共に極めて小
さなものとなすことから、チップ型電子部品を離脱事故
やアルファ線およびクラックの問題を皆無として所望個
所に正確に取着し得ることを知見した。
In view of the above-mentioned drawbacks, the present inventor conducted various experiments and found that a chip-type electronic component having at least two conductive electrodes is used as a circuit wiring member, and one electrode is made of a high melting point alloy, that is, one of germanium, silicon, and tin. When the other electrodes are attached through a first brazing material made of an alloy of one type of and gold (melting point 280°C to 370°C) and a second brazing material made of tin or an alloy of tin and silver, the First, the first brazing material with a high melting point solidifies in a high temperature range to fix one electrode of the chip-type electronic component, and then the soft second brazing material with a low melting point solidifies and fixes the other electrodes. Since it absorbs the thermal stress that occurs due to the difference in thermal shrinkage rate and makes it extremely small, it is possible to accurately attach chip-type electronic components to the desired location without any problems such as detachment accidents, alpha rays, and cracks. I found out that it is possible.

本発明は上記知見に基づき、チップ型電子部品にクラッ
クや割れ等を発生することなく半導体パッケージや回路
基板等、回路配線部材の所望個所に正確かつ強固に取s
I実装することができる電子部品の実装構造を提供する
ことをその目的とするものである。
Based on the above findings, the present invention is capable of accurately and firmly attaching chip-type electronic components to desired locations on circuit wiring members such as semiconductor packages and circuit boards without causing cracks or cracks.
The purpose is to provide a mounting structure for electronic components that can be mounted.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の電子部品の実装構造は、少なくとも二つの導通
用電極を有するチップ型電子部品を回路配線部材に、一
つの電極はゲルマニウム、ケイ素及び錫のうちの一種と
金との合金から成る第1ロウ材を介し、その他の電極は
錫もしくは錫と銀との合金から成る第2ロウ材を介し取
着することを特徴とするものである。
In the electronic component mounting structure of the present invention, a chip-type electronic component having at least two conductive electrodes is used as a circuit wiring member, and one electrode is a first electrode made of an alloy of gold and one of germanium, silicon, and tin. The other electrodes are attached via a second brazing material made of tin or an alloy of tin and silver.

本発明の電子部品の実装構造においては、少なくとも二
つの導通用電極を有する電子部品の一つの電Wiをゲル
マニウム、ケイ素および錫のうちの一種と金との合金か
ら成る第1ロウ材を介し、その他の電極を錫もしくは錫
と銀との合金から成る第2ロウ材を介し回路配線部材に
取着するものであり、第1ロウ材であるゲルマニウム、
ケイ素及び錫のうちの一種と金との合金は融点が280
’C〜370℃と高く、半導体パッケージを気密封止す
る際のシー/’/M度(約350℃)や半導体素子を取
着する際のダイポンディング温度(約370℃)におい
ても溶融流出することがなく、チップ型電子部品の一部
を回路配線部材に強固に取着し、該電子部品の取着位置
にズレが発生するのを有効に防止する。また、錫もしく
は錫と銀との合金は融点が221℃〜232℃と低く、
かつ軟質(ブリネル硬さ:15〜80)な材料であるこ
とから凝固するに際し、チップ型電子部品と回路配線部
材との間の熱収縮率の相違に伴ない発生する応力を吸収
し、極めて小さなものとなすことができ、チップ型電子
部品にクラックや割れ等を発生することもない。
In the electronic component mounting structure of the present invention, one electric current Wi of an electronic component having at least two conductive electrodes is connected through a first brazing material made of an alloy of gold and one of germanium, silicon, and tin. Other electrodes are attached to the circuit wiring member through a second brazing material made of tin or an alloy of tin and silver, and the first brazing material is germanium,
An alloy of silicon and one of tin and gold has a melting point of 280
It is as high as 'C~370℃, and melts and flows out even at C/'/M degrees (approximately 350℃) when hermetically sealing a semiconductor package and die bonding temperature (approximately 370℃) when attaching semiconductor elements. To firmly attach a part of a chip-type electronic component to a circuit wiring member without causing any problems, and to effectively prevent the electronic component from being misaligned in the attachment position. Furthermore, tin or an alloy of tin and silver has a low melting point of 221°C to 232°C.
Since it is a soft material (Brinell hardness: 15 to 80), when it solidifies, it absorbs the stress that occurs due to the difference in thermal contraction rate between chip-type electronic components and circuit wiring components, and has an extremely small The chip type electronic components do not suffer from cracks or cracks.

更には前記第1ロウ材及び第2ロウ材はそれを構成する
成分がいずれもアルファーカウントが低いため、メモリ
ーなどの半導体素子に対するアルファ線の悪影響は極め
て少なく、半導体素子を誤動作させることもない。
Furthermore, since the constituent components of the first brazing material and the second brazing material both have a low alpha count, the adverse effects of alpha rays on semiconductor devices such as memories are extremely small, and the semiconductor devices will not malfunction.

また本発明の電子部品の実装構造において使用、される
第1ロウ材はゲルマニウムがLO重−1満、ケイ素が0
.5重量%未満あるいは錫が10.0重量%未満ではロ
ウ材の融点が高く、一般の取着温度(500℃以下)で
は溶融が不完全で流れ性が悪いため、取着強度が弱い傾
向にあシ、一方ゲ〃マニウムが12.0重量%、ケイ素
が6.0重量%あるいは錫が30.0重量%を超えると
ロウ材が硬くもろくなることから衝撃試験等の評価試験
後の取着強度の劣化が著しい傾向にある。そのため、第
1ロウ材としてはゲルマニウムが1.0−12.0重量
%、ケイ素が0.5〜6.0重量%、錫が10.0〜3
0.0重量%にすることが好ましい。
In addition, the first brazing material used in the electronic component mounting structure of the present invention contains germanium with an LO weight of less than -1 and silicon with an LO weight of less than -1.
.. If the content of tin is less than 5% by weight or less than 10.0% by weight, the melting point of the brazing material will be high, and at normal bonding temperatures (below 500°C), melting will be incomplete and flowability will be poor, resulting in weak bonding strength. On the other hand, if the content exceeds 12.0% by weight of germanium, 6.0% by weight of silicon, or 30.0% by weight of tin, the brazing material becomes hard and brittle, so it must be installed after evaluation tests such as impact tests. Strength tends to deteriorate significantly. Therefore, as the first brazing material, germanium is 1.0-12.0% by weight, silicon is 0.5-6.0% by weight, and tin is 10.0-3% by weight.
The content is preferably 0.0% by weight.

また第2ロウ材は錫と銀との合金から成る場合、銀が1
0.0選量%を超えると融点が高くなり、第】ロウ材の
融点と近似するため、チップ型電子部品にクラックや割
れ等を発生する傾向にある。そのため、第2ロウ材が錫
と銀との合金から成る場合は、銀が0〜10.0重量%
にすることが好ましい。
In addition, when the second brazing filler metal is made of an alloy of tin and silver, silver is
If the amount exceeds 0.0%, the melting point becomes high and approximates that of the brazing filler metal, which tends to cause cracks and cracks in chip-type electronic components. Therefore, when the second brazing material is made of an alloy of tin and silver, the silver content is 0 to 10.0% by weight.
It is preferable to

〔実施例〕〔Example〕

次に本発明を実施例に基づき説明する。 Next, the present invention will be explained based on examples.

出発原料として金、ゲルマニウム、ケイ素、錫および銀
を下表に示す組成となる様に秤量するとともに、小型溶
解炉にて真空またはアルゴン雰囲気中で溶解し合金を作
製した。次にこの合金を小型圧延機にて圧延し、厚さZ
oo amの薄板と咬すとともに、長さ12 mm巾2
.Ommに切断し、第1ロウ材及び第2ロウ材の試料を
作製した。そして次に、表面にタングステンメタフィズ
パッドヲ有スる基板上にE工M規格(RC−3402)
cc −73−3−FIE224Z相当のチップ型セラ
ミックコンデンサ50個を導通用電極に前記第1ロウ材
及び第2ロウ材を介して載置させるとともに450℃に
加熱して取着固定した。次いで前記チップ型セラミック
コンデンサを取着した基板を一旦350℃(ハーメチッ
クシー〜の条件)に加熱し、その後−65℃から150
℃の温度サイクμを10サイク〜、さらK 8000 
Gの衝撃試験を10サイクル行なってチップ型セラミッ
クコンデンサの断面を顧漱鏡で観察し、クラック及び割
れの発生数を調べた。また同時にチップ型セラミックコ
ンデンサを基板に取着直後及び熱サイクル試験等を行な
った後に、横方向から押圧し、その取着強度を測定した
。なお、基板表面のタングステンメタライズパッド上に
は第1ロウ材及び第2ロウ材の濡れ性を容易とするため
のニッケルめっき及び金めつきが施こしである。また試
料番号31 、32.33は本発明品と比較するための
比較試料であり、試料番号31は従来周知の半田、32
は金−シリコン(Au−8i)、33は金−ゲルマニウ
ム(Au−Ge)である。上記の結果を下表に示す。
Gold, germanium, silicon, tin, and silver were weighed as starting materials to give the compositions shown in the table below, and were melted in a small melting furnace in vacuum or in an argon atmosphere to produce an alloy. Next, this alloy is rolled in a small rolling mill to a thickness of Z
oo am's thin plate and length 12 mm width 2
.. Samples of the first brazing material and the second brazing material were prepared by cutting to a size of 0 mm. Next, the E-Engineering Standard (RC-3402) was applied to the substrate with a tungsten metallurgical pad on the surface.
Fifty chip-type ceramic capacitors equivalent to cc-73-3-FIE224Z were placed on the conductive electrode via the first brazing material and the second brazing material, and were attached and fixed by heating to 450°C. Next, the board on which the chip-type ceramic capacitor was attached was heated once to 350°C (hermetic sea conditions), and then heated from -65°C to 150°C.
Temperature cycle μ of ℃ 10 cycles ~, further K 8000
A G impact test was conducted for 10 cycles, and the cross section of the chip-type ceramic capacitor was observed with a mirror to determine the number of cracks and breaks. At the same time, immediately after attaching the chip-type ceramic capacitor to the substrate and after performing a thermal cycle test, etc., the bonding strength was measured by pressing from the side. Note that nickel plating and gold plating are applied on the tungsten metallized pad on the surface of the substrate to facilitate the wettability of the first brazing material and the second brazing material. Sample numbers 31 and 32.33 are comparative samples for comparison with the products of the present invention, and sample number 31 is a conventionally well-known solder, 32.
33 is gold-silicon (Au-8i), and 33 is gold-germanium (Au-Ge). The above results are shown in the table below.

〔発明の効果〕〔Effect of the invention〕

従来周知の半田、Au−81,Au−Geで取着したも
のは取着強度が電子部品の取着直後で6.4 kg以下
、熱サイクル試験後で3.8 kg以下であり、かつク
ラックの発生率が26%(試料番号32)もあるのに対
し、本発明品は取着直後で7.7kg以上、熱サイクル
試験後で6.8 kg以上あり、かつ電子部品における
クラック及び割れの発生も皆無である。
The bonding strength of conventional solders such as Au-81 and Au-Ge was 6.4 kg or less immediately after the electronic components were attached, and 3.8 kg or less after a thermal cycle test, and there were no cracks. In contrast, the product of the present invention weighs more than 7.7 kg immediately after installation and more than 6.8 kg after the thermal cycle test, and is free from cracks and cracks in electronic components. There have been no outbreaks.

特に第1ロウ材がAu −Siの合金から成る場合、シ
リコンの量を1.0〜4.0重量%、Au−Geの合金
から成る場合、ゲルマニウムの量が3.0〜10.0 
 重の取着強度が熱サイクル試験後においても8.2k
g以上もあり、かつ電子部品のクラック及び割れも皆無
であることから、第1ロウ材を上記範囲にすることがよ
り望ましい。また第2ロウ材が錫−銀(Sn −Ag 
)の合金から成る場合、銀の竜を1.0〜7.0重量%
の際には電子部品の取着強度も熱サイクル試倹後で7.
2kg以上もあり、かつ電子部品のクラック及び割れも
皆無であることから、第2ロウ材を上記範囲にすること
がよシ望ましい。従って本発明の電子部品の実装構造に
おいては、電子部品にクラックや割れ等を発生すること
なく、回路配線部材に極めて強固にかつ所望する位置に
実装することができ、極めて有用である。
In particular, when the first brazing material is made of an Au-Si alloy, the amount of silicon is 1.0 to 4.0% by weight, and when it is made of an Au-Ge alloy, the amount of germanium is 3.0 to 10.0% by weight.
Heavy attachment strength is 8.2k even after thermal cycle test
g or more, and there are no cracks or cracks in the electronic parts, so it is more desirable to have the first brazing material in the above range. Further, the second brazing material is tin-silver (Sn-Ag).
), 1.0 to 7.0% by weight of silver dragon
In this case, the mounting strength of electronic components is also 7. after thermal cycle testing.
Since it weighs more than 2 kg and there are no cracks or breaks in the electronic component, it is desirable that the second brazing material be within the above range. Therefore, the electronic component mounting structure of the present invention is extremely useful because it can be mounted extremely firmly on a circuit wiring member at a desired position without causing any cracks or breaks in the electronic component.

Claims (1)

【特許請求の範囲】 1、少なくとも二つの電極を有するチップ型電子部品を
回路配線部材に対し、一つの電極はゲルマニウム、ケイ
素及び錫のうちの一種と金との合金から成る第1ロウ材
を介し、その他の電極は錫もしくは錫と銀との合金から
成る第2ロウ材を介し取着することを特徴とする電子部
品の実装構造。 2、前記第1ロウ材は、1.0〜12.0重量%のゲル
マニウム、0.5〜6.0重量%のケイ素及び10.0
〜30.0重量%の錫のうちの一種と残部が金の合金か
ら成ることを特徴とする特許請求の範囲第1項記載の電
子部品の実装構造。 3、前記第2ロウ材は、錫もしくは0〜10.0重量%
の銀と残部が錫の合金から成ることを特徴とする特許請
求の範囲第1項記載の電子部品の実装構造。
[Scope of Claims] 1. A chip-type electronic component having at least two electrodes is connected to a circuit wiring member, and one electrode is made of a first brazing material made of an alloy of gold and one of germanium, silicon, and tin. An electronic component mounting structure characterized in that the other electrodes are attached via a second brazing material made of tin or an alloy of tin and silver. 2. The first brazing material contains 1.0 to 12.0% by weight of germanium, 0.5 to 6.0% by weight of silicon, and 10.0% by weight of silicon.
2. The electronic component mounting structure according to claim 1, wherein the electronic component mounting structure is made of an alloy of at least 30.0% by weight of one kind of tin and the balance of gold. 3. The second brazing material contains tin or 0 to 10.0% by weight
2. The electronic component mounting structure according to claim 1, wherein the electronic component mounting structure is made of an alloy of silver and tin.
JP3793485A 1985-02-26 1985-02-26 Electronic component mounting structure Expired - Lifetime JPH06105828B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3793485A JPH06105828B2 (en) 1985-02-26 1985-02-26 Electronic component mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3793485A JPH06105828B2 (en) 1985-02-26 1985-02-26 Electronic component mounting structure

Publications (2)

Publication Number Publication Date
JPS61196598A true JPS61196598A (en) 1986-08-30
JPH06105828B2 JPH06105828B2 (en) 1994-12-21

Family

ID=12511385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3793485A Expired - Lifetime JPH06105828B2 (en) 1985-02-26 1985-02-26 Electronic component mounting structure

Country Status (1)

Country Link
JP (1) JPH06105828B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06169160A (en) * 1991-03-22 1994-06-14 Tokai Rika Co Ltd Solder joint structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06169160A (en) * 1991-03-22 1994-06-14 Tokai Rika Co Ltd Solder joint structure

Also Published As

Publication number Publication date
JPH06105828B2 (en) 1994-12-21

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