JPS61218227A - Divided pulse sending circuit - Google Patents

Abstract

PURPOSE:To absorb a timing error of a pulse signal before and after stopping by providing an up-down counter, a decoder and a reset circuit. CONSTITUTION:In selecting an output pulse from a waveform shaping circuit 3 when a DC motor 1 is driven, e.g., clockwise as a '+' pulse signal, the output pulse from the circuit 3 when the DC motor 1 is driven counter clockwise is a '-' direction pulse signal, and pulse numbers are added or subtracted by inputting the said direction signals respectively to an up terminal 62 or a down terminal 63 of a counter 6. When a binary code outputted from the counter 6 subject to addition or subtraction is coincident with a binary code present in a decoder 7, a pulse signal is outputted from the decoder 7, an output level of a monostable multivibrator 81 is inverted and a pulse signal is outputted via a NAND circuit 82, an output level of a monostable multivibrator 83 is inverted to reset the counter 6 and the binary code outputted from the counter restores to 0.

Description

[Detailed Description of the Invention] [Summary] This is a circuit that divides the output pulse of an encoder directly connected to a motor to 1/N and sends it out, and it is used to divide the output pulse of an encoder directly connected to a motor and send it out. This circuit has the function of absorbing the timing error of the divide pulse before and after.

[Industrial application field]

The present invention relates to a pattern recognition device, and more particularly to a divide pulse sending circuit that sends out a pulse that moves the relative position of a detection head and a pattern to be measured and serves as a reference for calculating a distance from the amount of rotation of an electric motor.

Keyboards, which are used as manual devices for various electronic devices, are visible to an unspecified number of people including operators, and information input is displayed on the key tops inserted into each push button switch that makes up the keyboard. This is done based on the characters and symbols that exist. Therefore, it is absolutely unacceptable to have a different arrangement of the key tops, which are the basis for inputting information. However, the arrangement of characters and symbols displayed on the key tops differs depending on the keyboard model, and at the same time, the size, font, line thickness, etc. of the characters and symbols also differ depending on the keyboard model.

Therefore, pattern recognition equipment is used in the keyboard manufacturing process to inspect the arrangement of characters and symbols on each keyboard, but if a defect is detected during the inspection, the inspection is stopped and the defect location and details are displayed. Methods have been adopted, such as performing a test and restarting the test to continue the next test.

However, the moving stage on which the detection head or pattern to be measured is mounted and the electric motor that moves it are connected via a transmission mechanism such as a belt, and information from the detection head is transmitted according to the output pulses of an encoder directly connected to the electric motor. Output. In a device with such a transmission mechanism, once the electric motor is stopped, the electric motor will rotate in the opposite direction due to the tension of the belt, etc., and even if the electric motor is restarted, the stage will not move until the tension of the belt, etc. is restored. Not done. However, a pulse signal is output from the encoder, and if information is output from the detection head due to the pulse signal during this period, a shift occurs in the dimming for outputting the information.

Therefore, a pattern recognition device having such a power transmission mechanism must have a function to absorb timing errors in pulse signals before and after stopping, which occur when the electric motor is stopped midway and restarted.

[Conventional technology]

FIG. 3 is a circuit diagram showing an example of a conventional divide pulse sending circuit.

In the figure, output pulses from an encoder 2 directly connected to a DC motor 1 are shaped by a waveform shaping circuit 3 and input to a counter 5 via an OR circuit 4. A divide condition is set in the counter 5, and the counter 5 outputs a divide pulse according to the set divide condition. For example, if the divide condition is N-3, 3 is input to the counter 5.
One divide pulse is output from the counter 5 for each pulse signal.

[Problem that the invention seeks to solve]

In the conventional divided pulse sending circuit, the pulse signals output from the encoder are added by a counter regardless of the rotational direction of the DC motor.

Therefore, the pulse signal output from the encoder during the period when the DC motor that stopped midway rotates in the opposite direction due to the tension of the belt, etc. and the tension of the belt, etc. is restored by restarting is also added by the counter and the divided pulse is Output. That is, there is a problem in that an error occurs in the timing of the divide pulse before and after the stop.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of a divided pulse sending circuit according to the present invention.

The above problem is that the up/down counter (hereinafter referred to as counter) 6 outputs a binary code when a pulse signal is input, and the binary code input from the counter 6 is
The problem is solved by the divided pulse sending circuit of the present invention, which includes a decoder 7 that outputs a pulse signal when it matches a preset binary code, and a reset circuit 8 that resets the counter 6 using the pulse signal output from the decoder 7. be done.

[Effect]

In FIG. 1, a pulse signal in the (+) direction and a pulse signal in the (-) direction are input to the counter 6. When a pulse signal in the (+) direction is input, it is added by the up counter, and the added pulse is The number is output in binary code. Then, for example, divide condition N=3 is applied to the decoder 7.
A binary code indicating this is set in advance, and when three pulse signals in the (+) direction are input to the counter 6, a pulse signal is output from the decoder 7 to the outside via the reset circuit 8, and a reset is performed. The counter 6 is reset by the circuit 8.

On the other hand, when a pulse signal in the (-) direction is input, it is subtracted from the number of pulses up to that point by a down counter, and the subtracted number of pulses is output as a binary code. For example, use a 24-base counter as counter 6, input 2 pulses in the (+) direction, and then input 10 pulses in the (-) direction.
If N = 3 is input, the binary code output from the counter 6 becomes a code representing 8, which does not match the binary code representing N = 3 set in advance in the decoder 7, and the pulse signal from the decoder 7 is It is never output. Therefore, the counter 6 is not reset during that time.

When a pulse signal in the (+) direction is input again from this state, it is added up by the amplifier counter, and the added number of pulses is output as a binary code. However, the initial value is 8
The decoder 7 will not output a pulse signal until 11 pulse signals in the (+) direction are input. That is, after returning to the state before the (-) direction pulse signal was input, the addition of the (+) direction pulse signal starts again from that point, and the binary code output from the counter 6 is set in the decoder 7 in advance. If it matches the binary code indicating N=3, the decoder 7
A pulse signal is outputted to the outside via the reset circuit 8, and the counter 6 is reset by the reset circuit 8.

Therefore, by using such a divided pulse sending circuit, a DC motor that has stopped midway rotates in the opposite direction due to the tension of the belt, etc., and a pulse signal is output from the encoder until the tension of the belt, etc. is restored by restarting. Even if the pulse number is stopped, the counter can accurately add and subtract the number of pulses, and it is possible to eliminate the timing error of the divide pulse that occurs before and after the stop.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 2 is a circuit diagram showing an embodiment of the divided pulse sending circuit according to the present invention, and the same objects are represented by the same symbols throughout the figures.

In the figure, output pulses from an encoder 2 directly connected to a DC motor 1 are shaped by a waveform shaping circuit 3 and input to a divide pulse sending circuit. The divide pulse sending circuit is 24
It is equipped with a decimal counter 6, a decoder 7, and a reset circuit 8,
Output terminals QA, QB, QCSQ of 24-decimal counter 6
D are connected to input terminals A, B, C, and D of the decoder 7, respectively. In addition, the reset circuit 8 is a monostable multipipe rake (hereinafter referred to as monostable multi) 81 and a NAND
It consists of a pulse signal output section consisting of a circuit 82 and a reset signal output section consisting of a monostable multi 83 and a NOR circuit 84, and the reset signal output from the NOR circuit 84 is input to the reset circuit 61 of the counter 6. .

For example, when the DC motor 1 rotates clockwise,
If the output pulse from the waveform shaping circuit 3 is a pulse signal in the (+) direction, the output pulse from the waveform shaping circuit 3 when the DC motor 1 rotates counterclockwise is a pulse signal in the (-) direction. By inputting these to the amplifier terminal 62 or down terminal 63 of the counter 6, addition and subtraction of the number of pulses is performed. Then, when the binary code outputted from the counter 6 after addition and subtraction matches the binary code preset in the decoder 7, a pulse signal is outputted from the decoder 7, and the output level of the monostable multi 81 is inverted and the NAND circuit At the same time, the pulse signal is outputted to the outside via 82, the output level of the monostable multi 83 is inverted, the counter 6 is reset, and the binary code output from the counter returns to O.

Therefore, in the divided pulse sending circuit of the present invention, even if a DC motor that has stopped midway rotates in the opposite direction and outputs a pulse signal from the encoder until the DC motor is restarted and restarted, the divided pulse that occurs before and after the stop is generated. timing errors can be eliminated.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a pattern recognition device having a function of absorbing the timing error of the pulse signal before and after the stop, which occurs when the electric motor is stopped midway and restarted.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a divide pulse sending circuit according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing an example of a conventional system. In the figure, 1 is a DC motor, 2 is an encoder, 3 is a waveform shaping circuit, 6 is an up/down counter, 7 is a decoder, 8 is a reset circuit, 61 is a reset terminal, 62 is an amplifier terminal, 63 is a down terminal, 81.83 is monostable multi, 82 is NAND circuit, 84 is NOR circuit, QA, QB, QC,
QD represents the output terminal of the counter, and A, B, C, and D represent the input terminals of the decoder, respectively. 6th day, child 6 days H/1 original factory 8L ゛℃, 77 ministers rate 1 closed site Sanskrit σsuke charcoal unprecedented 2 drunkenness

Claims (1)

[Claims] An up/down counter (6) that outputs a binary code when a pulse signal is input, and a pulse signal when the binary code input from the up/down counter (6) matches a preset code. A divide pulse sending circuit comprising: a decoder (7) that outputs a pulse signal; and a reset circuit (8) that resets the up/down counter (6) using a pulse signal output from the decoder (7). .