JPS61216509A - Television tuner - Google Patents

Abstract

PURPOSE:To prevent variance in characteristics of a varactor diode from exerting an adverse influence upon the performance of a television tuner by varying a control voltage impressed to the variable capacity element of a tuning circuit and also varying the gain of a high frequency amplifier so that the input signal level of the high frequency amplifier does not exceeds a saturation level. CONSTITUTION:The high frequency amplifier 3 decreases in gain by a constant extent when an input signal is too large. A host computer 27 calculates the value of an offset voltage supplied to a D/A converter 30 and either of D/A converters 31 and 32 and adds the calculated offset voltage data of data of the D/A converter 30 and either of the D/A converters 31 and 32. Then, the high frequency amplifier 3 is supplied from a control voltage from a high frequency AGC circuit 20 through an AGC controller 28 and returns to a normal operation state after tracking adjusting operation is all completed.

Description

DETAILED DESCRIPTION OF THE INVENTION For industrial application, the present invention relates to a television tuner, in which a high frequency amplifier and a local oscillator are used to perform tracking adjustment using a control signal applied to a variable capacitance element of a tuning circuit. This article concerns a superheterodyne type television tuner.

2. Description of the Related Art In general, a superhetero gain type television tuner is composed of a high frequency amplifier, a tuning circuit, a local oscillator, etc., and selects and receives a modulated wave of an arbitrary carrier frequency.
Frequency conversion to a predetermined intermediate frequency. The tuning circuit is composed of a coil, a capacitor, and a variable capacitance element (for example, a varicap diode), and tracking adjustment is performed by changing the inductance or capacitance Jl value of these elements.

Problems to be Solved by the Invention However, since the above-mentioned tracking adjustment is performed manually or by mechanical means, the accuracy of the tracking adjustment is low, it takes time, and is inconvenient. Furthermore, the variation in the characteristics of the variable capacitance diode is caused. However, there were problems such as having a negative effect on the performance of the television tuner.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a television tuner in which the tracking adjustment is electrically and automatically performed by detecting the tracking state at the detected synchronization signal level, thereby solving the above problems. .

Means for Solving the Problems The television tuner according to the present invention is comprised of synchronization signal level detection means and a control device. The synchronization signal level detection means detects the synchronization signal level in the detected video signal. The control device is supplied with a synchronization signal from the synchronization signal level detection means, and controls the gain of the high-frequency amplifier based on the synchronization signal level so that the input signal level of the high-frequency amplifier does not exceed the saturation level. A control voltage that changes sequentially is supplied to the variable capacitance element in order to obtain a tuning frequency at which the signal level becomes maximum.

Effect: The control device described above changes the control voltage applied to the variable capacitance element of the tuning circuit, and also changes the gain of the high-frequency amplifier so that the input signal level of the high-frequency amplifier does not exceed the saturation level. Obtain the tuning frequency at which the synchronization signal level in the signal is maximum.

Embodiment FIG. 1 shows a block system diagram of an embodiment of a television tuner according to the present invention. In the figure, a television broadcast signal received by an antenna 1 is transmitted to a tuning circuit 2. High frequency amplifier 3. A high frequency signal of an arbitrarily selected carrier frequency is extracted through the double tuning circuit 4 and supplied to the mixer 5. The mixer 5 is a PLL (phase, O-lacto,
(loop) ・Performs frequency conversion between the input high frequency signal and a predetermined local oscillation frequency supplied from 6 according to the selected channel, converts it into a predetermined intermediate frequency signal, and outputs the signal. Here, in PLL, 6, a predetermined frequency signal output from reference oscillator 7 is supplied to phase comparator 9 via frequency divider 8. On the other hand, the local oscillator 10
The local oscillation frequency output from the oscillator is supplied to the phase comparator 9 via a prescaler 11 and a programmable divider 12. The phase comparator 9 compares the phases of the two human input signals, generates an error voltage according to the phase difference between them, and sends the error voltage to the local oscillator 1 via the charge pump 13.
0 as a control voltage, while D in the control device 14
/A converters 30, 31 and 32 as a reference voltage. Here, selected channel data is inputted via the keyboard 26, and is supplied to the programmable divider 12 via the host computer 27, which is variably controlled to a predetermined frequency division ratio according to the selected channel. Therefore, it is well known that the local oscillator 10 outputs a local oscillation frequency of a predetermined frequency depending on the selected channel.

In this way, the intermediate frequency signal extracted from the mixer 5 is transmitted to the surface acoustic wave filter 15 and the video intermediate frequency amplifier 1.
6 to a video detector 17 and an AFT (automatic frequency adjustment) detector 18, respectively. The video signal output from the video detector 17 is supplied to an intermediate frequency AGC circuit (automatic gain control circuit) 19, which generates, for example, a synchronized AGC voltage to keep the signal level constant.
. Here, if the intermediate frequency AGC circuit 19 is keyed AGC, the voltage for AGC can be used. In addition, when the intermediate frequency AGC circuit 1-9 is a forward AGC, A
Tracking adjustment is performed so that the GC voltage is maximized, or in the case of reverse AGC, the AGC voltage is minimized. The output Ad of this intermediate frequency AGC circuit 19
The C voltage is supplied to the video intermediate frequency amplifier 16 in order to keep the synchronization signal level of the video signal constant, while the high frequency AG
It is supplied to the C circuit 20.

Composite video signal and FM extracted from video detector 17
□The audio signal and the frequency division multiplexed signal are supplied to the bandpass filter 21 and the audio trap circuit 22, respectively. The bandpass filter 21 converts the input frequency division multiplexed signal into FM
The carrier converts the 4.5M HZ FM audio signal into a P wave, while the audio trap circuit 22 converts the input frequency division multiplexed signal into an F wave.
Remove the FM audio signal of M carrier 4.5MH2 and extract the composite video signal. This FM carrier 4.5M HZ
The FM audio signal passes through an audio intermediate frequency amplifier 23 and a detector 24, is demodulated, and is output. On the other hand, the composite video signal is output via the video amplifier 25.

In such a superhetero gain type television tuner, the control device 14 includes a keyboard 26 . Host computer 27. AGC controller 28. A/D
The host computer 27 is composed of a converter 29 and multiplication type D/A converters 30 to 32, and performs tuning based on a channel selection instruction signal from the keyboard 26. Also,
When the same control voltage as that of the varicap diode in the local oscillator 10 is applied to the varicap diodes provided in the tuned circuit 2 and the double-tuned circuit 4, the desired receiving frequency (-+20 MHz to +60 MHz) is approximately 1z. ), the tuning circuit 2 and double tuning circuit 4
The inductance and capacitance values within are selected. The variable power diodes in the tuning circuit 2 and double tuning circuit 4 are controlled [li! This control voltage is supplied from the host computer 27 by D.
The control voltage applied to the varicap diode of the local oscillator 10 can be changed from Ov based on the digitized first data supplied to the /A converters 30 to 32.

The gain of the high frequency amplifier 3 is controlled by a control voltage from the AGC controller 28. This high frequency amplifier 3
is a high frequency AGC circuit 20 and an AGC controller 28
Maximum sensitivity is initially achieved by the control voltage obtained through . Further, this control voltage is such that a constant voltage is applied when performing tracking adjustment, and if the input signal is too large, it is fixed at a voltage value that reduces the gain by a constant amount. Further, after all the tracking adjustment processes are completed, a normal AGC voltage is applied here. The output control signal of the intermediate frequency AGC circuit 19 is level-shifted and amplified, and taken into the host computer 27 via the A/D converter 29, where it is digitized and the resulting numerical value represents the input level and tracking state. It is used as the second data.

Next, the operation of the control device 14, which is a main part of this embodiment, will be explained with reference to the chart 70 shown in FIGS.

First, the host combination user 27 outputs a predetermined control voltage via the AGC controller 28, and sets the gain to the maximum value so that the high frequency amplifier 3 has maximum sensitivity (Fig. 2 (A)). middle, step 33). After clearing the input data (second data) from the A/D converter 29, the host computer 27 clears all the D/A converters 3.
For example, the maximum control voltage is applied to each varicap diode in the tuning circuit 2 and double tuning circuit 4 by setting the first data given to 0 to 32 to the maximum value,
For example, set the tuning frequency to the maximum (Fig. 2 (A)
> Medium, Step 34.35).

Thereafter, in order to find the tuning frequency at which the synchronization signal level is maximum (tracking adjustment), the host computer 27 reduces the first data given to all the D/A converters 30 to 32 by "3" at the numerical level. Then, the tuning frequency is lowered, and the second data at the lowered tuning frequency is compared with a saturation level separately set inside the host computer 27 to determine whether the high frequency amplifier 3 is saturated. Determine whether Here, when the second data exceeds the input level, that is, when the input signal level of the frequency amplifier 3 exceeds the saturation level, the host computer 27 controls the control output via the AGC controller 28. The cylinder pressure is fixed at a voltage value that reduces the gain of the high frequency amplifier 3 by a certain amount, and all D/A converters (:72; The second data is cleared and the process returns to step 37, where the second data and the saturation level are compared (steps 36 to 40 in FIG. 2(A)).

In this way, by repeating the operations of steps 37 to 40, the gain of the high frequency amplifier 3 is lowered to a level at which the input level is not saturated, and the sensitivity is lowered. After that, the current second data is compared with the second data imported in the past, and if the current second data is larger, the current second data is stored in the host computer 27. For example, it is stored in RAM (Random Access Memory) (step 37.41.42).

Thereafter, the operations of steps 36 to 41 are repeated again.

In step 42, when the current second data is smaller than the past second data, the host computer 27 determines that the current tuning frequency is low, and first fine-tunes the tuning frequency. All D/A converters 30-3
2 is incremented by "1" at the numerical level to raise the tuning frequency a little, and then the second data at the raised tuning frequency is compared with a preset saturation level. Here, when the second data (input level) exceeds the saturation level, the host computer 27 lowers the gain of the high frequency amplifier 3 by a certain amount, and again all the D/A converters 30 to 32 The first data to be given to is reduced by "1" at the numerical level, returned to the tuning frequency before the arrival of the Stellaf 43, the second data is cleared, and the process returns to step 44 again, and the second data and the saturated and the level (steps 43 to 47).

After repeating the operations of steps 44 to 47 to reduce the sensitivity to a level at which the input level of the high frequency amplifier 3 is not saturated, the current second data is compared with the first second data captured in the past, When the current second data is larger, the current second data is stored (steps 44, 48, and 49). Then again step 43
Repeat steps 48 to 48.

In this way, the host computer 27
and the control voltages supplied to the respective varicap diodes in the double-tuned circuit 4 are all collectively controlled, and step 3
Rough adjustment is performed in steps 6 to 42, and then fine adjustment is performed in steps 43 to 49.

However, since the tracking adjustment described above cannot correct variations in the characteristics of individual varicap diodes as described above, next, each varicap diode is roughly finely adjusted. Now, when the current second data is smaller than the past second data in step 48, the host computer 27 only controls the D/A converter 30.
Rough adjustment of steps 36-42 and steps 43-4
The same operations as the fine adjustment in step 9 are performed in steps 50 to 56 and steps 57 to 63 in FIG. 2(B), respectively. Thereafter, in step 64, operations similar to steps 50 to 63 described above are sequentially performed for each of the D/A converters 31 and 32.

Thereafter, the host computer 27 calculates the offset voltage value to be applied to the D/A converter 30 and either the D/A converter 31 or 32 in order to obtain the necessary frequency bandwidth. These offset voltage data are sent to the D/A converter 30 and the D/A converter 31 or 32.
Add to the data of either - ・. Then, after all the tracking adjustment operations are completed, the high frequency field! @3 is the control voltage from the high frequency AGC circuit 20.
C controller 28 to return to normal operating conditions (steps 65-67).

Further, the data for the tracking adjustment described above is stored in a non-volatile memory in the host computer 27, and from now on, by performing tracking adjustment based on this data, the speed of channel selection can be increased.

Furthermore, the effects of the invention on the D/A converters 30 to 32 are as follows: As described above, according to the present invention, the tracking adjustment of the television tuner, which has conventionally been performed by humans or machines, can be performed completely automatically. It also has features such as being able to improve the negative effects that variations in the characteristics of variable capacitance elements such as varicap diodes have on tuner performance, and being able to obtain the best tracking condition over the entire receiving frequency band. .

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an embodiment of a television tuner according to the present invention, and FIG. 2 (A). (B) is a flowchart for explaining the operation of the control device in the block system shown in FIG. 2... Tuned circuit, 4... Double tuned circuit, 5... Mixer, 6... PLL (phase locked loop)
, 14...control device, 26...keyboard, 27.
...Host computer, 28...AGC controller, 29...A/D converter, 30-32...D/A
converter.

Claims (1)

[Claims] A tuning circuit capable of controlling the tuning frequency by a control voltage applied to a variable capacitance element is provided independently before and after the high-frequency amplifier and in the local oscillator, and tracking adjustment of the high-frequency amplifier and local oscillator is performed by each tuning circuit. In a superheterodyne television tuner that operates by changing the control voltage applied to the variable capacitance element of the circuit, a synchronization signal level detection means for detecting a synchronization signal level in a detected video signal; ,
A periodic signal is supplied from the synchronization signal level detection means,
The gain of the high frequency amplifier is controlled based on the synchronization signal level so that the input signal level of the high frequency amplifier does not exceed the saturation level, and the variable capacitance element is controlled to obtain a tuning frequency at which the synchronization signal level is maximized. A television tuner comprising a control device that supplies a control voltage that changes sequentially.