JPH0124990Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a radio receiver, and more particularly to a radio receiver in which the frequency sensitivity of an electronically tuned radio receiver can be automatically adjusted.

Conventionally, in radio receivers, a high frequency amplifier is installed in a tuned or non-tuned input circuit to perform high frequency amplification to increase sensitivity and selectivity, and to improve signal-to-noise ratios against noise generated from frequency conversion circuits, etc. The aim is to improve the ratio, that is, the S/N ratio. 1st
As an example of a conventional high-frequency amplifier, the figure shows a high-frequency amplification circuit for an untuned input circuit for AM reception in car radios and the like. The high frequency signal received by the rod antenna is passed through the AM band noise prevention coil _L11 ,
The signal is sent to FET2, which serves as a high frequency amplification circuit, via a DC blocking capacitor _C11 . FET2 includes source self-bias resistances R ₁₁ , R ₁₂ and bypass capacitors.
C ₁₂ is connected. The high frequency signal amplified to a predetermined level by this FET 2 is sent to the next stage mixer circuit or high frequency amplification circuit.

Rod antennas used in car radios have high impedance (approximately 1MΩ), and the capacitance changes depending on the length of the antenna, so it is not possible to connect a tuning circuit as is. For this reason, the above-mentioned high frequency amplifier circuit is used in the non-tunable input circuit.

By the way, in a high frequency region such as radio frequency,
When performing high frequency amplification using FET, the channel capacitance between drain and source (see C ₀ in Figure 1)
_Because the gain decreases as the frequency increases due _to the influence of _parallel capacitances such as As shown by solid line A, it becomes a decreasing curve. Therefore, if you try to increase the sensitivity to increase the S/N ratio for noise generated in the subsequent stage around 1400KHz, the sensitivity around 600KHz will increase too much and oscillate, or the noise components generated in the high frequency amplifier circuit will increase. or vice versa, 600KHz
When trying to lower the sensitivity to prevent oscillations and increases in noise components in the vicinity, there was an inconvenience that the S/N ratio around 1400KHz became extremely poor.

The present invention was developed in view of the shortcomings of the conventional technology, and it automatically adjusts the sensitivity to frequency to reduce the difference in sensitivity within the reception band, improve the S/N ratio of the entire band, and reduce noise. To provide a highly stable radio receiver by suppressing components,
That purpose.

Therefore, the present invention provides a sensitivity adjustment circuit that varies the amplification gain in the amplifier circuit of a radio receiver that performs electronic tuning by changing the circuit constant of the resonant circuit using a frequency-related control signal. The purpose of the present invention is to achieve the above object by adopting a configuration in which the sensitivity within the receiving band is controlled to be approximately constant by controlling the signal using a specific control signal.

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

Figure 3 shows the PLL for car radio according to the present invention.
1 is a partially block circuit diagram showing an electronically tuned AM receiver; FIG. In the figure, a high-frequency amplifier circuit 11 as a non-tunable input circuit connected to a rod antenna 10 includes a band-pass filter 12 consisting of C ₁ and L ₁ , and a received signal (high-frequency signal ), source self-bias resistances R ¹ , R ₂ , capacitors C ₂ ,
Tuning of a secondary side single resonance consisting of a bypass capacitor circuit 15 consisting of C ₃ and a transistor 14, a transformer T ₁ connected to the output side of the FET 13, capacitors C ₄ and C ₅ and a variable capacitance diode D ₁ It is composed of a circuit 16. The varicap _D1 has a characteristic that its capacitance changes depending on the magnitude of the reverse voltage, and electronic tuning can be performed by electronically changing the secondary resonance frequency by changing the capacitance. The capacitance of this variable cap _D1 is controlled by a frequency-related control signal (varactor voltage; see Figure 4) input via a resistor R from a low-pass filter 26 of a phase-locked loop (PLL), which will be described later. It is designed to be done.

The transistor 14 provided in the bypass capacitor circuit 15 changes the impedance of the bypass capacitor circuit 15 from large capacitance to small capacitance by changing from a conductive state (on state) to a non-conductive state, and amplifies the FET 13. This is for making the gain variable, and forms a sensitivity adjustment circuit 18 together with a level correction circuit 17 connected to the base on the input side. The level correction circuit 17 corrects the level of the control signal related to the frequency sent via the buffer circuit 19 according to a predetermined correction curve and applies it to the base of the transistor 14, so that the received frequency is shifted to the high frequency region within the band. When present, the gain is increased by increasing the base voltage to bring it closer to the conduction state, while
When the reception frequency is in the low frequency range, the gain is reduced by reducing the base voltage to bring it close to a non-conducting state, thereby reducing the channel capacitance of FET 13 in the high frequency region and the impedance of C ₂ Z ₂ = (1/jωC ₂ ) is possible within the range where the overall frequency sensitivity is approximately constant within the reception band as shown by the broken line B in Figure 2, the FET 13 does not oscillate, and the noise component can be ignored. This setting is to obtain the highest possible sensitivity.

The output signal of the high frequency amplification circuit 11 is taken out from the tap terminal provided on the secondary coil 20 of the tuned circuit 16, and the output signal is taken out from the high frequency amplification circuit 2 connected to the next stage.
Sent to 1. This high frequency amplification circuit 21 is a tuning circuit (not shown) using a varicap on the output side.
The high-frequency amplified signal here is mixed with the oscillation signal of a voltage controlled oscillator 23 as a local oscillation circuit in a frequency conversion circuit 22 connected to the next stage to become an intermediate frequency signal. The voltage controlled oscillator 23 is composed of an oscillation circuit using a varicap, and has a function of changing the oscillation frequency according to the magnitude of the voltage (varactor voltage) applied from the outside. This voltage controlled oscillator 23 includes a programmable counter 24 for frequency division, a phase detector 25,
It is connected in a closed loop with the low-pass filter 26 to form a phase locked loop, and when the frequency division ratio of the programmable counter 24 is constant, the frequency of the divided feedback signal oscillated by the voltage controlled oscillator 23 and its phase are are subjected to feedback control so that they match the frequency and phase of a reference signal input from a crystal oscillator 27 connected to a phase detector 25. Further, the controller 2 connected to the programmable counter 24
By sending program data from 8 and setting a desired frequency division ratio, an arbitrary oscillation frequency can be obtained in steps of the reference signal frequency. The controller 28 has functions such as automatic channel selection and skip channel selection using a preset memory, and can be operated externally by key input.

Here, the operation of the phase-locked loop is briefly explained.
First, the phase detector 25 determines the phase lead/lag of the reference signal and the feedback signal, and outputs a voltage corresponding to the phase error. Specifically, for example, if the reference signal leads the feedback signal in phase, the charge pump (not shown) output is set to "high" for a time equal to the phase difference, and conversely, if the reference signal lags the feedback signal, is adapted to keep the charge pump output "low" for a period of time equal to the phase difference.
The charge pump output of the phase detector 25 is provided by two Darlington-connected transistors 29, 30,
The signal is sent to an active low-pass filter 26 composed of feedback elements R ₄ , R ₅ , C ₆ and resistors R ₆ and R ₇ . This low-pass filter 26 integrates the output of the phase detector 25 and converts the phase error into a DC voltage. It has the function of holding. Low pass filter 2
The output of 6 is sent to the voltage controlled oscillator 23 as a varactor voltage for frequency control. and,
When the frequency division ratio is constant, the output of the low-pass filter 26 is controlled to vary slightly around a certain constant lock voltage, and the oscillation frequency is controlled to be a certain constant value. Furthermore, when the frequency division ratio changes, the output of the low-pass filter 26 changes to a lock voltage according to the frequency division ratio, and therefore the oscillation frequency of the voltage controlled oscillator 23 also changes according to the frequency division ratio. The value changes. Therefore, the output of the low-pass filter 26 becomes a frequency-related control signal, which is sent to the voltage-controlled oscillator 23 as a local oscillator circuit.
The voltage is applied as a varactor voltage to the tuning circuit 16 of the high frequency amplification circuit 11 and the tuning circuit provided in the high frequency amplification circuit 21 to perform tracking. However, the resonant frequency (reception frequency) of the tuned circuit is set higher than the oscillation frequency of the voltage controlled oscillator by an amount corresponding to the intermediate frequency. Further, as described above, the output of the low-pass filter 26 is sent to the level correction circuit 17 of the sensitivity adjustment circuit 18 via the buffer circuit 19. FIG. 4 shows the relationship between the output voltage of the low-pass filter 26 and the resonance frequency of the tuned circuit, that is, the reception frequency.

An intermediate frequency amplification circuit 31 is connected to the output side of the frequency conversion circuit 22, and the intermediate frequency signal amplified here is demodulated into an audio signal by a detection circuit 32 and then further demodulated by a low frequency amplification circuit 33. The power is amplified and the sound is output from the speaker 34.

An automatic gain adjustment circuit 35 is connected to the detection circuit 32, and when the voltage of the high frequency signal input from the rod antenna 10 changes due to fading or the like, the intermediate frequency amplifier circuit 31 or the automatic gain adjustment circuit 35 is connected to the detection circuit 32. AGC (automatic gain control) is applied to the high frequency amplification circuit 11 to keep the volume constant. The high frequency amplification circuit 11 generates a high frequency signal when the volume change is large.
It is configured so that AGC can be applied. The high frequency amplification circuit 11 is of an emitter follower type in which the high frequency AGC signal sent from the automatic gain adjustment circuit 35 is applied to its base, and the output side of the FET 13 is connected to the collector side via a neutralizing capacitor _C7 . A neutralizing type high frequency automatic gain control circuit 38 is provided, which is composed of a transistor 36 and a transistor ₃₇ whose base input is the emitter terminal output of this transistor 36 and whose collector side is connected to the gate side of the FET 13 via a resistor R8. It is being The transistor 36 has a function of superimposing a neutralization signal on the high frequency AGC signal. Here, neutralization means that a current is returned to the input side through the external capacitor _C7 to cancel the current that is internally fed back through the barrier capacitance between the gate and drain of FET 13, thereby preventing oscillation. When AGC is applied to the FET 13, the neutralization conditions change depending on the magnitude of the AGC, so the transistor 36 always adjusts the feedback current to the optimum value. The transistor 36 has a bias resistor R ₉ and a ground capacitor C ₈ for harmonic removal.
is grounded. The high frequency AGC signal on which the neutralization signal is superimposed by the transistor 36 is applied to the base side of the FET 13 via the transistor 37.
Gain adjustment is performed.

An AGC terminal for LOCAL/DX switching is connected to the output side of the FET 13 to vary the reception level according to the electric field strength.

Next, the operation of the automatic frequency sensitivity adjustment part of the above embodiment will be described in the case where automatic channel selection is performed.

When the controller 28 is instructed to automatically select a channel by key operation, the controller 28 first sets the frequency division ratio related to the minimum frequency within the reception band in the programmable counter 24, and then operates a phase-locked loop to gradually divide the channel. Increase the circumference ratio. At this time, a control signal related to the reception frequency is sent from the low-pass filter 26 to each of the voltage-controlled oscillator 23, the tuning circuit 16, etc., and the sensitivity adjustment circuit 18, and the reception frequency is gradually increased. . When the sensitivity adjustment circuit 18 receives a control signal, it outputs a voltage at an appropriate level for the reception frequency represented by the magnitude to the transistor 14, changes the impedance between its collector and emitter, and adjusts the capacitance component of the bypass capacitor circuit 15. is adjusted so that the sensitivity of the high-frequency amplifier circuit 11 remains approximately constant regardless of the frequency, as shown by the dotted line in FIG.

The controller 28 stops changing the frequency division ratio for a period of time when a local signal is detected by a method such as carrier peak detection, and allows the listener to judge whether the change satisfies his or her wishes, and then operates a key within a certain period of time. When the user instructs the station to continue receiving, the reception state is fixed for that station, and if there is no key operation, the frequency division ratio is changed again and the next channel selection operation is started. In this way, when the highest frequency within the reception band has been selected, it returns to the lowest frequency and repeats the same operation.

In the above embodiment, the capacitance component of the bypass capacitor circuit 15 is varied using a transistor to adjust the gain, but the same can be done by using a varicap. As shown in the figure, the source bias resistance R _2A of FET13A,
A resistor R ₁₀ and a transistor 14A are connected in parallel with the bypass capacitor C _2A , and this transistor 14A
may be controlled by a frequency-related control signal via the buffer circuit 19A and the level correction circuit 17A. In addition to the above-mentioned high-frequency amplification circuit 11, sensitivity adjustment is performed by the high-frequency amplification circuit 21.
It goes without saying that the intermediate frequency amplification circuit 31 can also perform the same operation.

As described above, according to the present invention, it is possible to eliminate sensitivity differences within the reception band, improve the S/N ratio in the high frequency range, and prevent oscillation and increase in noise components in the low frequency range.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional high-frequency amplification circuit, Fig. 2 is a diagram showing the relationship between receiving frequency and relative sensitivity, and Fig. 3 is a PLL type electronically tuned AM receiver according to an embodiment of the present invention. FIG. 4 is a diagram showing the frequency/output voltage characteristics of the low-pass filter according to a part of FIG. 3, and FIG. 5 is a circuit diagram showing another embodiment. 11... High frequency amplifier circuit, 14, 14A... Transistor as a main part of the sensitivity adjustment circuit, 16...
... Tuning circuit, 18 ... Sensitivity adjustment circuit, 23 ... Voltage controlled oscillator, 24 ... Programmable counter, 25 ... Phase detector, 26 ... Low pass filter.

Claims (1)

[Scope of utility model registration request] In a radio receiver equipped with a non-tunable input circuit that applies a frequency-related control signal to change the circuit constant of a resonant circuit and perform electronic tuning, the amplification gain is varied in the radio frequency amplifier circuit of the radio receiver. A sensitivity adjustment circuit is provided, and this sensitivity adjustment circuit is controlled by a control signal related to the frequency so that the sensitivity is high on the high frequency side and the sensitivity is low on the low frequency side, so that the sensitivity within the reception band is approximately constant. A radio receiver characterized in that it can be adjusted so that.