GB2173661A

GB2173661A - Superheterodyne television tuner

Info

Publication number: GB2173661A
Application number: GB08606962A
Authority: GB
Inventors: Takeo Oishi
Original assignee: Victor Company of Japan Ltd; Nippon Victor KK
Current assignee: Victor Company of Japan Ltd; Nippon Victor KK
Priority date: 1985-03-22
Filing date: 1986-03-20
Publication date: 1986-10-15
Also published as: DE3609349C2; GB8606962D0; DE3609349A1; DE3609349C3; GB2173661B

Abstract

A superheterodyne television tuner automatically and electrically performs a tracking adjustment by changing a gain of a high frequency amplifier 13 depending on a level of a synchronizing signal within a detected video signal so that an input signal level of the high frequency amplifier does not exceed a saturation level and by applying control voltages which successively change to variable capacitance elements of tuned circuits 12, 14 which are provided in stages before and after the high frequency amplifier so as to obtain a tuning frequency at which the level of the synchronizing signal within the detected video signal becomes a maximum. <IMAGE>

Description

SPECIFICATION Superheterodyne Television Tuner The present invention generally relates to television tuners, and more particularly to a superheterodyne television tuner which is designed so that tracking adjustments of a high frequency amplifier and a local oscillator are performed by control signals which are applied to variable capacitance elements of tuned circuits.

Generally, a superheterodyne television tuner comprises a high frequency amplifier, tuned circuits, a local oscillator and the like. The television tuner tunes into a modulated wave of an arbitrary carrier frequency, and frequency-converts the modulated wave into a predetermined intermediate frequency.

The tuned circuits respectively comprise coils, capacitors and variable capacitance elements (for example, variable capacitance diodes), and the tracking adjustments are performed by changing the inductance or capacitance of these elements constituting the tuned circuits.

However, the tracking adjustment is conventionally performed manually or by mechanical means. For this reason, the accuracy of the tracking adjustment is poor, and it takes time to perform the tracking adjustment. In addition, the tracking adjustment is troublesome to perform. Furthermore, inconsistencies in characteristics of the variable capacitance diodes introduce undesirable effects on the performance of the television tuner.

On the other hand, when the tracking adjustments of the tuned circuit in a stage preceding the high frequency amplifier and the double-tuned circuit in a stage subsequent to the tuned circuit are performed while receiving a television broadcast signal by changing control voltages which are applied to the variable capacitance elements so that a video signal supplied to a video intermediate frequency amplifier becomes a maximum or so that the level of a synchronizing signal in the video signal after the detection thereof becomes a maximum, tuning fre quencies of the tuned circuits become the same.

Hence, there is a problem in that it is impossible to obtain a frequency band width required for satisfactory signal reception and tuning.

Accordingly, it is a general object of the present invention to provide a novel and useful superheter odyne television tuner in which the problems de scribed heretofore are eliminated.

The present invention provides a superheterodyne television tuner comprising, tuned circuits indepen dently provided in stages before and after a high frequency amplifier and within a local oscillator, each of said tuned circuits having a variable capacitance element and being controlled of a tuning frequency thereof by a control voltage applied to the variable capacitance element, tracking adjustments of said high frequency amplifier and said local oscillator being performed by varying the control voltages applied to the variable capacitance ele ments of the tuning circuits, level detecting means for detecting a level of a synchronizing signal within a a video signal which is detected, and a control device supplied with the detected synchronizing signal level from said level detecting means for controlling a gain of said high frequency amplifier so that an input signal level of said high frequency amplifier does not exceed a saturation level thereof and for supplying to said variable capacitance elements control voltages which successively vary so as to obtain a tuning frequency at which the synchronizing signal level becomes a maximum. According to the television tuner of the present invention, it is possible to automatically perform the tracking adjustment which is conventionally performed manually or by mechanical means.Furthermore, it is possible to minimize undesirable effects on the performance of the television tuner caused by inconsistencies in characteristics of variable capacitance diodes and the like, and an optimum tracking state can be obtained throughout the entire frequency band of a signal which is received by the television tuner. It is also possible to obtain with ease a frequency band width required for satisfactory signal reception and tuning even when the tuning frequencies of the tuned circuits do not coincide when the tracking adjustments are performed.

Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.

Figure 1 is a system block diagram showing an embodiment of the superheterodyne television tuner according to the present invention; Figure 2 is a system circuit diagram showing an embodiment of a phase comparator and a charge pump in the block system shown in Figure 1; Figure 3 is a system circuit diagram showing an embodiment of a double-tuned circuit in the block system shown in Figure 1; Figures 4A and4B respectively are flow charts for explaining the operation of a host computer in the block system shown in Figure 1; and Figure 5 is a graph showing examples of the relationship between a control voltage applied to a variable capacitance element and a tuning frequency.

In Figure 1, a television broadcast signal is received via an antenna 11. The television broadcast signal is passed through a tuned (ortuning) circuit 12, a high frequency (HF) amplifier 13 and a doubletuned circuit 14 so as to obtain a high frequency signal having an arbitrarily tuned-in carrier frequency. The high frequency signal is supplied to a mixer 15 which performs a frequency conversion with the high frequency signal and a high frequency signal which is obtained from a phase locked loop (PLL) 16 and has a predetermined local oscillation frequency in accordance with a tuned-in channel, and a predetermined intermediate frequency signal is outputted from said mixer 15. In the PLL 16, an output predetermined frequency signal of a reference oscil lator 17 is supplied to a phase comparator 19 via a frequency divider 18.On the other hand, an output local oscillation frequency signal of a local oscillator 20 is passed through a pre-scaler 21 and a prog rammable divider 22 and is supplied to the phase comparator 19. The phase comparator 19 compares phases of the two signals supplied thereto and generates a two-bit phase error voltage in accord- is ance with a phase error between the two signals.

The phase error voltage is supplied to a charge pump 23. The charge pump 23 converts the phase error voltage which is in a form of a pulse signal having high and low levels into an analog voltage.

For example, the charge pump 23 comprises transistors, resistors and the like as shown in Figure 2. In Figure 2, those parts which are the same as those corresponding parts in Figure 1 are designated by the same reference numerals. In Figure 2, a lowpass filter comprising transistors including a field-effect transistor (FET), a capacitor, resistors and the like is coupled to a stage subsequent to terminals 23a and 23c of the charge pump 23. Hence, the signals from the terminals 23a and 23c are passed through this iowpass filter before being outputted as an output analog voltage of the charge pump 23.

When the output signal of the programmable divider 22 is lower in frequency or lagging in phase compared to the output signal of the frequency divider 18, a first bit of the phase error voltage at a terminal 19a of the phase comparator 19 has a low level, for example. On the other hand, when the output signal of the programmable divider 22 is higher in frequency or leading in phase compared to the output signal of the frequency divider 18, a second bit of the phase error voltage at a terminal 19b of the phase comparator 19 has a low level, for example. Furthermore, when the frequency of phase of the output signal of the programmable divider 22 is equal to that of the output signal of the frequency divider 18, the first and second bits of the phase error voltage attheterminals 19a and 19b respectively have a high level.The two-bit phase error voltage from the phase comparator 19 having such a high-and-low level bit combination is supplied to the charge pump 23.

When the first bit of the phase error voltage at the output terminal 1 9a ofthe phase comparator 19 has a low level, a current flows from the terminal 23a shown in Figure 2 to the terminal 19a, and the output voltage of the charge pump 23 increases. On the other hand, when the second bit of the phase error voltage at the output terminal 1 9b of the phase comparator 19 has a low level, a current flows from a power source (not shown) for supplying a power source voltage Vcc to the terminal 23c via a terminal 23b, and the output voltage of the charge pump 23 decreases.When the first and second bits of the phase error voltage at the terminals 1 9a and 1 9b respectively have a high level, the terminals 23a and 23c respectively assume floating states, and the output voltage of the charge pump 23 does not change.

Accordingly, the charge pump 23 outputs an analog voltage in accordance with the phase error voltage generated from the phase comparator 19, and supplies this analog voltage to the local oscillator 20 as a control voltage therefor. The analog voltage from the charge pump 23 is also supplied to multiplier type digital-to-analog (D/A) converters 40, 41 and 42 as reference voltages therefor.

Returning now to the description of Figure 1, a channel selection datum related to a channel to which the television tuner is to be tuned in is entered from'a keyboard 36 and is supplied to the programmable divider 22 via a host computer 37. Hence, a frequency dividing ratio of the programmable divider 22 is variably controlled by the channel selection datum entered from the keyboard 36. As a result, a local oscillation frequency signal having a predetermined frequency (that is, a sum of the frequency of the received signal and the intermediate frequency) in accordance with the tuned-in channel is obtained from the local oscillator 20, as is well known.

The intermediate frequency signal obtained from the mixer 15 is passed through a surface wave filter 25 and a video intermediate frequency (IF) amplifier 26, and is supplied to a video detector 27 and an automatic frequency tuning (AFT) detector 28. A video signal obtained from the video detector 27 is supplied to an intermediate frequency automatic gain control (IF AGC) circuit 29 which generates an AGC voltage for making the level of a synchronizing signal within the video signal constant.In the case where the IF AGC circuit 29 is a keyed AGC circuit, it is possible to use as the output AGC voltage of the IF AGC circuit 29 an AGC voltage which is used within the keyed AGC circuit to control the gain of the keyed AGC circuit. In the case where the IF AGC circuit 29 is a forward AGO circuit, the tracking adjustment is performed so that the AGC voltage becomes a maximum. On the other hand, in the case where the IF AGC circuit 29 is a reverse AGO circuit, the tracking adjustment is performed so that the AGC voltage becomes a minimum.The output AGC voltage of the IF AGC circuit 29 is supplied to the video IF amplifier 26 so as to make the level of the synchronizing signal constant. The output AGC voltage of the IF AGC circuit 29 is also supplied to a high frequency automatic gain control (HF AGC) circuit 30.

Afrequency division muitiplexed signal obtained from the video detector 27 comprises a composite video signal and a frequency modulated (FM) audio signal. This frequency division multiplexed signal is supplied to a bandpass filter 31 and an audio trap circuit 32. The bandpass filter 31 filters and obtains from the frequency division multiplexed signal the FM audio signal having an FM carrier of 4.5 MHz. On the other hand, the trap circuit 32 eliminates from the frequency division multiplexed signal the FM audio signal having the FM carrier of 4.5 MHz, and obtains the composite video signal. The FM audio signal having the 4.5 MHz FM carrier is passed through an audio intermediate frequency (IF) amplifier 33 and a detector 34, and is outputted via an output terminal. The composite video signal from the audio trap circuit 32 is passed through a video amplifier 35 and is outputted via another output terminal.

In the superheterodyne television tuner having the construction described heretofore, a control device 24 is constituted by the keyboard 36, the host computer 37, an automatic gain controller (AGC) 38, an analog-to-digital (AID converter 39, and the D/A converters 40,41 and 42. The host computer 37 performs the tuning based on the channel selection datum entered from the keyboard 36. The values of the inductances and capacitances within the tuned circuit 12 and the double-tuned circuit 14 are selected so that the tuned circuits 12 and 14 respectively tune into a desired reception frequency (+ 20 MHz to + 60 MHz) when a control voltage identical to that applied to a variable capacitance diode provided within the local oscillator 20 is applied to variable capacitance diodes provided within the tuned circuits 12 and 14.A control voltage is applied to the tuned circuits 12 and 14fromthe host computer 37 via the D/A converters 40 through 42 and operational amplifiers (not shown). The control voltages applied to the tuned circuits 12 and 14 are respectively varied from zero to the control voltage applied to the variable capacitance diode within the local oscillator 20 depending on digitized first data supplied to the D/A converters 40 through 42 from the host compu ter37.

The AGC 38 comprises at least a switch (not shown) and a D/A converter (not shown). While the tracking adjustment is being performed, the AGC 38 outputs a control voltage which is obtained by subjecting an output datum of the hostcomputer37 to a digital-to-analog (D/A) conversion. After the tracking adjustment is finished, the AGC 38 outputs a normal AGC voltage from'the HF AGC circuit 30 as it is.

The gain of the HF amplifier 13 is controlled by the control voltage from the AGC 38. At first, the sensitivity of the HF amplifier 13 is set to a maximum sensitivity by the control voltage which is obtained through the HF AGC circuit 30 and the AGC 38. The control voltage supplied to the HF amplifier 13 is constant when the tracking adjustment is performed, and the control voltage is fixed to a predetermined voltage for lowering the gain of the HF amplifier 13 when the level of an input signal of the HF amplifier 13 is too high. Afterthe tracking adjustment is completed, the normal AGC voltage is supplied to the HF amplifier 13.The output AGC voltage of the IF AGC circuit 29 is passed through the AID converter 39 and is entered into the host computer 37 which digitizes the AGC voltage and uses the digitized control voltage as a second datum indicative of the input level and the tracking state.

Next, description will be given with respect to the construction and operation of the double-tuned circuit 14 by referring to Figure 3. In Figure 3, those parts which are the same as those corresponding parts in Figure 1 are designated by the same reference numerals. As is well known, the doubletuned circuit 14 comprises two resonance circuits. In the present embodiment, the double-tuned circuit 14 comprises coils L1 through L5, capacitors C1 through C10, diodes D1 and D2, variable capacitance diodes VD1 and VD2 and resistors R1 through R6. A connection point A between one teminal of the resistor R3 and one terminal of the resistor R4 is coupled to the host computer 37 via a diode D3. The other terminal of the resistor R3 is grounded via a parallel circuit comprising a resistor R7 and a capacitor C11.A connection point B of one terminal of the capacitor C5 and respective terminals of the resistors R1 and R6 is coupled to the host computer 37. The other terminal of the capacitor C5 is grounded.

The switching of the receiving channel between a high channel and a low channel upon reception of a very high frequency (VHF) television broadcast signal is performed by controlling ON and OFF states of the diodes D1, D2 and D3 depending on channel designating signals from the host computer 37.

When a high channel VHF television broadcast signal is to be received, the keyboard 36 is manipulated to select a high channel, and the host computer 37 supplies a high-level high-channel designating signal to the connection point B shown in Figure 3.

Further, a low-level low-channel designating signal is supplied to the diode D3 from the host computer 37. The high-channel designating signal and the low-channel designating signal are two-valued signals having mutually opposite phases. As a result, the diode D3 is turned OFF and the diodes D1 and D2 are turned ON to short-circuit the capacitors C3 and C8.

On the other hand, when a low channel VHF television broadcast signal is to be received, the keyboard 36 is manipulated to select a low channel, and the host computer 37 supplies a high-level low-channel designating signal to the diode D3 shown in Figure 3 and a low-level high-channel designating signal to the connection point B. As a result, the diode D3 is turned ON and the diodes D1 and D2 are turned OFF. In this case, the capacitors C3 and C8 are not short-circuited.

Accordingly, the time constant of the doubletuned circuit 14 is switched depending on whether the high channel or the low channel is selected by the keyboard 36.

The control voltage from the D/A converter 41 is supplied to a connection point between a terminal of the capacitor C1 and a cathode of the variable capacitance diode VD1. The control voltage from the D/A converter 42 is supplied to a connection point between a terminal of the capacitor C10 and a cathode of the variable capacitance diode VD2. The capacitances of the variable capacitance diodes VD1 and VD2 are varied depending on the respective control voltages from the D/A converters 41 and 42, and thus, the tuning frequencies (resonance frequencies) of the two resonance circuits within the double-tuned circuit 14 are controlled accordingly.

Therefore, the time constant of the double-tuned circuit 14 is varied and the resonance frequencies of the two resonance circuits within the double-tuned circuit 14 are accordingly varied depending on whether the high channel or the low channel is selected by the keyboard 36 and also depending on the output control voltages of the D/A converters 41 and 42.

As described heretofore, according to the television tuner of the present invention, the variable capacitance diodes within the tuned circuits 12 and 14 and the local oscillator 20 are controlled independently.

Next, description will be given with respect to the operation of the host computer 37 by referring to fiowcharts shown in Figures 4A and 4B. The operation of the host computer 37 is started in a step 51 when it is detected that a power switch (not shown) is turned ON and the power source voltage Vcc is supplied to the television tuner of the present invention. First, the host computer 37 outputs a predetermined control voltage via the AGC 38 in a step 52 to set the gain of the HF amplifier 13 so that the HF amplifier 13 is set to the maximum sensitivity.

A step 53 clears the input datum (second datum) from the A/D converter 39. A step 54 sets all of the first data supplied to the DIA converters 40 through 42 to maximum values, so that maximum control voltages are supplied to the variable capacitance diodes of the tuned circuits 12 and 14 and the tuning frequencies are set to maximum frequencies, for example.

A step 55 decreases the values of the first data supplied to each of the DIA converters 40 through 42 by "3" and decreases the tuning frequency so as to obtain a tuning frequency at which the level of the synchronizing signal becomes a maximum. A step 56 discriminates whether or not the value of the second datum at the decreased tuning frequency is greater than a saturation level preset within the host computer 37 to determine whether or not the HF amplifier 13 is in a saturated state. In the case where the level of the second datum is greater than the level of the input signal of the HF amplifier 13, that is, in the case where the level of the inputsingal of the HF amplifier 13 is greater than the saturation level, the discrimination result in the step 56 is YES.When the discrimination result in the step 56 is YES, a step 57 fixes the control voltage outputted through the AGC 38 to a predetermined voltage so as to reduce the gain of the HF amplifier 13 by a predetermined quantity. A step 58 increases the values of the first data supplied to each of the DIA converters 40 through 42 by "3" and so as to return the tuning frequency to the original maximum tuning frequency. A step 59 clears the second datum, and the operation is returned to the step 56 which discrimin ateswhetherornotthe level of the second datum is greater than the saturation level.

By repeating the steps 56 through 59, the gain and the sensitivity of the HF amplifier 13 are reduced to such an extent that the level of the input signal of the HF amplifier 13 does not exceed the saturation level.

When the discrimination result in the step 56 becomes NO, a step 60 discriminates whether or not the level of the present second datum is greater than the level of the second datum entered previously. In the case where the discrimination result in the step 60 is YES, a step 61 stores the present second datum into a random access memory (RAM) or the like within the host computer 37. Thereafter, the operation is returned to the step 55 and the steps 55 through 60 are repeated.

When the discrimination result in the step 60 becomes NO, the host computer 37 discriminates that the present tuning frequency is low. Hence, in order to finely adjust the tuning frequency, a step 62 increases the values of the first data supplied to each of the DIA converters 40 through 42 by "1" so as to increase the tuning frequency. Next, a step 63 discriminates whether or not the second datum at the increased tuning frequency is greater than the preset saturation level. In the case where the discrimination result in the step 63 is YES, a step 64 reduces the gain of the HF amplifier 13 by a predetermined quantity, and a step 65 decreases the values of the first data supplied to each of the D/A converters 40 through 42 by "1" to return the tuning frequency to the tuning frequency at the time before the step 62 was performed.A step 66 clears the second datum, and the operation is returned to the step 63 which discriminates whether or not the level of the second datum is greater than the saturation level.

The steps 63 through 66 are repeated until the sensitivity of the HF amplifier 13 is reduced to such an extent that the HF amplifier 13 does not assume the saturated state. When the discrimination result in the step 63 becomes NO, a step 67 discriminates whether or not the level of the present second datum is greater than the level of the previous second datum. When the discrimination result in the step 67 is YES, a step 68 stores the present second datum into the RAM or the like within the host computer 37, and the operation is returned to the step 62. Hence, the steps 62 through 67 are repeated.

Accordingly, the host computer 37 controls the control voltages supplied to the variable capacitance diodes within the tuned circuits 12 and 14. The steps 55 through 61 perform a rough adjustment, and the steps 62 through 68 thereafter perform a fine adjustment.

However, it is impossible to compensate for the inconsistencies in the characteristics of the variable capacitance diodes by the tracking adjustment described above. Hence, a further fine adjustment is performed to compensate for the inconsistencies in the characteristics of the variable capacitance diod es. When the level of the present second datum is smaller than the level of the previous second datum and discrimination result in the step 67 is NO, the host computer 37 performs steps 69 through 75 and steps 76 through 82 shown in Figure 4B which are respectively similarto the rough adjustment steps 55 through 61 and the fine adjustment steps 62 through 68 shown in Figure 4A, only with respect to the DIA converter 40. Then, a step 83 successively performs operations similar to those performed in the steps 69 through 82 with respect to the DIA converters 41 and 42.

But according to the operations described above, center frequencies of the tuned circuits 12 and 14 will coincide, and it is impossible to obtain a sufficient frequency band width in the HF amplifier 13. Thus, in order to obain the frequency band width required to achieve satisfactory signal reception and tuning, the host computer 37 calculates offset voltages to be supplied to the DIA converters 40 through 42 in a step 84.

Figure 5 shows examples of the relationship between the control voltage supplied to the variable capacitance diode and the tuning frequency. In FigureS, characteristics I and II respectively indicate tuning frequency versus control voltage characteristics for the cases where the low channel and the high channel are selected upon reception of the VHF television broadcast signal, and a characteristic Ill indicates a tuning frequency versus control voltage characteristic for the case where an ultra high frequency (UHF) television broadcast signal is received. As shown in Figure 5, the control voltage changes approximately linearly with respect to the tuning frequency.For example, between the case where the tuning frequency is high and the case where the tuning frequency is low, the changes in the control voltages supplied to the D/A converters 40 through 42 per one bit of respective first data differ. Accordingly, offset voltages for the maximum frequency and the minimum frequency are obtained as initial values for each of the frequency bands, and the required offset voltages are obtained for the inbetween frequencies by performing calculations to interpolate the required offset voltages.Even in the case where the control voltage does not change linearly with respect to the tuning frequency, it is possible to divide the tuning frequency versus control voltage characteristic into several sections in terms of respective frequency bands, and obtain the required control voltages by performing an interpolation similar to the interpolation described above for each of the divided sections.

A step 85 adds the offset voltages obtained in the step 84 to the first data of the D/A converters 40 and 41 or the first data of the D/A converters 40 and 42.

After all of the tracking adjustments are completed, the HF amplifier 13 is supplied with the output control voltage of the HF AGC circuit 30 which is obtained via the AGC 38 in a step 86. Hence, the step 86 returns the AGC circuit 30, the AGC 38 and the HF amplifier 13 back into the respective normal operating states, and the operation is ended in a step 87.

It is of course possible to add or subtract the offset voltages to or from the first data of the D/A converters 41 and 42 and leave the first datum of the D/A converter 40 as it is.

The first data used for the tracking adjustments are stored within a non-volatile memory (not shown) within the host computer 37, and the tuning speed can be increased thereafter by performing the tracking adjustments based on the stored first data.

The values with which the first data are increased or decreased in the flow charts shown in Figures 4A and 4B are not limited to "3" or "1", and other values may be used instead.

Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.

Claims

1. A superheterodyne television tuner comprising: tuned circuits independently provided in stages before and after a high frequency amplifier and within a local oscillator, each of said tuned circuits having a variable capacitance element and being controlled of a tuning frequency thereof by a control voltage applied to the variable capacitance element, tracking adjustments of said high frequency amplifier and said local oscillator being performed by varying the control voltages applied to the variable capacitance elements of the tuning circuits; level detecting means for detecting a level of a synchronizing signal within a video signal which is detected; and a control device supplied with the detected synchronizing signal level from said level detecting means for controlling a gain of said high frequency amplifier so that an input signal level of said high frequency amplifier does not exceed a saturation level thereof and for supplying to said variable capacitance elements control voltages which successively vary so as to obtain a tuning frequency at which the synchronizing signal level becomes a maximum.

2. A television tuner as claimed in claim 1 in which said level detecting means comprises a video detector for detecting an intermediate frequency video signal and an intermediate frequency automatic gain control circuit for supplying an automatic gain control voltage to said control device so that a level of a synchronizing signal within an intermediate frequency video signal detected in said video detector becomes constant.

3. A television tuner as claimed in claim 1 in which said control device supplies preset offset voltages to said variable capacitance elements after the tuning frequency at which the synchronizing signal level becomes the maximum is obtained, so that a frequency band width required for satisfactory signal reception and tuning is obtained.

4. A television tuner as claimed in claim 1 in which said control device comprises a keyboard for entering a channel selection datum related to a channel which is to be received, an analog-to-digital converter for subjecting the synchronizing signal from said level detecting means, digital-to-analog converter means, an automatic gain controller, and a host for supplying a control voltage to said high frequency amplifier via said automatic gain controller depending on a comparison result obtained by comparing an output datum of said analog-to-digital converter and a saturation level which is preset in said host computer so that said high frequency amplifier is first set to a maximum sensitivity and is thereafter successively reduced of the gain thereof by a predetermined quantity, and for supplying control voltages which successively vary independently to said variable capacitance elements via said digital-to-analog converter means depending on said comparison result so as to obtain the tuning frequency at which the synchronizing signal level becomes the maximum.

5. A television tuner as claimed in claim 4 in which said control device comprises first tracking adjustment means for simultaneously supplying to said variable capacitance elements control voltages which vary at identical rates so as to perform a rough adjustment of the tuning frequency, and second tracking adjustment means for supplying to said variable capacitance elements control voltages which successively vary so as to perform a fine adjustment of the tuning frequency.

6. Atelevision tuner as claimed in claim 5 in which said first tracking adjustment means comprises means for setting the gain of said high frequency amplifier to a maximum value, means for clearing the output datum of said analog-to-digital converter, means for supplying via said digital-to-analog converter means maximum control voltages so that tuning frequencies of said tuned circuits provided in the stages before and after said high frequency amplifier become maximum, means for reducing the gain of said high frequency amplifier so that the input signal level of said high frequency amplifier does not exceed the saturation level, and means for comparing present and previous output data of said analog-to-digital converter to store the present output datum in a case where the present output datum is greater than the previous output datum and to again reduce the gain of said high frequency amplifier in other cases so that the input signal level of said high frequency amplifier does not exceed the saturation level.

7. A television tuner as claimed in claim 5 in which said second tracking adjustment means comprises means for reducing the gain of said high frequency amplifier so that the input signal level of said high frequency amplifier does not exceed the saturation level, and means for comparing present and previous output data of said analog-to-digital converter to store the present output datum in a case where the present output datum is greater than the previous output datum and to again reduce the gain of said high frequency amplifier in other cases so thatthe input signal level of said high frequency amplifier does not exceed the saturation level.

8. A superheterodyne television tuner substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.