JPS61216436A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61216436A JPS61216436A JP5924285A JP5924285A JPS61216436A JP S61216436 A JPS61216436 A JP S61216436A JP 5924285 A JP5924285 A JP 5924285A JP 5924285 A JP5924285 A JP 5924285A JP S61216436 A JPS61216436 A JP S61216436A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- protective film
- handling
- semiconductor
- peripheral section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 230000002093 peripheral effect Effects 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims abstract description 13
- 230000007547 defect Effects 0.000 claims description 11
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- 239000003822 epoxy resin Substances 0.000 abstract description 4
- 229920000647 polyepoxide Polymers 0.000 abstract description 4
- 229920001721 polyimide Polymers 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 238000005336 cracking Methods 0.000 abstract description 2
- 230000035939 shock Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000208140 Acer Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に係り、特に半導体チップのハ
ンドリングな容易にするための半導体チップの周辺部の
補強方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a method for reinforcing the peripheral portion of a semiconductor chip to facilitate handling of the semiconductor chip.
C従来の技術〕
従来、半導体チップは篤2図(a)に示すように、半導
体チップの周辺部は伺も保護されていなかった。すなわ
ち、第2図において、1は半導体チップ、2は前記半導
体チップ1の側面、3は前層半導体チツア1上に形成さ
れた半導体装置の動作部分、4は前記半導体チップ1の
周辺部である。また第2図(b)は半導体チップIKハ
ンドリングにより損傷を生じたときの半導体チップ1の
斜視図で。C. Prior Art Conventionally, as shown in Figure 2 (a) of a semiconductor chip, the periphery of the semiconductor chip was not protected at all. That is, in FIG. 2, 1 is a semiconductor chip, 2 is a side surface of the semiconductor chip 1, 3 is an operating part of the semiconductor device formed on the previous layer semiconductor chip 1, and 4 is a peripheral part of the semiconductor chip 1. . Further, FIG. 2(b) is a perspective view of the semiconductor chip 1 when damage occurs due to semiconductor chip IK handling.
5aは前記半導体9−ツブ1の角部に生じた割れ等の欠
損、sbは同じく側面に生じたカケ、等の欠損である。5a is a defect such as a crack occurring at the corner of the semiconductor 9-tube 1, and sb is a defect such as a chip occurring on the side surface.
なお、以下の説明では、割・れ等の欠損5a、カケ等の
欠損sbvまとめて欠損5という。In the following description, defects 5a such as cracks and cracks, and defects sbv such as chips are collectively referred to as defects 5.
6はクラックである。゛「:
上に多数の素子”が形成され1次いでダイシングエ
(j半導体デバイスは、ウェハ工程においてウ
ェハ □程において各素子が分離され、組立
工程に移り、バツ□ケージングされて作られる。ダイシ
ング工程以降では1個々の半導体チップ1をハンドリン
グする必要があり、取分は半導体チップ1t−ダイボン
ドするときなど必ずハンドリングが伴う。このハンドリ
ングの際、第2図のよ5に半導体チップ1F)周辺s4
カー何も保護されていないと、ハンドリング時の多少の
衝撃で第2図(b)に示すように欠損5.′クラック6
等の損傷が生じ易い。特にGaAsデバイスにおいては
、シリコンデバイスの場合よりも欠損5やクラック6が
生じ易く歩留り低下の原因となっている。6 is a crack. ``A large number of elements'' are formed on the dicing process.
(j Semiconductor devices are manufactured by separating each element at the wafer step in the wafer process, moving to the assembly process, and packaging the semiconductor chips in boxes. After the dicing process, it is necessary to handle each individual semiconductor chip 1. The semiconductor chip 1t - Handling is always involved when die bonding.During this handling, as shown in Figure 2, the semiconductor chip 1F) surroundings s4
If the car is not protected, some impact during handling will cause damage to the car as shown in Figure 2(b). 'Crack 6
Such damage is likely to occur. In particular, in GaAs devices, defects 5 and cracks 6 are more likely to occur than in silicon devices, causing a decrease in yield.
上記のように1周辺部4が保護されていない従来の半導
体チップ1は、以上のよ5にハンドリングに伴う欠損5
.クラック6などの損傷が生じ易く、歩留り向上にも問
題となっていた。また以上の理由により、半導体チップ
1を扱う場合にもかなりの修練が必要であった。特にG
aAg基板の半導体チップにおいては、Si基板に比べ
て欠損5゜クラック6が生じ易く、歩留り向上にも大き
な問題となっていた。As described above, the conventional semiconductor chip 1 in which the peripheral portion 4 is not protected has the following damage due to handling.
.. Damage such as cracks 6 is likely to occur, which poses a problem in improving yield. Furthermore, for the above reasons, considerable training was required when handling the semiconductor chip 1. Especially G
Semiconductor chips using aAg substrates are more likely to suffer from 5° cracks 6 than Si substrates, which poses a major problem in improving yield.
この発明は、上記のような問題点を解消するため釦なさ
れたもので、半導体チップの欠損、クラック等の損傷を
生じにくくすることを目的とする。This invention has been made to solve the above-mentioned problems, and its purpose is to make it difficult for damage such as chipping and cracking to occur in semiconductor chips.
〔問題点を解決するための手段〕
この発明に係る半導体装置は、半導体チップの周辺部を
保護膜、例えばポリイミド、シリコン窒化膜、エポキシ
樹脂などからなる絶縁膜をコーティングしたものである
。[Means for Solving the Problems] In the semiconductor device according to the present invention, the peripheral portion of the semiconductor chip is coated with a protective film, for example, an insulating film made of polyimide, silicon nitride film, epoxy resin, or the like.
この発明においては、半導体チップの周辺部が保護膜に
よって保護されているから、ハンドリングによる欠損、
クラック等の損傷が生じにくくなる。In this invention, since the periphery of the semiconductor chip is protected by a protective film, there is no possibility of damage due to handling.
Damage such as cracks is less likely to occur.
第1図(a)、 (b)はこの発明の一実施例を示す
半導体チップの斜視図および正面図である。第1図にお
いて、第2図と同一符号は同じ部分を示し。FIGS. 1(a) and 1(b) are a perspective view and a front view of a semiconductor chip showing an embodiment of the present invention. In FIG. 1, the same reference numerals as in FIG. 2 indicate the same parts.
Tは前記半導体チップ10周辺部4に、この周辺部4V
保護するためにコーティングされた保護膜であり、例え
ばポリイミド、シリコン窒化膜、エポキシ樹脂等の絶縁
膜が用いられる。T is the peripheral area 4V of the semiconductor chip 10.
This is a protective film coated for protection, and for example, an insulating film such as polyimide, silicon nitride film, epoxy resin, etc. is used.
上記のような周辺部4を保護膜7で保護した半導体チッ
プ1は、半導体チップ1のハンドリング時に半導体チッ
プ1に対する衝撃が和らげられ。In the semiconductor chip 1 in which the peripheral portion 4 is protected by the protective film 7 as described above, the impact on the semiconductor chip 1 is softened when the semiconductor chip 1 is handled.
従来生じていたハンドリングに伴う欠損5やクラック6
等の発生を減少させることができる。Defects 5 and cracks 6 caused by handling that previously occurred
etc. can be reduced.
特にGaAs基板の半導体チップは、シリコン基板ウェ
ハに比べへき開性に富むため欠損やクラックが生じ易す
く、歩留りにも大きな影響を与えていた。したがって、
この発明による保護膜7を用いることにより1歩留りが
大きく向上する。In particular, semiconductor chips based on GaAs substrates have higher cleavage properties than silicon substrate wafers, and are therefore more prone to defects and cracks, which greatly affects yield. therefore,
By using the protective film 7 according to the present invention, the yield per unit is greatly improved.
なお、上記実施例では、半導体チップ1の周辺部40表
面だけを絶縁物をコーティングして保護するよ5にした
が、半導体チップ1の側面2をコーティングしてもよい
。また絶縁物をコーティングする工程は、チップの状態
においてもウェハの状態でもよい。In the above embodiment, only the surface of the peripheral portion 40 of the semiconductor chip 1 is coated with an insulator to protect it, but the side surface 2 of the semiconductor chip 1 may also be coated. Further, the step of coating the insulator may be performed in the state of a chip or in the state of a wafer.
また上記実施例では、半導体チップ1の欠損5やクラッ
ク6等の損傷の防止効果について説明したが、これに付
随して半導体チップ1の周辺部4の金楓パターンを押え
る効果もある〇
〔発明の効果〕
この発明は以上説明したとおり、半導体チップの周辺部
に絶縁物をコーティングして保護膜を形成したので、半
導体チップの周辺部はこの保護膜によって保護されるの
で、従来ハンドリング時に生じていた欠損やクラック等
の損傷の発生を防止することができ、作業性の向上とと
もに歩留りの向上も図れる利点がある。In addition, in the above embodiment, the effect of preventing damage such as defects 5 and cracks 6 on the semiconductor chip 1 was explained, but there is also an effect of suppressing the gold maple pattern on the peripheral part 4 of the semiconductor chip 1. [Effect] As explained above, this invention forms a protective film by coating the periphery of the semiconductor chip with an insulating material, so that the periphery of the semiconductor chip is protected by this protective film, which eliminates the problems that conventionally occur during handling. This has the advantage that damage such as chips and cracks can be prevented from occurring, and that workability and yield can be improved.
第1図(a) 、 (b)はこの発明の一実施例を示
す半導体チップの斜視図および正面図、第2図(a)。
(b)は従来の半導体チップを示す斜視図および欠損、
クラック等の損傷状mv説明する斜視図である。
図において、1は半導体チップ、2は半導体チップの側
面、3は動作部分、4は半導体チップの周辺部、Tは保
護膜である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大岩 増雄 (外2名)
第1図
7:億」1罠
第2図FIGS. 1(a) and 1(b) are a perspective view and a front view of a semiconductor chip showing an embodiment of the present invention, and FIG. 2(a) is a perspective view of a semiconductor chip. (b) is a perspective view showing a conventional semiconductor chip and defects;
FIG. 3 is a perspective view illustrating damage mv such as cracks. In the figure, 1 is a semiconductor chip, 2 is a side surface of the semiconductor chip, 3 is an operating part, 4 is a peripheral part of the semiconductor chip, and T is a protective film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 7: 100 million 1 trap Figure 2
Claims (1)
記半導体チップのハンドリングに伴う欠損やクラックを
防止するための保護膜としたことを特徴とする半導体装
置。1. A semiconductor device, characterized in that a peripheral portion of a semiconductor chip is coated with an insulating material to serve as a protective film for preventing defects and cracks caused by handling of the semiconductor chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5924285A JPS61216436A (en) | 1985-03-22 | 1985-03-22 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5924285A JPS61216436A (en) | 1985-03-22 | 1985-03-22 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61216436A true JPS61216436A (en) | 1986-09-26 |
Family
ID=13107721
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5924285A Pending JPS61216436A (en) | 1985-03-22 | 1985-03-22 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61216436A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6885522B1 (en) | 1999-05-28 | 2005-04-26 | Fujitsu Limited | Head assembly having integrated circuit chip covered by layer which prevents foreign particle generation |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49115654A (en) * | 1973-03-07 | 1974-11-05 |
-
1985
- 1985-03-22 JP JP5924285A patent/JPS61216436A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49115654A (en) * | 1973-03-07 | 1974-11-05 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6885522B1 (en) | 1999-05-28 | 2005-04-26 | Fujitsu Limited | Head assembly having integrated circuit chip covered by layer which prevents foreign particle generation |
US7347347B2 (en) | 1999-05-28 | 2008-03-25 | Fujitsu Limited | Head assembly, disk unit, and bonding method and apparatus |
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