JPS61216338A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the parasitic capacity of each semiconductor device and to improve the high-frequency characteristic thereof by a method wherein each semiconductor device in the state of a wafer is independently isolated from the state of a wafer. CONSTITUTION:These semiconductor devices are mutually coupled electrically through an impurity layer (2) in the state of a wafer respectively. The outer peripheral parts of each semiconductor device in this state of a wafer are diced up to reach a semi-insulative substrate (1), parts of the impurity layer (2) are deleted and each semiconductor device on the wafer is mutually isolated electrically. Then, measuring needles (19) and (19) are respectively abutted on each semiconductor device on the wafer and the electrical characteristic of each semiconductor device is measured. After this measuring ends, the semiconductor devices are again diced and each semiconductor device is made to independently isolate from the state of a wafer. There exists no isolating groove in the completed semiconductor devices. As a result, the parasitic capacity of each semiconductor device can be reduced.

Description

[Detailed description of the invention] g) Industrial application field The present invention relates to a method of manufacturing a semiconductor device.

←) Prior Art FIG. 2 is a top view of a semiconductor device manufactured by a conventional manufacturing method, and the 'ms diagram is a cross-sectional view taken along I--■ in FIG.

In Figure 182 and Figure 1s3, (1) is a G&A11 semi-insulating substrate as a semi-insulating layer, (2) is a semi-insulating substrate (1
), this impurity layer (2) is an impurity layer epitaxially grown on top of the n++ low resistance layer (3) and the n operation 11 (
4). (5) is a Wll isolation groove provided across the center of the impurity layer (2), and (6) is the impurity layer (
21 and surrounding this impurity layer (2)! This is the separation groove for I&2. This first. The isolation grooves (5) and (6) of $2 are connected to each other, and the lower ends of each reach the semi-insulating substrate (1). That is, the impurity layer (2).

1s1. Second separation groove (5) (6) K,! , Tute,
181 area (7) and 1!82 area (8),
electrically isolated.

(9) is the upper surface of the element and the first. Second separation groove (5) (6
) It is a polyimide film formed in a similar manner. (llIfi 1st
In the region (7), the active layer (4) and the Schottky electrode 111 of SL are connected to the Schottky electrode in the second region (8).
) in.

The active layer (4) is a second ν-Jet electrode which is joined to the active layer (4). This 'I&1. $2 Glue Yotsuto Electrode α [
The Schottky junction diameter of al) is determined by the 8102 film 0. u3 is l'g1's seat electrode (1G
1P11 region (7) surrounding the low resistance layer (3)
a first ohmic electrode, (14
1 surrounds the second Schottky electrode αυ, ! This is a second ohmic electrode that is Schottky-junctioned with the low resistance layer (3) in the region (8) of 82. ttS is $1 that connects the first ohmic electrode α3 and the second Schottky electrode a
lead electrode (161 is the second ohmic electrode (1
41 and the first Schottky electrode [alpha]. As is clear from the above configuration, 1s
A diode (17) of iJl is provided in the region (7) of No.1.

A second diode frame is provided in the second region (8). And the first. Second diode? ) (lυ are connected in antiparallel to each other by the lead electrode α9 of Ml and 's2.

FIG. 4 is a top view of the semiconductor device shown in FIG.

In FIG. 9J4, a large number of the semiconductor devices shown in FIGS. 2 and 3 are regularly formed in the shape of a substrate above the semi-insulating square. The manufacturing process up to FIG. 4 is described in detail in, for example, Japanese Unexamined Patent Publication No. 59-161836.

It will be omitted in the following explanation.

By the way, in the wafer state of FIG. 4, the individual semiconductor devices are electrically isolated from each other by the second isolation groove (6)K. Therefore, first, in FIG. 4, as shown in FIG. The characteristics of each semiconductor device are measured by bringing the measuring needle a9 (II) into contact with the second lead electrode n5tte.

When this measurement is completed, first, as shown in Figure $6, the individual semiconductor devices are independently separated by gilling to obtain the semiconductor devices shown in Figures %j12 and 3.

(c) Problems to be Solved by the Invention In the conventional manufacturing method, a second isolation trench (6) is required to electrically isolate individual semiconductor devices from each other in a wafer state. However, at the time of completion of the semiconductor device, the second separation groove (6) is not formed as shown in FIG.

As shown in FIG. 3, when included in a semiconductor device, extra parasitic capacitance is generated in this @2 isolation trench (6).
This had an adverse effect on the high frequency characteristics of semiconductor devices.

B) Means for solving the problems The present invention has been made in view of the above-mentioned problems.
What is the gist of it?

forming a plurality of semiconductor devices including a semi-insulating layer and an impurity layer formed on the semi-insulating layer in a wafer state without performing electrical element isolation between each semiconductor device;
removing the impurity layer in the outer periphery of each semiconductor device until it reaches the semi-insulating layer to electrically isolate the semiconductor devices; and electrically measuring each semiconductor device. and a step of independently separating each of the semiconductor devices from a wafer state.

(E) Function: There is no need for isolation trenches that electrically isolate one semiconductor device from another semiconductor device in a working wafer state. Therefore,
At the completed semiconductor device.

Since the isolation trench does not exist, parasitic capacitance is reduced.

(to) Examples! FIG. J1 is a top view of a semiconductor device manufactured according to an embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along the line -■ in FIG.

In FIG. 131 and FIG. 7, the same parts as in FIG. IJ2 and FIG. ll! The semiconductor devices in Figure 1, 'li & Figure 7 are! The difference from the semiconductor devices in FIGS. 82 and 3 is that the impurity 1111(2)t-surrounding IJ&2
This is where the separation groove (6) is not provided. That is, the first and 1jI2 regions ()) (8) are electrically isolated only by the first isolation groove (5).

FIG. 8 is a top view of the semiconductor device shown in FIG. Note that the manufacturing steps up to FIG. 8 will be omitted.

Specifically, the size of the semiconductor device of the seventh factor in FIG. 1 is as follows:
The long side is 360 m, the short side is 260 μm, and the height is 100 m. The width of the one-separation groove (5) is 8 #m, in the wafer state shown in Figure 's8.

Between adjacent separation grooves (5) (5)..., 20 active W
are spaced apart.

In the wafer state of FIG. 8, the semiconductor devices are electrically connected to each other through the impurity layer (2). Therefore, first, as shown in FIG. fi9, the outer peripheral portion of each semiconductor device in a wafer state is diced until it reaches the semi-insulating substrate (1), and the impurity layer (2) t- is removed from this portion. First, the wafer is washed with ultrapure water to remove dust and the like, and the semiconductor devices on the wafer are electrically isolated from each other. At this time, the width of dicing is 30. cjm
I went there.

Next, as shown in FIG. 10, the measuring needle (L9al) is brought into contact with the semiconductor device on the wafer to measure the electrical characteristics of the semiconductor device. When this measurement is completed, as shown in FIG. , Dice the same part as the dicing part in FIG. 189 again and separate it into eight semiconductor devices alt-que.
The semiconductor device It shown in FIG. 1 and FIG. 7 is obtained.

(G) Effects of the Invention According to the present invention, there is no need for separation grooves for electrically separating semiconductor devices in a wafer state from each other. Therefore, since the isolation trench is not included in each completed semiconductor device, the parasitic capacitance can be reduced and the high frequency characteristics of the semiconductor device can be improved.

Also, there is no need to provide the separation groove.

The size of the semiconductor device can be reduced, and the area can be utilized to the maximum extent possible.

[Brief explanation of drawings]

Figure s1 is a top view of a semiconductor device manufactured by an embodiment of the present invention, Figure 2 is a top view of a semiconductor device manufactured by a conventional manufacturing method, and Figure '@3 is a top view of a semiconductor device manufactured by an embodiment of the present invention.
②Cross sections, Figures 4 to s6 are manufacturing process diagrams of the semiconductor devices shown in Figures 2 and 3. Figure 7 is a sectional view taken along ■-■ in Figure 1, and Figures 918 to 11 are! FIG. 7 is a manufacturing process diagram of the semiconductor device shown in FIGS. 1 and 7; (1)...Semi-insulating substrate (semi-insulating layer), +23...
- Impurity layer, (3)...low resistance layer, (4)...operating layer.

Claims (1)

[Claims] (1) A process of forming a plurality of semiconductor devices including a semi-insulating layer and an impurity layer formed on the semi-insulating layer in a wafer state without electrically separating the semiconductor devices between the individual semiconductor devices. a step of removing the impurity layer in the outer periphery of each of the semiconductor devices until it reaches the semi-insulating layer to electrically isolate the semiconductor devices; and performing electrical measurements of each of the semiconductor devices. 1. A method for manufacturing a semiconductor device, comprising: a step of performing a wafer, and a step of independently separating each of the semiconductor devices from a wafer state.