JPS60145660A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the yeild of products by obtaining n type layers with less defect by a method wherein the n type layer of the titled device of n<+>p-i-n-p<+> structure is formed by the diffusion method. CONSTITUTION:n<+> Type layers 6 are formed on both main surfaces by deeply diffusing the V-group element such as phosphorus to a low concentration n type (i type) semiconductor substrate 1, and the width of the i type layer 1 is adjusted by lapping removal by including one n<+> type layer 6. Then, a p type layer 2 is formed by diffusing the III-group element such as Ga. The surface part of the n<+> type layer 6 where the impurity concentration is high is removed by lapping, thus leaving an n type layer 6a; then, a p<+> type layer 4 is formed by diffusing the III-group element such as boron only to the surface part. n<+> Type layers 5 are formed by selective diffusion of the V-group element such as phosphorus only on the side of the p type layer 2 into a required pattern. Since the n<+>p-i-n-p<+> structure is formed only by the diffusion method, the manufacturing cost can be reduced.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a semiconductor device having an np+ structure. A method for manufacturing an npxnpm gate turn-off thyristor (GTO) will be described below as an example.

[Prior art]

Figure 1 A-E shows n grown by conventional epitaxial growth method.
FIG. 2 is a cross-sectional view illustrating the main stages of the PINP+ structure GTO manufacturing method, but only the wafer processing steps thereof will be explained.

First, a low-concentration n-type (type 1) semiconductor substrate (1) with an impurity concentration of about 10 impurities/cm3 as shown in FIG.
As shown in the figure, a p-type layer (2) is formed on the amphiphilic surface by diffusing a Group Ⅰ element such as gallium (Ga), and the p-type layer (2) formed on one of the main surfaces is included. , the portion indicated by the dashed line shown in the figure is removed by wrapping. Next, as shown in FIG.
An n-type layer (3) having an impurity concentration of about 100% is formed. The diffusion profile at this point is shown in FIG. Next, the first
As shown in the diagram, group III elements such as boron (B) are
Diffused to the shape layer (3) side, surface concentration 1020 pieces/c
A p+ type layer (4) of m3 or more is formed, and then Fig. 1E
As shown in K, Group V elements such as P are selectively diffused into the required pattern only on the p-type layer (2) side to form an n-type layer (5) with a surface concentration of 1020 elements/Qm'' or more. form.

This n pinp structure GTO was devised to increase the blocking voltage inside the semiconductor element without increasing the forward ON voltage. Since the forward ON voltage is almost determined by the width of the type 1 layer (1) in FIG. 1E, it is necessary to make the width as narrow as possible to lower the forward ON voltage. This is why the hatched portion shown by the dashed dotted line is removed by wrapping at the stage shown in FIG. 1B.

However, when the width of this i-type layer (1) is narrowed, the busy depletion layer expands when a high voltage is applied, and this extends to the opposing junction, causing a bunch-through phenomenon, which increases the blocking voltage. It disappears. Therefore, in order to prevent the depletion layer from spreading, the n-type layer (3) having a higher impurity concentration than the 1-type layer (1) is provided. In actual design, if a large electric field is applied to the n-type layer (3), the blocking voltage will drop due to new avalanche breakdown, so it is necessary to adjust the width of the i-type layer (1) appropriately, and the width of the i-type layer (1) must be adjusted appropriately. The impurity concentration of the n-type layer (3) is approximately 10 impurities/a in order to further form the p+-type layer (4) in this layer.
It can be kept to about m.

However, the conventional method of producing the n-type layer (3) by epitaxial growth has several drawbacks. First of all, in a power semiconductor device such as a GTO, the thickness of the n-type 1i(3) formed by epitaxial growth is considerably thick. Therefore, K defects are likely to occur in the n-type layer (3), which lowers the yield of the product in manufacturing. Furthermore, an epitaxial growth apparatus is required, which also increases the product price.

[Summary of the invention]

This invention was developed in order to eliminate the drawbacks of the conventional devices as described above, and it is possible to obtain an n-type layer with fewer defects by forming the n-type layer of an n''pinp+ structure semiconductor device by a diffusion method. The present invention provides a method for manufacturing a semiconductor device which increases the yield of the product and is extremely advantageous in terms of product cost and manufacturing simplicity since manufacturing is performed using only a diffusion device.

[Embodiments of the invention]

Figures 3A to 3E show npinp which is an embodiment of this invention.
FIG. 2 is a cross-sectional view showing the state at the main stages of the method for manufacturing structure G'['O, in order to explain only the diffusion process.

First, the impurity concentration shown in Figure 3A is 1014 particles/cm3.
Figure 3B on a low concentration n-type (i-type) semiconductor substrate (1)
As shown in Figure 2, a group V element such as phosphorus (P) is deeply diffused to form an n+ type layer (6) on the amphiphilic surface, including the n+ type layer (6) formed on one of the main surfaces. Then, remove the wrapping from the hatched part shown in the dashed line.
Adjust the width of the i-shaped layer (1). Subsequently, as shown in FIG. 3CK, a p-type layer (2) is formed by diffusing a Group Ⅰ element such as C)a only from the surface which has been removed by lapping. The diffusion profile at this point is shown in FIG. Next, n
Although it is necessary to form a p+ type layer on the surface of the + type layer (6), it is difficult to form it if the surface impurity concentration of the n+ type layer (6) is too high. The surface area shown by the hatching is removed by lapping. In FIG. 4, the portion to be removed by wrapping is shown hatched with a dashed dotted line. This lapping removal leaves an n-type layer (6a) with a surface impurity concentration of 101
Keep it to about 8 pieces/am or less. Next, as shown in the third diagram, boron (B) is applied only to the surface of this n-type layer (6a).
A p+ type layer (4) is formed by diffusing group Ⅰ elements such as. Next, as shown in FIG. 3E, a group V element such as P is selectively diffused into a desired pattern only on the p-type layer (2) side to form an n+-type layer (5). The diffusion process is complete.

The method of this embodiment differs from the conventional method explained in FIG.
As shown in Figure C, in order to further create a p+ type layer (4) on the n+ type layer (6), the surface portion of the n+ type layer (6) is removed by lapping, and the surface impurity concentration is reduced to 1000 impurities/cm3.
There are two points: to make the n-type layer (6a) to a certain degree.

The n-type layer (6) can be formed by a diffusion method by using a diffusion device to deeply diffuse a group V element such as P by increasing the drive time. In addition, in order to suppress the surface impurity concentration of the n-type layer (6a) to about 1018 particles/cm3, K measures the diffusion profile of the wafer in the state shown in Figure 3C using a diffusion resistance measuring device, and determines the surface impurity concentration. The n+ layer (6) may be lapped until the concentration is at its desired value.

Next, as can be seen by comparing FIG. 2 and FIG. 4, the diffusion profiles of the n-type layer are quite different. The slope of the impurity concentration on the 1-type layer (1) side of the n-type layer (3) formed by the epitaxial growth method in the conventional example is steep;
Although the subsequent diffusion process for forming the p+ type layer (4) and the n+ type layer (5) is somewhat slow, the n-type layer (1) of the n-type layer (6a) formed by the diffusion method in the example is
The slope of the impurity concentration on the ) side is even gentler. However, even considering the subsequent diffusion process, the impurity concentration from the boundary between the n-type layer (6a) and the n-type layer (1) to the junction between the n-type layer (6a) and the p+-type layer (4) is 3. There is a difference of 4 orders of magnitude, and if the thickness of the n-type layer (6a) is appropriately selected, there will be no problem with the bunch-through phenomenon. vice versa,
Since the avalanche breakdown voltage is a decreasing function with respect to the impurity concentration, if the depletion layer spreads to the n-type layer (6a) when a high voltage is applied, the impurity concentration on the type 1 layer (1) side of the n-type layer (6a) will decrease. A gentler slope is advantageous in that the blocking voltage can be increased because the potential gradient does not change as sharply as the impurity concentration increases. Therefore, it can be seen that the profile trap caused by forming the n-type layer (6a) by the diffusion method is eliminated and there is no problem.

In addition, in the above embodiment, the reverse blocking n"pinp+ structure GTO
We have explained the manufacturing method for the anode short-circuit type n”pin
The present invention is applicable not only to the p-structure G'i'O1 and other n+pinp+ structure silicon risks, but also to the manufacturing method of general conductor devices having the n''pinp+ structure.

〔Effect of the invention〕

As explained above, 1 In this invention, only the diffusion method is used
Since a pinp+ structure is formed, an n-type layer with few defects can be obtained, and a reduction in manufacturing costs and an improvement in product yield can be expected.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view showing the state at the main stages of the conventional manufacturing method of n+pinp+ structure GTO to explain only the wafer processing process, and Figure 2 is the same as Figure 1
Diagram showing the diffusion profile of the wafer at the stage of
FIG. 3 is a sectional view showing the main stages of an embodiment of the present invention in order to explain only the wafer processing process, and FIG. 4 is a diagram showing the diffusion profile of the wafer at the stage of FIG. 3C. be. In the figure, (1) is type 1 conductor wafer, (2) is p
(4) is a P+ type semiconductor layer, (5) is an n+ type semiconductor layer (formed in the second step), (6) is an n+ type semiconductor layer (formed in the second step), (6a) is an n-type semiconductor layer. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

[Claims] (1) Group V elements are deeply diffused from the ambidextrous surface of an n-type (referred to as i-type) semiconductor wafer with a low impurity concentration to form an n-type (referred to as n+ type) semiconductor layer with a high impurity concentration to form an n+in+ structure. The first step is to remove the n+ type semiconductor layer on one main surface of the semi-dedicated tube 1 having the n+in+ structure and a part of the i shadow region following this by lapping to form the in+ structure. Step: Diffusing group m elements only on the main surface on the i-shaded region side of the in+ structure semiconductor wafer to form a p-type semiconductor layer having an impurity concentration intermediate between the i-shade region and the n+-type semiconductor layer. In the third step, the surface of the n+ type semiconductor layer on the pin+ structure semiconductor wafer is removed by lapping to form an n type semiconductor wafer with a surface impurity concentration similar to that of the p type semiconductor layer. The fourth step is to leave the semiconductor layer and form a pin structure, in which group m elements are diffused only on the main surface on the n-type semiconductor layer side of the pin-structured semiconductor wafer to form a p+ type semiconductor layer with a high impurity concentration. a fifth step of forming a pinp+ structure with the semiconductor wafer, and diffusing a group V element only on the main surface on the p-type semiconductor layer side of the semiconductor wafer having the pinp+ structure with the n
A method for manufacturing a semiconductor device, comprising a sixth step of forming a +-type semiconductor layer to form an n"pinp" structure.