JPS6110276A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To contrive the reduction in number of the manufacturing process and the improvement of manufacturing yield by a method wherein a buffer layer that covers crystal defects generating in a gate layer channel is formed collectively with the gate layer by diffusing impurities through a thin oxide film in order to form the former layer in manufacture of a semiconductor element having a buried gate. CONSTITUTION:After formation of an oxide film, the window of the part corresponding to patterns of a P2<++> layer and a P2<+> buffer layer is bored in a P1N1P2 structure by a photo resist process. Next, a thinner oxide film than the oxide film formed in the former process is formed by reoxidation. Then, the window of the part corresponding to the P2<++> layer pattern is bored by a photo resist process, and the P2<+> buffer layer and the P2<++> layer are formed at the same time by selective diffusion of boron with the patterns of the two layers. Since the P2<+> buffer layer is formed by boron diffusion through a thin oxide film in such a manner, one time boron diffusion is sufficient.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device having a buried gate 1.

(Prior Art) In recent years, due to demands for higher efficiency and smaller size of devices, semiconductors with self-extinguishing ability have been attracting attention in place of conventional thyristors that require commutation circuits. Among these, gate turn-off thyristors (hereinafter referred to as GTO) can easily be made to have a high breakdown voltage and a large current compared to other semiconductors, and their practical use is progressing.

By the way, GTO has a surface gate GT due to its gate structure.
It is divided into a buried gate GTO and a buried gate GTO.

Surface gate) GTO has a structure in which an intricately shaped gate electrode is exposed on the element surface), while buried gate GTO has a PL% concentration diffusion layer (buried gate) used as a gate in the P space layer by epitaxial growth. The embedded structure shown in FIG. 3 is obtained. In the figure, G is a gate electrode,
K is a cathode electrode, A( is an anode electrode, P2 is a space layer, P2- is an epitaxial growth layer, and P2++ is a buried gate layer.

This embedded GTO can have a higher breakdown voltage at the cathode-emitter junction than the surface GTO, and can improve turn-off characteristics by applying a large reverse voltage to the cathode-emitter junction at turn-off. In addition, miniaturizing the gate structure to improve the turn-off characteristics is extremely easy to achieve with buried gate G゛Cθ (1, becomes.

By the way, in a buried gate (GTO), the turn-off characteristics are improved by increasing the impurity concentration of the P2++ expansion coral used as the gate and lowering the resistance of the buried gate by decreasing the sheet resistance. This is because a large gate current can be drawn out. However, if the resistance of the buried gate is significantly reduced, crystal defects Cd5f will occur in the channel as shown in FIG. These defects shorten the lifetime of minority carriers in the P2 base, thereby deteriorating the turn-off characteristics and causing variations in characteristics within and between devices. In addition, if the channel width is made smaller than a certain range, the turn-off characteristics will deteriorate rapidly, so these defects will impair the characteristic of buried gate GTo, which is that the channel can be easily miniaturized. In order to eliminate the various adverse effects caused by this, the applicant of the present invention has already proposed a gate structure as shown in FIG. 5 (Patent Application No. 59-66873). In addition to the conventional buried gate structure, this structure uses a P
2+ buffer layer is provided. Since the P24° buffer layer has a lower impurity concentration and a higher sheet resistance than the P2++ layer, the occurrence of crystal defects caused by the P2 buffer layer can be ignored. As a result, all the channel parts operate effectively, and the uniformity of characteristics within and between elements is greatly improved. Furthermore, since the channel width can be reduced without impairing the turn-off characteristics compared to the conventional method, the degree of freedom in element design for improving turn-off characteristics is greatly expanded.

(Problems to be Solved by the Invention) A GTO with a structure in which a P2+ buffer layer is provided requires an oxidation process, a photoresist process, a diffusion process, a drive-in process, etc. to form the P2+ buffer layer as part of the device manufacturing process. do. Such additional steps have the problem of increasing costs and lowering the manufacturing yield compared to GT OK having a conventional structure.

(Means and effects for solving the problems) The present invention is a manufacturing method for simultaneously forming a gate layer and a buffer layer by one-time impurity diffusion. A PNP structure is formed, and after double-sided cultivation, a window is opened in the pattern of the gate layer and buffer layer using a photoresist process, a thin oxide film of medium thickness is formed through reconsideration, and a window is opened in the gate layer pattern part using a photoresist process. death,
The gate layer is formed by 1IIj tangential diffusion by selectively and uniformly diffusing impurities into corresponding portions of the gate layer and buffer layer, and the buffer layer is simultaneously formed by diffusion through a thin oxide film.

(Actual #1 example) A practical example of the present invention will be explained together with a conventional manufacturing method.

FIG. 2 shows a conventional method for providing a buried gate GTOICP2+buffer layer. As shown in the same figure (A), n
PINI is created by diffusing gallium from both sides of a shaped silicon substrate.
A P2 structure was obtained and oxidized on both sides as shown in (b).
After forming 5to2, a photoresist process is performed and then P2 is formed.
Selectively diffuse boron into the layer pattern to form P2
form a layer. Next, as shown in (C), oxidation @
5i02 is formed and P2 is formed through a photoresist process.
+ Selectively diffuse boron into the buffer layer pattern 7 to form P2
+ Form a buffer layer. Next, as shown in (d),
An oxide film is formed, and the oxide film in the portion to be epitaxially grown is removed by a photoresist process, and a p2-/ie layer is formed by epitaxial growth to bury a P2+1 layer and a P2+ buffer layer, as shown in FIG.

As described above, in order to form a P2+ buffer layer to eliminate the influence of crystal defects in the P2 layer, a step of forming a P2 buffer layer is required after the step of forming a P2+1 layer. On the other hand, the process shown in FIG. 1 in this embodiment is shown in FIG. 2(b).

This is an alternative to the step shown in (c).

In FIG. 1(A), after forming 111810z oxide for the PINIP2 structure, a photoresist process is used to open windows in the portions corresponding to the patterns of the P2++ layer and P2+ buffer layer, and then in FIG. 1(b). As shown, the oxide film formed in step 8i (a) also forms a thin oxide film [:5iOz] by reoxidation. Next, as shown in (e), a window is opened in the portion corresponding to the P2++ layer pattern by a photoresist process, and as shown in (d), a window is opened in the portion corresponding to the P2++ layer pattern. A P2+ buffer layer and a P22 overlayer are simultaneously formed by selectively diffusing boron with pins in the ++ layer and the P2 buffer layer.

In this way, in this example, boron is diffused through a thin oxide film to form the 2+ buffer layer, so one diffusion of boron is performed in contrast to the two times of boron diffusion in the conventional process (Fig. 2, c). Boron diffusion will suffice.

Note that the thickness of the rough oxide film (stOz) is determined from the boron diffusion conditions, the surface concentration of the P2+ buffer layer, and the diffusion depth. Specifically, heat was removed from boron at 1240'C for 1 hour.
In the case of diffusion under slow cooling conditions, the sheet resistance of the P2+1 layer is t; f, o, 6Ω/mouth, and the film thickness is 0.5
The sheet resistance of the P2+ buffer layer formed by boron penetrating the μm oxide film [5iOz] is 15Ω/
D was obtained. In this case, BN was used as the diffusion depth. Furthermore, it was confirmed that the number of crystal defects entering the channel from the P2+ buffer layer was sufficiently small and exhibited an extremely good percent property.

It should be noted that the present invention can be applied not only to a simple GTO but also to a method of manufacturing other semiconductor devices having buried gates to manufacture devices in which the influence of crystal defects has been removed.

(Effects of the Invention) According to the present invention, when manufacturing a semiconductor device having a buried gate, impurity diffusion is carried out through a thin oxide film to form a buffer layer that covers and hides convex defects occurring between gate layer channels. Rounding that is formed at once during layer formation is effective in reducing the number of manufacturing steps and improving yield.

[Brief explanation of the drawing]

Figure 1 is a manufacturing process diagram of the main parts showing one embodiment of the present invention, Figure 2
The figure is a diagram of the conventional main part manufacturing process, Figure 3 is a GTO structure diagram with a buried gate, and Figure 4 is the crystal defect C in Figure 3.
FIG. 5 is a diagram showing the structure of an extreme part showing daf, and FIG. 5 is a diagram of the structure of an extreme part having a buffer layer. A... Anode electrode, K... Cathode electrode, G...
・Gate electrode, P2 ... Embedded gate layer, P2
-...Epitaxial growth layer, P2...Base layer,
5i02...Oxide film, [EiiO21...Thin oxide film. Figure 2 id2

Claims (1)

[Claims] In a semiconductor device having a buried gate layer with a high impurity concentration in the base layer and a buffer layer with a low impurity concentration that covers a region where crystal defects that invade the channel portion of the gate layer occur, the oxide film of the base layer is A window is formed in the pattern of the buffer layer, and then a window is formed in the thin oxide film formed by re-oxidation according to the pattern of the buffer layer, and the pattern portions of the gate layer and buffer layer are selectively etched. A method for manufacturing a semiconductor device characterized by diffusing impurities at a high concentration.