JPS63236366A - Vertical field-effect transistor - Google Patents
Vertical field-effect transistorInfo
- Publication number
- JPS63236366A JPS63236366A JP62068814A JP6881487A JPS63236366A JP S63236366 A JPS63236366 A JP S63236366A JP 62068814 A JP62068814 A JP 62068814A JP 6881487 A JP6881487 A JP 6881487A JP S63236366 A JPS63236366 A JP S63236366A
- Authority
- JP
- Japan
- Prior art keywords
- thickness
- mum
- substrate
- effect transistor
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims 1
- 230000001681 protective effect Effects 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、縦形構造を有する電界効果トランジスタに係
り、特に低損失化に好適な電界効果トランジスタに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor having a vertical structure, and particularly to a field effect transistor suitable for reducing loss.
従来の装置は、特開昭５７−４２１°６４号に記載のよ
うに、縦形ＭＯ８ＦＥＴを構成する低濃度ドレイン領域
となるエピタキシャル層底部の不純物濃度をその上部よ
りも大きくするなどして、低損失化を図っていた。しか
し、該エピタキシャル層の基板となる高濃度ドレイン領
域に関しては、低損失化についての配慮がなかった。Conventional devices achieve low loss by making the impurity concentration at the bottom of the epitaxial layer, which becomes the low concentration drain region of the vertical MO8FET, higher than that at the top, as described in JP-A No. 57-421°64. He was trying to make the world a better place. However, with regard to the highly doped drain region that serves as the substrate of the epitaxial layer, no consideration has been given to reducing loss.
上記従来技術は、高濃度ドレイン基板の低損失化につい
ては配慮されておらず、縦形ＭＯ３ＦＥＴの超低損失化
を図るうえで問題があった。The above-mentioned conventional technology does not take into account the reduction in loss of the highly doped drain substrate, and there is a problem in achieving ultra-low loss in the vertical MO3FET.
本発明の目的は、上記縦形ＭＯ８ＦＩＥＴの損失を低減
することである。An object of the present invention is to reduce the loss of the vertical MO8FIET.
上記目的は、縦形’ＭＯ３ＦＥＴの高濃度ドレイン基板
をエツチングにより薄くすることにより、達成される。The above object is achieved by thinning the highly doped drain substrate of the vertical MO3FET by etching.
縦形ＭＯ３ＦＥＴの高濃度ドレイン基板を薄くすること
により、該ＭＯ３ＦＥＴのオン抵抗を低減することがで
きる。また、半導体基板が薄くなったことで、半導体部
分の熱抵抗が低減でき、素子の電力容量を向上すること
ができる。By making the highly doped drain substrate of the vertical MO3FET thinner, the on-resistance of the MO3FET can be reduced. Furthermore, since the semiconductor substrate is made thinner, the thermal resistance of the semiconductor portion can be reduced, and the power capacity of the element can be improved.
以下、本発明の一実施例を第１図により説明する。第１
図は、大電力用の縦形パワーＭＯ３ＦＥＴ主要部の断面
構造図である。１はｎ形高不純物濃度基板で、不純物濃
度が５Ｘ１０１８０−３、厚さが３μｍである。２はｎ
形エピタキシャル層を有する低不純物濃度ドレイン領域
で、不純物濃度が６×１０１８０−８、厚さが８μｍで
ある。３はｐ形ベース領域で、表面不純物濃度が４ Ｘ
１０１７ａｍ−’、深さが２μｍである。４はｎ形ソ
ース領域で、表面不純物濃度が３ Ｘ １０ ”ｃｘｓ
−”、深さが０．５ μｍである。５はゲート酸化膜で
厚さが、２０ｎｍ、６は多結晶シリコンのゲート電極で
、厚さが０．３μｍである。７は保護絶縁膜で厚さが０
．６μｍである。８はソース電極で厚さ３μｍのアルミ
ニウムより成っている。９はドレイン電極で厚さが２μ
ｍである１本実施例によれば、ｎ形高不純物濃度基板１
の厚さが、低濃度ドレイン領域２の厚さに比べて薄いこ
とが特徴となっている。An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a cross-sectional structural diagram of the main part of a vertical power MO3FET for high power. 1 is an n-type high impurity concentration substrate with an impurity concentration of 5×10180-3 and a thickness of 3 μm. 2 is n
The low impurity concentration drain region has a type epitaxial layer, the impurity concentration is 6×10180−8, and the thickness is 8 μm. 3 is a p-type base region with a surface impurity concentration of 4
1017 am-', and the depth is 2 μm. 4 is an n-type source region with a surface impurity concentration of 3×10”cxs
-", the depth is 0.5 μm. 5 is a gate oxide film with a thickness of 20 nm, 6 is a polycrystalline silicon gate electrode with a thickness of 0.3 μm. 7 is a protective insulating film. Thickness is 0
．． It is 6 μm. Reference numeral 8 denotes a source electrode made of aluminum with a thickness of 3 μm. 9 is the drain electrode with a thickness of 2μ
According to this embodiment, the n-type high impurity concentration substrate 1
It is characterized in that its thickness is thinner than that of the low concentration drain region 2.
本実施例では、５ｍ角のパワーＭＯ５ＦＥＴを製作した
。その結果、ドレイン耐圧６０Ｖドレイン電流３０Ａ、
オン抵抗６ｍΩのパワーＭＯ５ＦＥＴが得られた。これ
らの特性は、従来構造のものに比べて、オン抵抗が約１
０％低減できている。In this example, a 5 m square power MO5FET was manufactured. As a result, drain breakdown voltage is 60V, drain current is 30A,
A power MO5FET with an on-resistance of 6 mΩ was obtained. These characteristics mean that the on-resistance is approximately 1% higher than that of the conventional structure.
It has been reduced by 0%.
第２図は、本発明の他の実施例で、製造工程の一部を示
す図である。（ａ）が基板エツチング前のパワーＭＯ３
ＦＥＴの断面構造図、（ｂ）が基板領域１を厚さ３μｍ
、ウェーハ厚さ約１１７μｍにエツチングした図である
。このように、パワーＭＯ３ＦＥＴとしてソース電極を
形成後、基板をエツチングした。しかる後、基板裏面よ
りイオン打込み１０を行い、結晶欠陥層によるライフタ
イムキラー１１を導入した。イオン打込み条件は、イオ
ン種ヘリウム、エネルギ３ Ｍ ｅ Ｖ、打込み景ｌＸ
１０１”Ｑｌ−”である。イオン打込み後、水素中で、
３５０℃、３０分間の熱処理を行った。FIG. 2 is a diagram showing a part of the manufacturing process in another embodiment of the present invention. (a) is the power MO3 before substrate etching
Cross-sectional structure diagram of FET, (b) shows substrate region 1 with a thickness of 3 μm.
, which is etched to a wafer thickness of approximately 117 μm. After forming the source electrode of the power MO3FET in this manner, the substrate was etched. Thereafter, ion implantation 10 was performed from the back side of the substrate to introduce a lifetime killer 11 formed by a crystal defect layer. The ion implantation conditions were: ion species helium, energy 3M e V, implantation direction 1X.
101"Ql-". After ion implantation, in hydrogen,
Heat treatment was performed at 350°C for 30 minutes.
本実施例では、基板を薄くエツチングしているので、裏
面より均一にライフタイムキラーが導入できる。その結
果１表面チャネル領域に影響を与えないで、基板ダイオ
ードの逆方向回復時間を低減できるという利点が生ずる
。本実施例の基板ダイオードの逆方向回復時間は、０．
２μＳ であり、イオン打込み前の１．２μｓ に比べ
、格段に低減できた。In this embodiment, since the substrate is etched thinly, the lifetime killer can be uniformly introduced from the back side. As a result, an advantage arises in that the reverse recovery time of the substrate diode can be reduced without affecting the first surface channel region. The reverse recovery time of the substrate diode of this example is 0.
The time required was 2 μS, which was significantly reduced compared to 1.2 μs before ion implantation.
次に、本発明の他の実施例を第３図を用いて説明する。Next, another embodiment of the present invention will be described using FIG.
基板を薄くエツチングした縦形パワーＭＯ３ＦＥＴを熱
伝導の良い１２の銅基板に接着する。A vertical power MO3FET whose substrate is thinly etched is bonded to 12 copper substrates with good thermal conductivity.
半導体基板の厚さは全体で１０μｍである。従って、電
力印加による発熱部が放熱基板１２に近いので従来の基
板Ｄ２ｏｏμｍの場合に比べて、熱抵抗を約３０％低減
できた。The total thickness of the semiconductor substrate is 10 μm. Therefore, since the heat generating part due to power application is close to the heat dissipation substrate 12, the thermal resistance can be reduced by about 30% compared to the case of the conventional substrate D2ooμm.
第４図は、基板を薄くエツチングした縦形パワーＭＯ３
ＦＥＴをフェースダウンさせて放熱基板１２に接着する
構造としたものである。この場合、ソース電極１３を銅
電極とし、放熱基板１２との接着性の向上を図った６図
に示すような半導体基板１４を放熱基板１２ではさみ込
む構造にすることで、電界効果トランジスタの活性部以
外の直列抵抗が低減でき、その結果、オン抵抗の極めて
小さいパワーＭＯ５ＦＥＴが製作できた。Figure 4 shows a vertical power MO3 with thinly etched substrate.
The structure is such that the FET is bonded face down to the heat dissipation substrate 12. In this case, the source electrode 13 is made of a copper electrode, and the semiconductor substrate 14 is sandwiched between the heat dissipation substrates 12 as shown in FIG. As a result, we were able to manufacture a power MO5FET with extremely low on-resistance.
本発明によれば、縦形パワーＭＯＳＦＥＴの半導体基板
が能動領域の厚さよりも薄くできるので直列抵抗の低減
、熱抵抗の低減に効果がある。According to the present invention, the semiconductor substrate of the vertical power MOSFET can be made thinner than the thickness of the active region, which is effective in reducing series resistance and thermal resistance.
第１図は本発明の一実施例の縦形電界効果トランジスタ
の断面構造図、第２図は本発明の他の実施例の縦形電界
効果トランジスタの製法を示す新面構造図、第３，４図
は本発明の他の実施例を示す縦形電界効果トランジスタ
の断面構造図である。
１・・・高濃度半導体基板、２・・・低濃度ドレイン領
域。
３・・・ベース領域、４・・・ソース領域、５・・・ゲ
ート酸化膜、６・・・ゲート電極、７・・・保護絶Ｒ膜
、８・・ソース電極、９・・・ドレイン電極、１ｏ・・
・イオンビーム、１１・・・ライフタイムキラー、１２
・・・放熱基板、第 ２図
（ｂ）FIG. 1 is a cross-sectional structural diagram of a vertical field effect transistor according to an embodiment of the present invention, FIG. 2 is a new structural diagram showing a manufacturing method of a vertical field effect transistor according to another embodiment of the present invention, and FIGS. 3 and 4 FIG. 2 is a cross-sectional structural diagram of a vertical field effect transistor showing another embodiment of the present invention. 1...High concentration semiconductor substrate, 2...Low concentration drain region. 3... Base region, 4... Source region, 5... Gate oxide film, 6... Gate electrode, 7... Protective isolation film, 8... Source electrode, 9... Drain electrode , 1o...
・Ion beam, 11...Lifetime killer, 12
...Heat dissipation board, Figure 2 (b)
Claims (1)
在する電界効果トランジスタにおいて、該基板の高濃度
不純物領域の厚さが、該基板の表面側に位置する低濃度
不純物領域の厚さよりも小となることを特徴とする縦形
電界効果トランジスタ。 ２、特許請求の範囲第１項において、電界効果トランジ
スタを構成する半導体基板が、それよりも熱伝導率の良
い他の金属基板に接着されていることを特徴とする縦形
電界効果トランジスタ。[Claims] 1. In a field effect transistor in which the main current path exists in the depth direction from the surface of the semiconductor substrate, the thickness of the high concentration impurity region of the substrate is greater than the thickness of the high concentration impurity region located on the surface side of the substrate. A vertical field effect transistor characterized in that the thickness is smaller than the thickness of a concentrated impurity region. 2. A vertical field effect transistor according to claim 1, wherein the semiconductor substrate constituting the field effect transistor is bonded to another metal substrate having a higher thermal conductivity than the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62068814A JPS63236366A (en) | 1987-03-25 | 1987-03-25 | Vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62068814A JPS63236366A (en) | 1987-03-25 | 1987-03-25 | Vertical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63236366A true JPS63236366A (en) | 1988-10-03 |
Family
ID=13384561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62068814A Pending JPS63236366A (en) | 1987-03-25 | 1987-03-25 | Vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63236366A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5032880A (en) * | 1989-05-23 | 1991-07-16 | Kabushiki Kaisha Toshiba | Semiconductor device having an interposing layer between an electrode and a connection electrode |
| JP2000269234A (en) * | 1999-03-15 | 2000-09-29 | Toshiba Corp | Semiconductor device |
-
1987
- 1987-03-25 JP JP62068814A patent/JPS63236366A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5032880A (en) * | 1989-05-23 | 1991-07-16 | Kabushiki Kaisha Toshiba | Semiconductor device having an interposing layer between an electrode and a connection electrode |
| JP2000269234A (en) * | 1999-03-15 | 2000-09-29 | Toshiba Corp | Semiconductor device |
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