CN116613214A - Metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents

Metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDF

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Publication number
CN116613214A
CN116613214A CN202310614740.3A CN202310614740A CN116613214A CN 116613214 A CN116613214 A CN 116613214A CN 202310614740 A CN202310614740 A CN 202310614740A CN 116613214 A CN116613214 A CN 116613214A
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type
region
layer
mosfet
functional layer
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李伟聪
陈钱
陈银
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Shenzhen Vergiga Semiconductor Co Ltd
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Shenzhen Vergiga Semiconductor Co Ltd
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Priority to CN202310614740.3A priority Critical patent/CN116613214A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The application discloses a metal oxide semiconductor field effect transistor and a manufacturing method thereof, wherein the metal oxide semiconductor field effect transistor comprises a semiconductor substrate, a functional layer and a device layer, an N-type drift region is arranged on the semiconductor, and two P-type buried layers which are arranged at intervals are arranged in the N-type drift region; the functional layer is arranged on the N-type drift region and comprises an N-type current expansion region and two P-type base regions arranged on two sides of the N-type current expansion region, a P+ ohmic contact region and an N-type source region which are connected with each other are arranged in the P-type base regions, a polysilicon trench is arranged in the N-type current expansion region, and P+ buried layers are arranged on two sides of the polysilicon trench; the device layer comprises a grid structure and a first metal layer, the grid structure is arranged on the functional layer, the first metal layer covers the grid structure and the functional layer, and the first metal layer is respectively connected with the P+ ohmic contact region, the N-type source region and the polysilicon groove. The scheme can improve the reliability of the metal oxide semiconductor field effect transistor.

Description

Metal oxide semiconductor field effect transistor and manufacturing method thereof
Technical Field
The application relates to the technical field of semiconductors, in particular to a metal oxide semiconductor field effect transistor and a manufacturing method thereof.
Background
With the development of technology, semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have a larger forbidden bandwidth, higher thermal conductivity, higher electron saturation drift velocity and 10 times of critical breakdown electric field than silicon materials, and are widely applied to the technical fields of high temperature, high frequency, high power, radiation resistance and the like.
Silicon carbide (SiC) -Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is used as a switching device, and an anti-parallel freewheeling diode is required to prevent the SiC-MOSFET from being damaged by too high voltage spikes caused by abrupt current changes during switching. Currently, the parasitic body diode of the SiC-MOSFET device itself is generally employed as a flywheel diode.
However, if the parasitic body diode of the SiC-MOSFET device is directly adopted, the turn-on voltage of the parasitic body diode is very high due to the wider forbidden bandwidth of the silicon carbide, which causes additional power loss of the system. In addition, after the parasitic body diode of the self-body diode is started, the SiC-MOSFET device generates larger conduction voltage drop due to the bipolar degradation effect of the SiC material, and the reliability of the SiC-MOSFET device is seriously influenced.
Disclosure of Invention
The application provides a metal oxide semiconductor field effect transistor and a manufacturing method thereof, which can improve the reliability of the metal oxide semiconductor field effect transistor.
In a first aspect, the present application provides a mosfet comprising:
the semiconductor substrate is provided with an N-type drift region, and two P-type buried layers which are arranged at intervals are arranged in the N-type drift region;
the functional layer is arranged on the N-type drift region and comprises an N-type current expansion region and two P-type base regions arranged on two sides of the N-type current expansion region, a P+ ohmic contact region and an N-type source region which are connected with each other are arranged in the P-type base region, a polysilicon groove is arranged in the N-type current expansion region, and P+ buried layers are arranged on two sides of the polysilicon groove;
the device layer comprises a grid structure and a first metal layer, the grid structure is arranged on the functional layer, the first metal layer covers the grid structure and the functional layer, and the first metal layer is respectively connected with the P+ ohmic contact region, the N-type source region and the polysilicon groove.
In the mosfet provided by the application, the P-type buried layer is located at one side of the drift region close to the functional layer, and the orthographic projection of one side of the P-type buried layer on the functional layer is located on the P-type base region or is flush with the boundary between the P-type base region and the N-type current expansion region.
In the mosfet provided by the application, the orthographic projection of the other side of the P-type buried layer on the device layer is located within the orthographic projection of the p+ buried layer on the device layer.
In the metal oxide semiconductor field effect transistor provided by the application, the metal oxide semiconductor field effect transistor further comprises a second metal layer, wherein the second metal layer is positioned on one side of the semiconductor substrate, which is away from the N-type drift region.
In the metal oxide semiconductor field effect transistor provided by the application, the gate structure comprises a gate oxide layer and gate polysilicon which are stacked from bottom to top, and an oxide layer covering the gate oxide layer and the gate polysilicon.
In the metal oxide semiconductor field effect transistor provided by the application, the metal oxide semiconductor field effect transistor has a bilateral symmetry structure.
In the metal oxide semiconductor field effect transistor provided by the application, the material of the semiconductor substrate is silicon carbide.
In the metal oxide semiconductor field effect transistor provided by the application, the distance between the two P+ buried layers is 0.5-4 um.
In the metal oxide semiconductor field effect transistor provided by the application, the distance between the two P-type buried layers is 0.5-4 um.
In a second aspect, the present application provides a method for manufacturing a metal oxide semiconductor field effect transistor, where the metal oxide semiconductor field effect transistor is manufactured by the method for manufacturing a metal oxide semiconductor field effect transistor, and the method for manufacturing a metal oxide semiconductor field effect transistor includes:
providing a semiconductor substrate, and forming an N-type drift region on the semiconductor substrate, wherein two P-type buried layers which are arranged at intervals are arranged in the N-type drift region;
forming a functional layer on the drift region, wherein the functional layer comprises an N-type current expansion region and two P-type base regions arranged on two sides of the N-type current expansion region, a P+ ohmic contact region and an N-type source region which are connected with each other are arranged in the P-type base region, a polysilicon trench is arranged in the N-type current expansion region, and P+ buried layers are arranged on two sides of the polysilicon trench;
and forming a device layer on the functional layer, wherein the device layer comprises a gate structure and a first metal layer, the gate structure is arranged on the functional layer, the first metal layer covers the gate structure and the functional layer, and the first metal layer is respectively connected with the P+ ohmic contact region, the N-type source region and the polysilicon groove.
In summary, the metal oxide semiconductor field effect transistor provided by the application comprises a semiconductor substrate, a functional layer and a device layer, wherein an N-type drift region is arranged on the semiconductor, and two P-type buried layers arranged at intervals are arranged in the N-type drift region; the functional layer is arranged on the N-type drift region and comprises an N-type current expansion region and two P-type base regions arranged on two sides of the N-type current expansion region, a P+ ohmic contact region and an N-type source region which are connected with each other are arranged in the P-type base region, a polysilicon groove is arranged in the N-type current expansion region, and P+ buried layers are arranged on two sides of the polysilicon groove; the device layer comprises a gate structure and a first metal layer, the gate structure is arranged on the functional layer, the first metal layer covers the gate structure and the functional layer, and the first metal layer is respectively connected with the P+ ohmic contact region, the N-type source region and the polysilicon groove. According to the scheme, the polysilicon groove is formed in the JFET region of the metal oxide semiconductor field effect transistor, so that the polysilicon groove and the semiconductor substrate form a heterojunction, and therefore when the metal oxide semiconductor field effect transistor is reversely conducted, the conduction voltage drop is effectively reduced, bipolar degradation of the metal oxide semiconductor field effect transistor is avoided, and further the reliability of the metal oxide semiconductor field effect transistor is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a mosfet according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a current flow when the mosfet is turned on in a reverse direction according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a current flow when the mosfet is turned on in a forward direction according to an embodiment of the present application.
Fig. 4 is a flow chart of a method for manufacturing a mosfet according to an embodiment of the application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Embodiments of the application are described herein with reference to schematic illustrations that are idealized embodiments of the present application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
The semiconductor field vocabulary used in the application is technical vocabulary commonly used by a person skilled in the art, for example, for P-type and N-type impurities, P+ type represents P type with heavy doping concentration, P type represents P type with medium doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.
Silicon carbide (SiC) -Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is used as a switching device, and an anti-parallel freewheeling diode is required to prevent the SiC-MOSFET from being damaged by too high voltage spikes caused by abrupt current changes during switching. Currently, the parasitic body diode of the SiC-MOSFET device itself is generally employed as a flywheel diode.
However, if the parasitic body diode of the SiC-MOSFET device is directly adopted, the turn-on voltage of the parasitic body diode is very high due to the wider forbidden bandwidth of the silicon carbide, which causes additional power loss of the system. In addition, after the parasitic body diode of the self-body diode is started, due to the bipolar degradation effect of the SiC material,
the SiC-MOSFET device generates larger on-voltage drop, and the reliability of the SiC-MOSFET device is seriously affected.
Based on the above, the embodiment of the application provides a metal oxide semiconductor field effect transistor and a manufacturing method thereof. The technical scheme shown in the application will be described in detail through specific examples. The following description of the embodiments is not intended to limit the priority of the embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a mosfet according to the present application. The mosfet may include a semiconductor substrate 11, a functional layer 20, and a device layer 30.
Wherein, the semiconductor substrate 11 is provided with an N-type drift region 12, and two P-type buried layers 121 which are arranged at intervals are arranged in the drift region of the N-type drift region 12;
the functional layer 20 is arranged on the N-type drift region 12, the functional layer 20 comprises an N-type current expansion region 22 and two P-type base regions 21 arranged on two sides of the N-type current expansion region 22, a P+ ohmic contact region 211 and an N-type source region 212 which are mutually connected are arranged in the P-type base region 21, a polysilicon trench 221 is arranged in the N-type current expansion region 22, and P+ buried layers 223 are arranged on two sides of the polysilicon trench 221;
the device layer 30 includes a gate structure 31 and a first metal layer 32, the gate structure 31 is disposed on the functional layer 20, the first metal layer 32 covers the gate structure 31 and the functional layer 20, and the first metal layer 32 is respectively connected to the p+ ohmic contact region 211, the N-type source region 212 and the polysilicon trench 221.
It can be appreciated that since the first metal layer 32 is connected to the two p+ ohmic contact regions 211, respectively. Therefore, the N-type current extension region 22 can be used as a Junction Field-Effect Transistor (JFET) region, and the polysilicon trench 221 and the semiconductor substrate 11 form a heterojunction through the arrangement of the polysilicon trench 221 in the JFET region, so that the PN Junction in the P-type base region 21 is not conducted when the mosfet is conducted reversely, as shown by a line segment "B" in fig. 2, and at this time, current sequentially passes through both sides and bottom of the polysilicon trench 221, the N-type current extension region 22, the N-type drift region 12 and the semiconductor substrate 11, thereby effectively reducing the conduction voltage drop, avoiding bipolar degradation of the mosfet, and further improving the reliability of the mosfet.
In addition, when the mosfet is turned on in the forward direction, the JFET region between the two P-type base regions 21 is set to be the N-type current extension region 22, so that current flows laterally, the current concentration of the JFET region is increased, and the on-resistance of the mosfet can be reduced without reducing the breakdown voltage of the mosfet.
In some embodiments, the semiconductor substrate 11 is an n+ semiconductor substrate 11, and an N-type epitaxial layer is formed on the semiconductor substrate 11, and the N-type drift region 12 and the functional layer 20 are disposed in the N-type epitaxial layer.
The material of the n+ semiconductor substrate 11 may be monocrystalline silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium, the material of the semiconductor substrate 11 may also be silicon germanium, a compound of iii-v element, silicon carbide or a stacked structure thereof, or a silicon-on-insulator structure, or may also be a diamond substrate or other semiconductor material substrate known to those skilled in the art. In the embodiment of the present application, the material of the n+ semiconductor substrate 11 is silicon carbide.
In some embodiments, the mosfet may further include a second metal layer 40. Wherein the second metal layer 40 is located at a side of the semiconductor substrate 11 facing away from the N-type drift region 12.
The gate structure 31 may include a gate oxide layer 313 and a gate polysilicon 312 stacked from bottom to top, and an oxide layer 313 covering the gate oxide layer 313 and the gate polysilicon 312.
In some embodiments, two p+ buried layers 222 and 223 may be disposed at the bottom of the polysilicon trench 221 and on two sides of the polysilicon trench 221, and two P-type buried layers 121 may be disposed at intervals on one side of the drift region near the functional layer 20, so as to increase the flow path of current in the JFET region during forward conduction, and further increase the current concentration of the JFET region.
In order to make the current flow path shown as line "a" in fig. 3, the current flow path in the JFET region is further increased in the forward conduction.
In some embodiments, the P-type buried layer 121 is located on a side of the N-type drift region 12 near the functional layer 20, and an orthographic projection of a side of the P-type buried layer 121 on the functional layer 20 is located on the P-type base region 21 or is flush with an interface between the P-type base region 21 and the N-type current expansion region 22. The orthographic projection of the other side edge of the P-type buried layer 121 on the device layer 30 is located in the orthographic projection of the p+ buried layer 222 on the device layer 30 and the orthographic projection of the p+ buried layer 223 on the device layer 30.
In the embodiment of the present application, the interval between the two p+ buried layers 222 is 0.5um to 4um. The interval between the two P-type buried layers 121 is 0.5um to 4um, the depth of the polysilicon trench 221 is 0.5um to 3um, and the width is 1um to 5um. The current concentration of the N-type current expansion area is 2e16cm -3 ～5e17cm -3 。
It will be appreciated that in the implementation process, the smaller the spacing between the two p+ buried layers 222 and the spacing between the two P-type buried layers 121 may be set as appropriate, so as to increase the flow path of current in the JFET region.
The mosfet has a laterally symmetrical structure.
In summary, the mosfet provided in the embodiments of the present application may include a semiconductor substrate 11, a functional layer 20, and a device layer 30. The semiconductor substrate 11 is provided with an N-type drift region 12, and two P-type buried layers 121 which are arranged at intervals are arranged in the drift region of the N-type drift region 12; the functional layer 20 is arranged on the N-type drift region 12, the functional layer 20 comprises an N-type current expansion region 22 and two P-type base regions 21 arranged on two sides of the N-type current expansion region 22, a P+ ohmic contact region 211 and an N-type source region 212 which are mutually connected are arranged in the P-type base regions 21, a polysilicon trench 221 is arranged in the N-type current expansion region 22, and two P+ buried layers 222 which are arranged at intervals are arranged at the bottom of the polysilicon trench 221; the device layer 30 includes a gate structure 31 and a first metal layer 32, the gate structure 31 is disposed on the functional layer 20, the first metal layer 32 covers the gate structure 31 and the functional layer 20, and the first metal layer 32 is respectively connected to the p+ ohmic contact region 211, the N-type source region 212 and the polysilicon trench 221. According to the scheme, the polysilicon groove 221 can be formed with the semiconductor substrate 11 by arranging the polysilicon groove 221 in the JFET region, so that the conduction voltage drop can be effectively reduced when the metal oxide semiconductor field effect transistor is reversely conducted, the bipolar degradation of the metal oxide semiconductor field effect transistor is avoided, and the reliability of the metal oxide semiconductor field effect transistor is further improved.
In addition, the JFET region between the two P-type base regions 21 is set as the N-type current expansion region 22, so that current can flow transversely during forward conduction, the current concentration of the JFET region is improved, and the on-resistance of the JFET region can be reduced under the condition that the breakdown voltage of the mosfet is not reduced. In addition, the flow path of the current in the JFET region can be further increased by arranging two p+ buried layers 222 at intervals at the bottom of the polysilicon trench 221 and two P-type buried layers 121 at intervals at one side of the drift region close to the functional layer 20, so that the current concentration of the JFET region can be further increased, the on-resistance of the JFET can be reduced under the condition that the breakdown voltage of the mosfet is not reduced, and the reliability of the mosfet can be improved.
The embodiment of the application also provides a manufacturing method of the metal oxide semiconductor field effect transistor, and the metal oxide semiconductor field effect transistor can be formed through the manufacturing method of the metal oxide semiconductor field effect transistor. As shown in fig. 4, the specific flow of the method for manufacturing the mosfet may be as follows:
101. providing a semiconductor substrate, forming an N-type drift region on the semiconductor substrate, and arranging two P-type buried layers at intervals in the N-type drift region.
In some embodiments, the semiconductor substrate 11 is an n+ semiconductor substrate 11, and an N-type epitaxial layer is formed on the semiconductor substrate 11, and the N-type drift region 12 and the functional layer 20 are disposed in the N-type epitaxial layer. In the embodiment of the present application, the material of the n+ semiconductor substrate 11 is silicon carbide.
Specifically, the surface of the N-type epitaxial layer may be subjected to a photolithography process, and then two P-type buried layers 121 disposed at intervals may be formed by high-energy ion implantation.
102. And forming a functional layer on the N-type drift region, wherein the functional layer comprises an N-type current expansion region and two P-type base regions arranged on two sides of the N-type current expansion region, a P+ ohmic contact region and an N-type source region which are mutually connected are arranged in the P-type base regions, a polysilicon groove is arranged in the N-type current expansion region, and two P+ buried layers which are arranged at intervals are arranged at the bottom of the polysilicon groove.
In some embodiments, a trench structure may be etched on the surface of the N-type epitaxial layer using photolithography and etching processes.
Then, two p+ buried layers 222 are formed on the left and right sides of the bottom of the trench structure respectively through photolithography and aluminum ion implantation, and p+ ohmic contact regions 211 are formed on the surface of the N-type epitaxial layer.
Then, forming two P-type base regions 21 on the surface of the N-type epitaxial layer through photoetching and aluminum ion implantation; then, photoetching and nitrogen ion implantation are carried out, and an N-type current expansion region is formed between the two P-type base regions 21; forming an N+ source region connected with the P+ ohmic contact region 211 on the surface of the N-type epitaxial layer through photoetching and nitrogen ion implantation; and then, carrying out high-temperature annealing to activate impurities.
Finally, P-type polysilicon is deposited and an etch back process is performed to leave only the P-type polysilicon within the trench structure, forming polysilicon trench 221.
103. And forming a device layer on the functional layer, wherein the device layer comprises a grid structure and a first metal layer, the grid structure is arranged on the functional layer, the first metal layer covers the grid structure and the functional layer, and the first metal layer is respectively connected with the P+ ohmic contact region, the N-type source region and the polysilicon groove.
In some embodiments, the semiconductor substrate 11 may be thermally oxidized to form the gate oxide 313, then the N-type gate polysilicon 312 is deposited, and the excess gate polysilicon 312 and gate oxide 313 are etched. Thereafter, an oxide layer 313 is deposited and the hole areas are lithographically etched. Finally, aluminum metal is deposited on the front side and lithographically formed to form first metal layer 32, and then back side thinning is performed and second metal layer 40 is deposited.
In summary, the method for manufacturing a mosfet provided in the embodiment of the present application includes providing a semiconductor substrate 11, and forming an N-type drift region 12 on the semiconductor substrate 11, wherein two P-type buried layers 121 are disposed in the drift region of the N-type drift region 12 at intervals; forming a functional layer 20 on the drift region, wherein the functional layer 20 comprises an N-type current expansion region 22 and two P-type base regions 21 arranged on two sides of the N-type current expansion region 22, a P+ ohmic contact region 211 and an N-type source region 212 which are mutually connected are arranged in the P-type base region 21, a polysilicon trench 221 is arranged in the N-type current expansion region 22, and two P+ buried layers 222 which are arranged at intervals are arranged at the bottom of the polysilicon trench 221; a device layer 30 is formed on the functional layer 20, the device layer 30 includes a gate structure 31 and a first metal layer 32, the gate structure 31 is disposed on the functional layer 20, the first metal layer 32 covers the gate structure 31 and the functional layer 20, and the first metal layer 32 is connected to the p+ ohmic contact region 211, the N-type source region 212 and the polysilicon trench 221, respectively.
According to the scheme, the polysilicon groove 221 can be formed with the semiconductor substrate 11 by arranging the polysilicon groove 221 in the JFET region, so that the conduction voltage drop can be effectively reduced when the metal oxide semiconductor field effect transistor is reversely conducted, the bipolar degradation of the metal oxide semiconductor field effect transistor is avoided, and the reliability of the metal oxide semiconductor field effect transistor is further improved.
It should be noted that, the meaning of the noun in this embodiment is the same as that of the above-mentioned mosfet embodiment, and specific implementation details may refer to the description in the above-mentioned mosfet embodiment.
The above description is made in detail on the mosfet and the manufacturing method thereof, and specific examples are applied to the present application to illustrate the principles and embodiments of the present application, and the above examples are only for helping to understand the core idea of the present application; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the ideas of the present application, the present description should not be construed as limiting the present application in summary.

Claims (10)

1. A metal oxide semiconductor field effect transistor, comprising
The semiconductor substrate is provided with an N-type drift region, and two P-type buried layers which are arranged at intervals are arranged in the N-type drift region;
the functional layer is arranged on the N-type drift region and comprises an N-type current expansion region and two P-type base regions arranged on two sides of the N-type current expansion region, a P+ ohmic contact region and an N-type source region which are connected with each other are arranged in the P-type base region, a polysilicon groove is arranged in the N-type current expansion region, and two P+ buried layers arranged at intervals are arranged at the bottom of the polysilicon groove;
the device layer comprises a grid structure and a first metal layer, the grid structure is arranged on the functional layer, the first metal layer covers the grid structure and the functional layer, and the first metal layer is respectively connected with the P+ ohmic contact region, the N-type source region and the polysilicon groove.
2. The mosfet of claim 1 wherein the P-buried layer is located on a side of the drift region adjacent to the functional layer, and an orthographic projection of a side of the P-buried layer on the functional layer is located on the P-base region or is flush with a boundary between the P-base region and the N-type current spreading region.
3. The mosfet of claim 2 wherein an orthographic projection of the other side of the P-buried layer onto the device layer is within an orthographic projection of the p+ buried layer onto the device layer.
4. The mosfet of claim 1, further comprising a second metal layer on a side of the semiconductor substrate facing away from the N-type drift region.
5. The mosfet of claim 1 wherein said gate structure comprises a gate oxide layer and a gate polysilicon layer stacked from bottom to top, and an oxide layer overlying said gate oxide layer and said gate polysilicon layer.
6. The mosfet of any one of claims 1-5 wherein said mosfet is of a bilateral symmetry.
7. The mosfet of any one of claims 1-5 wherein the semiconductor substrate is silicon carbide.
8. The mosfet of any one of claims 1-5 wherein a spacing between two of said p+ buried layers is between 0.5um and 4um.
9. The mosfet of any one of claims 1-5 wherein a spacing between two of said buried P-type layers is between 0.5um and 4um.
10. A method of manufacturing a metal oxide semiconductor field effect transistor according to any one of claims 1 to 9, wherein the metal oxide semiconductor field effect transistor is manufactured by the method of manufacturing a metal oxide semiconductor field effect transistor, the method of manufacturing a metal oxide semiconductor field effect transistor comprising:
providing a semiconductor substrate, and forming an N-type drift region on the semiconductor substrate, wherein two P-type buried layers which are arranged at intervals are arranged in the N-type drift region;
forming a functional layer on the drift region, wherein the functional layer comprises an N-type current expansion region and two P-type base regions arranged on two sides of the N-type current expansion region, a P+ ohmic contact region and an N-type source region which are connected with each other are arranged in the P-type base region, a polysilicon trench is arranged in the N-type current expansion region, and P+ buried layers are arranged on two sides of the polysilicon trench;
and forming a device layer on the functional layer, wherein the device layer comprises a gate structure and a first metal layer, the gate structure is arranged on the functional layer, the first metal layer covers the gate structure and the functional layer, and the first metal layer is respectively connected with the P+ ohmic contact region, the N-type source region and the polysilicon groove.
CN202310614740.3A 2023-05-29 2023-05-29 Metal oxide semiconductor field effect transistor and manufacturing method thereof Pending CN116613214A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117650158A (en) * 2024-01-26 2024-03-05 湖北九峰山实验室 Wide bandgap semiconductor trench MOSFET device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117650158A (en) * 2024-01-26 2024-03-05 湖北九峰山实验室 Wide bandgap semiconductor trench MOSFET device and manufacturing method thereof

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