JPS61215286A - Forming of pattern of semiconductor film - Google Patents

Forming of pattern of semiconductor film

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Publication number
JPS61215286A
JPS61215286A JP5440785A JP5440785A JPS61215286A JP S61215286 A JPS61215286 A JP S61215286A JP 5440785 A JP5440785 A JP 5440785A JP 5440785 A JP5440785 A JP 5440785A JP S61215286 A JPS61215286 A JP S61215286A
Authority
JP
Japan
Prior art keywords
film
substrate
pattern
forming
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5440785A
Other languages
Japanese (ja)
Inventor
Toshio Kobayashi
俊雄 小林
Kazumasa Takagi
高木 一正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5440785A priority Critical patent/JPS61215286A/en
Publication of JPS61215286A publication Critical patent/JPS61215286A/en
Pending legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To enable the accurate deposition of an Si or Ge film to the exposed part of a substrate, by forming a fine pattern of an Si or Ge film accurately to the desired part of a substrate. CONSTITUTION:An SiO2 film 5 is formed on the surface of an Si (100) single crystal substrate 4, and a square opening is opened to the SiO2 film 5 by photolithography or reactive ion-etching process to expose the surface of the Si substrate 4. Si is deposited to the substrate by electron beam evaporation apparatus to form a deposited Si film 6 until the thickness of the deposited film becomes equal to that of the SiO2 film 5. The Si film 6 is formed exclusively between the SiO2 films and there is no generation of polycrystalline Si on the SiO2 film.

Description

【発明の詳細な説明】 〔発明の利用分野〕 不発明は薄膜の形成方法に係り、籍に下地上の所望の所
にSiもしくはGe単結晶ま九は多結晶膜を選択的に蒸
着する方法に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method of forming a thin film, particularly a method of selectively depositing a Si or Ge single crystal or polycrystalline film at a desired location on a substrate. Regarding.

〔発明の背景〕[Background of the invention]

従来、基板の所望の場所に81もしくはQe等の薄!a
t−形成する際には一旦これらの薄膜を形成した後、こ
れを所望の形状に加工するのが一般的でめった。この刀
U工は4膜の上にスピン塗布したホトレジストヲ露光お
よび現像することによって所望の形に加工し、これをマ
スクとして81もしくはGei反応性イオンエツチング
、イオンミリング、ウェットエツチング等の方法で加工
することによってなる。lた、この方法の逆の方法には
リフトオフ法なる方法がある。すなわち、所望の薄膜を
形成する前に上述の万床で基板上にホトレジスト力為ら
なるマスクを形成し、この上に81もしくdGeJll
l−形成する。ついで、ホトレジストを除去すると、ホ
トレジスト上に被着したsiもしくはGemがホトレジ
ストと一緒に除かれ丞板上にはホトレジストの存在しな
かった所に所望の形状のSiもしくは()e膜が形成さ
れる。
Conventionally, a thin film such as 81 or Qe was applied to a desired location on the board. a
When forming T-layers, it is common practice to once form these thin films and then process them into a desired shape, which is rare. This sword U process is processed into the desired shape by exposing and developing the photoresist spin-coated on the 4-layer film, and using this as a mask, processing is performed using methods such as 81 or Gei reactive ion etching, ion milling, wet etching, etc. Become by doing. Additionally, there is a method called a lift-off method which is the opposite of this method. That is, before forming a desired thin film, a mask made of photoresist is formed on the substrate using the above-mentioned method, and a mask of 81 or dGeJll is applied on this mask.
l-form. Then, when the photoresist is removed, the Si or Gem deposited on the photoresist is removed together with the photoresist, and a Si or ()E film with a desired shape is formed on the plate where the photoresist was not present. .

しかしながら、これら従来法ではSiもしくはGe膜を
微細なパターンに加工するには、困−がめった。すなわ
ち、前者の方法ではホトレジストをマスクとして81も
しくはGe!fj!−加工する際にオーバーエッチやア
ンダーエッチという現象が生じるために再現性良くマス
クパターンを81もしくはGegに転写することができ
ず、1μm以下の、141!をゼする微細パターンにS
iもしくはQei加工することはできなかった。ま九、
後者の方法ではSiもしくはGeを蒸着する際の加熱一
度でるる400C以上で安定なホトレジスト膜が存在し
ないため、Slもしくは()e膜のパターン形成は不可
能であった。
However, these conventional methods have been difficult to process Si or Ge films into fine patterns. That is, in the former method, using photoresist as a mask, 81 or Ge! fj! - Due to the phenomenon of over-etching and under-etching occurring during processing, it is not possible to transfer the mask pattern to 81 or Geg with good reproducibility, and 141! S on the fine pattern that zes
i or Qei processing was not possible. Maku,
In the latter method, since there is no photoresist film that is stable at 400 C or higher once heated when depositing Si or Ge, patterning of the Sl or ()e film was impossible.

さらに、基板上にMinx膜のパターンが形成されて2
す、dich膜の存在しない下地の露出した部分にだけ
81もしくは()e膜を正確に形成すること、すなわち
埋め込むことはホトレジストを用いる従来の方法では不
可症でめった。
Furthermore, a pattern of Minx film is formed on the substrate.
However, it is difficult to accurately form (ie, embed) the 81 or ()e film only on the exposed portion of the underlying layer where the dich film is not present, which is difficult to do using the conventional method using photoresist.

以上のように、従来法では下地の所望の場所にSiもし
くはGe膜を選択的に形成する際、特に所望の場所が微
細でるる場合やSiO□膜の間に埋め込む場合に問題が
めった。
As described above, in the conventional method, problems arose when selectively forming a Si or Ge film at a desired location on the base, especially when the desired location was microscopic or embedded between SiO□ films.

〔発明の目的〕[Purpose of the invention]

本発明は上述の問題点を4決するためになされたもので
あり、その目的は下地の所望の部分に正確にSiもしく
はGe膜の微細なパターンを形成すること、さらにSi
ghで覆われていない下地の露出した部分に84もしく
はGe膜を埋めこむことを可能にするSiもしくは()
6の選択的な蒸着法を提供することにある。
The present invention has been made to solve the above-mentioned problems, and its purpose is to form a fine pattern of Si or Ge film accurately on a desired part of the base, and to form a fine pattern of Si or Ge film.
Si or
The purpose of the present invention is to provide six selective deposition methods.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明においてはホトレジ
ストマスクの代わりにSiO冨膜をマスクとして便用し
、す7トオフ法のように、あらかじめ下地上にS+02
膜のパターンを形成しておき、この上にSiもしくはG
e膜を被着せしめた。九九し、通常の方法でSiもしく
はGe膜を被着した4会は率に8!02)5!4上、下
地の露出した部分を問わず、々−に81もしくは()e
膜が蒸着される。
In order to achieve the above object, in the present invention, a SiO rich film is conveniently used as a mask instead of a photoresist mask, and S+02
A film pattern is formed in advance, and Si or G is deposited on top of this.
E-film was applied. However, 4 layers coated with Si or Ge film by the usual method have a rate of 8! 02) 5!
A film is deposited.

この結果、Siftkm解することによって5ift膜
上に被着したSiもしくはGagを一緒に除去しようと
しても、SiもしくはGe膜が均一にSjO*dt−4
ってしまうので、ホトレジストの場合のように容易にS
iOzMk?!解することは不可能である。したがって
、本発明に2いては、SiもしくはGea!の選択的な
蒸着方法を検討してき九結釆明らかになったI X 1
0−”L’orr以上の水Xを含む雰囲気中でSiもし
くは()e膜を蒸着させる方法を適用するものでめる。
As a result, even if we try to remove Si or Gag deposited on the 5ift film by using Siftkm analysis, the Si or Ge film is uniformly SjO*dt-4
Therefore, it is easy to remove S as in the case of photoresist.
iOzMk? ! It is impossible to understand. Therefore, in the present invention, Si or Gea! After studying the selective vapor deposition method of I
This method applies a method of depositing a Si or ()e film in an atmosphere containing water X of 0-''L'orr or more.

この方法によれば、SiもしくはQeが5iChji上
には被層せず1、下地の露出した部分にのみ選択的に4
膜する。この結果、5i02膜はSiもしくはGeによ
って覆われず、容易に俗解除去することができ、下地上
に81もしくはGemの所望のパターンを形成すること
ができる。このとき、5ins膜は膜厚が薄けnばホト
レジストを用いて正確に微細パターンを形成することが
可能なため、81もしくはGe膜の正確な微細パターン
を得ることができる。さらに、この選択蒸着法によれば
、下地上に選択的に着膜させることができるため、露出
した下地の周囲が810.によって囲まれ、深いくぼみ
になっていたとしても、このくぼみを81もしくはGe
によって埋込むことができる。これにより素子間絶縁構
造を形成することができる。
According to this method, Si or Qe is not coated on 5iChji1, but selectively 4 is applied only to the exposed portion of the base.
To form a film. As a result, the 5i02 film is not covered with Si or Ge, and can be easily removed, allowing a desired pattern of 81 or Gem to be formed on the base. At this time, if the 5ins film is thin, it is possible to accurately form a fine pattern using a photoresist, so that an accurate fine pattern of the 81 or Ge film can be obtained. Furthermore, according to this selective vapor deposition method, the film can be selectively deposited on the base, so that the periphery of the exposed base is 810. Even if the hollow is surrounded by 81 or Ge
can be embedded by Thereby, an inter-element insulation structure can be formed.

本発明において、SiもしくはGeとはSi。In the present invention, Si or Ge refers to Si.

()eの他に3iとGeからなる固溶体をも含むもので
ある。ま九、成長させる3iもしくはGe膜は単結晶の
みならず多結晶をも含む。
In addition to ()e, it also includes a solid solution consisting of 3i and Ge. (9) The 3i or Ge film to be grown includes not only single crystal but also polycrystal.

〔発明の実施例〕[Embodiments of the invention]

実施例1 m1図には本発明の1実施例の工程を示す。図に示すよ
うに、3j(100)単結晶基板1の表面に、4&a化
法によって膜厚300AのSin、膜2を形成した後、
ホトリソグラフィ法およびC)(F 3ガスを用いた反
応性イオンエツチング法によりて5i(h#2に最小+
Il+@ 0.5 a mのパターン形成した(a)。
Example 1 Figure m1 shows the steps of one example of the present invention. As shown in the figure, after forming a Sin film 2 with a thickness of 300A on the surface of a 3j (100) single crystal substrate 1 by the 4&a method,
By photolithography method and C) (reactive ion etching method using F3 gas)
A pattern of Il+@0.5 am was formed (a).

ついで電子ビーム蒸着表直に装填し、−旦2 X 10
” Torrまで真空に引いた後、5X10−’gor
rまで水素を導入し、基板温度700CでGe膜の#層
を行なった。この結果、GeはSiの成田した場所にの
み1.2μmの厚さに被着し、810*膜2の上には(
)e膜は形成されなかった(b)。
Then, it was loaded directly onto the electron beam evaporator, and 2 x 10
” After vacuuming to Torr, 5X10-'gor
Hydrogen was introduced up to r, and # layer of Ge film was formed at a substrate temperature of 700C. As a result, Ge was deposited to a thickness of 1.2 μm only where Si was formed, and on 810* film 2 (
) e film was not formed (b).

この結果、Ge膜にはSigh膜をマスクとして最小線
I11! 0.5μmの微細パターンが形成され、さら
に、形成され九Ge膜は基板に対しほぼ垂直に立ち上か
つ次単結晶漠になっていることが明らかになった。次に
5−フッ酸水溶液を用いてSin、を除去することによ
り、Si基板上にGe巣結晶膜の微細なパターンを形成
することができた(C)。
As a result, using the Sigh film as a mask on the Ge film, the minimum line I11! It was revealed that a fine pattern of 0.5 .mu.m was formed, and that the formed 9-Ge film stood up almost perpendicularly to the substrate and was in the form of a single-crystalline haze. Next, by removing Sin using a 5-hydrofluoric acid aqueous solution, a fine pattern of a Ge nest crystal film could be formed on the Si substrate (C).

この結果は水素雰囲気中で蒸着することによってGeR
lXが選択的に被着することに基づいており、これによ
って5ICh膜はGeBI!、に榎われず、容易にフッ
酸水溶液を用いて除去することが可能になった。また%
GeMは基板に垂直に成長することが明らかに瀝り、こ
れによって微細パターンにもかかわらず、膜厚の厚いG
eaにパターンを形成することができた。
This result shows that GeR can be produced by vapor deposition in a hydrogen atmosphere.
It is based on the selective deposition of lX, which allows the 5ICh film to form GeBI! , and can be easily removed using a hydrofluoric acid aqueous solution. Also%
It is clear that GeM grows perpendicularly to the substrate, and this results in a thick G film despite the fine pattern.
A pattern could be formed on ea.

実施例2 実施/IJ 1において、蒸着装置に導入する水素の圧
力fr:1×10−?TOrrからI X 10−’ 
Tortの間で変えて、水素圧力が選択蒸着に与える影
響を検討した。この結果、基板温度が700Cのとき、
()eは水素がI X 10−’ ゛forr以上の圧
力条件でSi基板上に選択的に被層し、水素圧力が小さ
い場合はsho、上にアイランド状にGe多結晶粒が生
成した。本検討ではI X 10−’ Torrを超え
て水素を導入し、Geの電子ビーム蒸着を行なうことは
できなかったが、I X 10−’ Torr以上でも
選択性が帰られるものと予想される。しかし、真空蒸着
の場合実質的な圧力の上限Fi1×101Port程置
と考えられる。
Example 2 Implementation/IJ In 1, the pressure fr of hydrogen introduced into the vapor deposition apparatus: 1×10−? TOrr to I x 10-'
The effect of hydrogen pressure on selective deposition was investigated by changing between Tort and Tort. As a result, when the substrate temperature is 700C,
In ()e, hydrogen was selectively coated on the Si substrate under pressure conditions of I x 10-' forr or higher, and when the hydrogen pressure was low, island-like Ge polycrystalline grains were formed on top. In this study, it was not possible to perform electron beam evaporation of Ge by introducing hydrogen at a pressure exceeding I x 10-' Torr, but it is expected that selectivity would be achieved even at I x 10-' Torr or higher. However, in the case of vacuum evaporation, the practical upper limit of the pressure is considered to be Fi1×101Port.

実施例3 実施例1において、Geの変わりにSiを電子ビーム蒸
着法で被着せしめた。このときの基板温度は1000C
とした。この結果、SiはSi基板の露出し次場所にの
み0.8μmの4さで被着しており、Ge04合と同様
にSiも水素雰囲気中で選択蒸着ができることが明らか
になった。また、6i膜も基板に対してほぼ垂直に立ち
上がった単結晶膜になっていることが明らかになり、S
ijlEノ4ILsAハターンを形成することができた
Example 3 In Example 1, Si was deposited by electron beam evaporation instead of Ge. The substrate temperature at this time is 1000C
And so. As a result, it was found that Si was deposited with a thickness of 0.8 .mu.m only on the exposed portions of the Si substrate, and it was revealed that Si could be selectively deposited in a hydrogen atmosphere in the same manner as Ge04. It was also revealed that the 6i film is a single crystal film that stands up almost perpendicular to the substrate, and the S
It was possible to form an ijlE-4ILsA pattern.

なお、Siの選択蒸着に対しても水素圧力の影響を検討
した結果、はぼGeの場合と同様の条件で選択性が得ら
れることが確i!la!された。
Furthermore, as a result of examining the influence of hydrogen pressure on the selective vapor deposition of Si, it is certain that selectivity can be obtained under the same conditions as in the case of Ge! la! It was done.

実施例4 1Xz図には本発明の他の実施例の工程を示す。Example 4 Figure 1Xz shows the steps of another embodiment of the invention.

実施例1と同様に3i(100)単結晶基板4の狭面に
1.1μmの840*膜を形成した後、ホトリソグラフ
ィ法および反応性イオンエツチング法によってSjOz
Mに正方形の開口部を開け、下地のSi基板4を4出さ
せ念。正方形の一辺の長さは5μm、浅つ九SiO!の
線幅は2μmである(a)。
After forming a 1.1 μm 840* film on the narrow side of a 3i (100) single crystal substrate 4 in the same manner as in Example 1, a SjOz film was formed by photolithography and reactive ion etching.
Make a square opening in M and let the four underlying Si substrates 4 come out. The length of one side of the square is 5 μm, and the shallow depth is 9 SiO! The line width is 2 μm (a).

ついで、電子ビーム蒸着装置によって、水素圧力1 x
 10−56Torr、 4板温度950tll’の条
件で81の蒸4金行なった。第2図(b)はSiを蒸着
させた途中の段階を示す。B+の蒸ノー膜6の膜厚が、
−1iOz5の膜厚と同じになる1、1μmで蒸着を終
了した。この結果、Si属6はSiQ!fi5の中にの
み成長し、5i01膜上にはSi多結晶粒の発生は認め
られなかった(C)。すなわち、SiはSiO2からな
る格子の中に埋め込まれ、この方法はSi索子を5iO
zによって分離絶縁する素子間絶縁を可能にした。
Then, using an electron beam evaporator, a hydrogen pressure of 1 x
81 4-metal evaporation was carried out under the conditions of 10-56 Torr and 4-plate temperature of 950 tll'. FIG. 2(b) shows a stage in the middle of depositing Si. The thickness of the B+ evaporated film 6 is
The vapor deposition was completed at a thickness of 1.1 μm, which is the same as the film thickness of -1iOz5. As a result, Si genus 6 is SiQ! Si polycrystalline grains grew only in fi5, and no Si polycrystalline grains were observed on the 5i01 film (C). That is, Si is embedded in a lattice made of SiO2, and this method
Enables isolation between elements by separating and insulating them by z.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の方法によれば、砿細なパ
ターンを有するSiもしくはGe膜の微細パターンを形
成することができ、さらに、5i02膜によって囲まれ
次領域にSiもしくは(Je膜を選択的に蒸着し、埋め
込むことができる。
As explained above, according to the method of the present invention, it is possible to form a fine pattern of Si or Ge film having a fine pattern, and furthermore, a Si or (Je film) can be formed in the next region surrounded by the 5i02 film. Can be selectively deposited and embedded.

なお、本発明においては、SiとQeからなる固浴体も
5i−Qeと同様の効果を得ることができる。
In addition, in the present invention, a solid bath consisting of Si and Qe can also obtain the same effect as 5i-Qe.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は選択蒸着法によってGeの微細パターンを形成
する工程図、第2図ri選択蒸着法によって8jO!膜
からSi基板の露出した場所にSamを埋込む工程図で
ある。 1.4・・・Si基板、2,5・・・SiO2膜、3・
・・Ge単結晶膜、6・・・S4単結晶膜。 第  l  日
Fig. 1 is a process diagram of forming a fine pattern of Ge by selective vapor deposition, and Fig. 2 is a process diagram of forming a fine pattern of Ge by selective vapor deposition. FIG. 3 is a process diagram of embedding Sam into the exposed area of the Si substrate from the film. 1.4...Si substrate, 2,5...SiO2 film, 3.
...Ge single crystal film, 6...S4 single crystal film. day l

Claims (1)

【特許請求の範囲】 1、一部SiO_2に覆われてなる下地上のSiO_2
の存在しない部分にSi、Ge、SiとGeの固溶体の
中の少なくとも1種を選択的に蒸着させる工程を少なく
とも有することを特徴とする半導体膜のパターン形成方
法。 2、特許請求の範囲第1項において、前記蒸着させる工
程が水素を1×10^−^6Torr以上含む雰囲気で
行なわれることを特徴とする半導体膜のパターン形成方
法。 3、特許請求の範囲第1項または第2項において、前記
下地がSi単結晶であり、該下地上に蒸着した膜が単結
晶であることを特徴とする半導体膜のパターン形成方法
。 4、特許請求の範囲第1項乃至第3項記載のいずれかに
おいて、前記蒸着させる工程が電子ビーム蒸着法によつ
てなされることを特徴とする半導体膜のパターン形成方
法。
[Claims] 1. SiO_2 on a substrate partially covered with SiO_2
1. A method for forming a pattern of a semiconductor film, the method comprising at least the step of selectively depositing at least one of Si, Ge, and a solid solution of Si and Ge on portions where the pattern does not exist. 2. A semiconductor film pattern forming method according to claim 1, wherein the vapor deposition step is performed in an atmosphere containing hydrogen at 1×10^-^6 Torr or more. 3. A method for forming a pattern of a semiconductor film according to claim 1 or 2, wherein the base is a Si single crystal, and the film deposited on the base is a single crystal. 4. A method for forming a pattern of a semiconductor film according to any one of claims 1 to 3, characterized in that the vapor deposition step is performed by an electron beam evaporation method.
JP5440785A 1985-03-20 1985-03-20 Forming of pattern of semiconductor film Pending JPS61215286A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5440785A JPS61215286A (en) 1985-03-20 1985-03-20 Forming of pattern of semiconductor film

Publications (1)

Publication Number Publication Date
JPS61215286A true JPS61215286A (en) 1986-09-25

Family

ID=12969846

Family Applications (1)

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Country Status (1)

Country Link
JP (1) JPS61215286A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011527832A (en) * 2008-07-11 2011-11-04 サンディスク スリーディー,エルエルシー Method for fabricating a non-volatile memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011527832A (en) * 2008-07-11 2011-11-04 サンディスク スリーディー,エルエルシー Method for fabricating a non-volatile memory device

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