JPS61214819A - Digital level detecting circuit - Google Patents

Abstract

PURPOSE:To srovide the response characteristic of prescribed attack response, hold recovery response, or the like to an outputted detection signal by performing the time base processing of an input signal. CONSTITUTION:A divider 13 obtains v/b where (b) is the absolute value of input data and (v) is data of the current detection signal from an output terminal 14. This value v/b is compared with a constant by a comparator 15, and a switch 16 is controlled in accordance with the comparison result. When the switch 16 is connected to the side of a contact 16a, an attack coefficient is read out from a ROM 17 and is multiplied by the input absolute value (b) in a multiplier 19. This multiplication result is added to the detection signal (v) through the switch 16 by an adder 20. When the switch 16 is connected to the side of a contact 16b, a hold recovery coefficient is read out from a ROM 23 is multiplied by the value of b-v, which is operated by an adder 25, in a multiplier 24. This multiplication result is added to the detection signal (v) through the switch 16 by an adder 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for detecting the level of a digital signal such as an output signal of an A/D converter.

[Summary of the invention]

The present invention calculates the ratio between the absolute value of input data and the current value of the detection signal, and compares the ratio with a predetermined value, and stores constants corresponding to the ratio and the comparison result, respectively. A storage means is provided, and the next value of the detection signal is calculated based on the constant read from the storage means, so that the obtained detection signal has a predetermined response characteristic. It is something.

[Conventional technology]

A noise removal device used in a recording/reproducing device or the like compresses a signal during recording and expands it during playback. In a signal companding circuit that compands an input analog signal, the signal companding circuit is controlled in an analog manner depending on the level of the companded output signal.

When the signal companding circuit is constructed from a digital circuit, it is necessary to digitally detect the level of the companded digital signal and digitally control the input signal based on this detected level. As a conventional digital control method, one that performs instantaneous companding is known. Some of these methods instantaneously compand the input signal depending on the output level.

[Problem that the invention seeks to solve]

None of the above-mentioned digital control systems has been designed to have response characteristics like analog control systems.

[Means for solving problems]

In the present invention, means for detecting the absolute value of input data, means for determining the ratio between the absolute value and the current value of the detection signal, means for comparing the ratio with a predetermined value, and the ratio and the A storage means storing constants corresponding to the comparison results of the comparison means, and means read from the storage means and calculating the next value of the detection signal based on the constants are provided.

[Effect]

A predetermined attack response, hold response, and
It is possible to provide response characteristics such as recovery response.

〔Example〕

FIG. 1 shows a first embodiment of the present invention.

The digital level detection circuit according to this embodiment performs predetermined time-base processing on input data so that the output data of the detection signal has a predetermined response characteristic. That is, by providing a predetermined attack response characteristic and hold/recovery response characteristic to changes in input data, a detection signal of an appropriate level suitable for human auditory sense can be obtained.

FIGS. 3A and 3B show the attack response characteristics and hold/recovery response characteristics of the detection circuit.

Figure A shows the attack response characteristic, and when the input level of the detection circuit increases stepwise from a to b, data that increases along a curve V(t) shown by a dotted line is obtained as a detection signal. Note that the above-mentioned human power level refers to the magnitude converted to the level of the input analog signal when the digital signal whose level is detected is A/D converted.

Figure B shows the hold-attack response characteristics. When the input level falls stepwise from a to b, level a is maintained for a certain hold time tII, and then the curve v (shown by the dotted line) Obtain data of a detection signal falling along t).

In this embodiment, the above curve v(t) is expressed as follows.

・For attack response characteristics v(t) = ((b'-a H) (1-exp
(-) ) +a') 1--・------・--
-(11 However, N and T are arbitrary constants.

・For recovery response characteristics - and 2 ■(t) = (b a) e T4 aHowever, t≧
tM ・−・・−・・−１−−−−・−・・・(
2) The recovery response characteristic according to equation (2) has approximately the same shape as the discharge curve of a capacitor.

In the case of hold response characteristic, v(t)=a However, t≦t 1l−−−−−−−
(3) The hold response characteristic is provided to prevent ripples from occurring in the output in response to low frequency input.

Next, attack response characteristics will be explained.

In the above (Equation 11), v(t) when a≠O is v
(t) = b (1-exp (-(t+to))
) '' ----(4) As shown in FIG. 4, in the curve v(t) when a=O, v (t,) = a.

It is equivalent to the curve shown by the dotted line starting at .

Proof〉 If a = v (to), then in equation (4), 1 =
0, 1' (Substituting equation (5) into equation 11, T Proof path. Since it follows from equation (4), it is defined as to. That is, the current detection signal v(t) To is uniquely determined by applying the function f to the ratio of target value S. If this time point is a new time point t=Q and the input data sampling interval is Δτ, then V(Δτ)−v( 0) =b(1-exp((Δr +io)) +znHowever, it is defined as a function g.

The above equation (7) has b and the current detection signal V. , it is shown that the detection signal ν(Δτ) for the next sampling point can be obtained from . Here, if b is a function of t, b in equation (7) is t-
It is appropriate to use b at the time of Δτ, that is, b at the next sampling time.

This equation (7) is the attack response characteristic, and can be determined as an attack coefficient by performing a calculation on the above in advance.

Next, the digital level detection circuit shown in FIG. 1 based on the above principle will be explained.

This circuit calculates the absolute value g of the current input data (in the explanation of the above principle, b at the next sampling time),
Data V of the detection signal for the previous sampling point
(In the explanation of the above principle, the next value on the curve v(t) is calculated from the ratio V/b of the current detection signal to the data V(.)) based on the attack coefficient or hold/recovery coefficient. I have to. The above attack coefficient is all v
/b is calculated in advance and stored in the ROM 17. Further, the hold coefficient is set to "0" and the recovery coefficient is set to a constant rkJ, which are stored in the ROM 23.

In FIG. 1, input data of, for example, 10 bits is applied to an input terminal 11 from, for example, an A/D converter. This input data is converted into data b representing a 9-bit absolute value in the absolute value detection circuit 12 and is added to the division circuit 13. Data V of the current detection signal obtained at the output terminal 14 for the previous sampling time is added to this division circuit 13, and the ratio of v/b is determined here. This v/b indicates the ratio of the current position on the curve v(t) to the final target value. This v/
b is added to the comparator 15 and compared with a constant rlJ to determine whether the curve v(t) is currently rising or falling.

As is clear from FIGS. 3A and 3B, if v(t) is rising, v/b<Q, and if v(t) is falling, v/b≧0. Comparator 15 compares the above v/b with constant 1 and determines whether v(t) increases or
It is determined that the vehicle has descended, and the switch 16 is switched in accordance with this determination.

If v(t) is rising, switch 16 is at contact 16
Closed to side a. In this case, the attack coefficient described above is obtained. The ROM 17 stores attack coefficients for each v/b.

The address generation circuit 18 is a ROM1 for each v/b.
7 read address is generated. Note that this address generation circuit 18 generates ROM1 for a certain range of v/b.
7, one address is read out. This allows the capacity of the ROM 17 to be saved.

If the ROM 17 has attack coefficients for all v/b, the v/b itself may be used as an address, and the address generation circuit 18 can be omitted. The attack coefficient read from the ROM 17 is added to the multiplier 19 and multiplied by the manual absolute value. The attack coefficient is a coefficient that indicates what percentage of the input absolute value should be added to the current detection signal V, and therefore, the output of the multiplier 19 indicates the value that should actually be added to V. This multiplication output is added to V in adder 20 through switch 16. This addition output is output as a detection signal V to the output terminal 14 via the latch circuit 21. Curve V(t
) is rising, the above operation is repeated.

Next, when the comparator 15 determines that v/b≧1, the switch 16 is switched to the contact 16b side by this determination signal, and the hold circuit 22 consisting of a counter or a retriggerable monomulti is operated. . For example, a signal of "0" is output from the hold circuit 22 at the aforementioned hold time t14.The hold coefficient rOJ is read out from the ROM 23 by this signal of "0". Therefore, the output of the multiplier 24 becomes rOJ, and this output rOJ is added to the adder 20 via the switch 16 and added to the detection signal V. This addition output V is applied to the output terminal 14 via the latch circuit 21. Therefore, the detection signal is held at a constant value V during the time t14. When the time 1N has passed, the output of the hold circuit 22 is inverted to "1", and a predetermined recovery coefficient k is thereby read out from the ROM 23. As mentioned above, since the recovery response characteristic substantially matches the discharge curve of the capacitor, the recovery coefficient is constant regardless of the value of v/b.

This coefficient is added to the multiplier 24 and multiplied by the value of b−v calculated by the adder 25. This multiplication output is added to the detection output (2) in the adder 20 via the switch 16. The discharge curve of a capacitor is calculated by multiplying the difference between the current value and the final target value by a constant coefficient k.
It is obtained by repeating the operation of subtracting from . By performing this calculation by the multiplier 24 and adders 25 and 20, a curve v (t) of the detection signal having recovery response characteristics can be obtained.

FIG. 2 shows a second embodiment of the digital level detection circuit, in which the same parts as in FIG. 1 are given the same reference numerals.

The attack response characteristic according to equation (7) mentioned above is b−V (
0) may be obtained. In that case, you can use .

This embodiment uses the above (9) 2, in which the difference b-v obtained from the adder 26 used in the recovery response in FIG. 1 is also used in the attack response, and this b-v and the attack coefficient are is configured to be multiplied by a multiplier 26. This has the advantage that the circuit configuration is simpler than that shown in FIG. 1, and the number of attack coefficients can be reduced.

Next, as an application example of the above-mentioned digital level detection circuit, the fifth section describes the case where it is applied to a digital signal compression device.
This will be explained with figures. The circuit shown in FIG. 5 is the same as the embodiment of the "signal compression device" filed on the same day as the present application.

In FIG. 5, the digital level detection circuit 7 uses the digital level detection circuit shown in FIG. 1 or 2. In FIG. An analog signal SA is input to the input terminal 1, and this signal SA is supplied to the compression circuit 2. This compression circuit 2 has a division type D/A converter 4 inserted into the feedback circuit of the operational amplifier 3 and the operational amplifier 3.
/A converter. This kind of division type D/A
The converter can be used as a digitally controlled attenuator that compresses the analog signal SA to a predetermined size by controlling the multiplication type D/A converter 4 using a digital control signal S, which will be described later. It also has the advantage that the number of bits of the control signal Sc can be reduced.

The analog signal compressed by the compression circuit 2 is supplied to the A/D converter 5, where it is converted into a digital signal S having a predetermined number of bits, and taken out from the output terminal 6. A part of this digital signal S0 is applied to a digital level detection circuit 7 to generate the signal S.

level is detected. The detection circuit 7 outputs a digital control signal S corresponding to the detection level, and the multiplication type D/A converter 4 of the compression circuit 2 is controlled by this control signal SC.

The present invention can also be applied to a "signal processing circuit" filed on the same day.

〔Effect of the invention〕

By subjecting the input signal to time axis processing, the output detection signal can have response characteristics such as a predetermined attack response, hold/recovery response, etc. By applying the present invention to a signal compression device of a noise removal device, control can be performed in accordance with human auditory sense.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
Figure 3 is a block diagram showing a second embodiment of the present invention, Figure 3 is a characteristic diagram for explaining the attack response and hold/recovery response, Figure 4 is a characteristic diagram for explaining the attack response, and Figure 5 is a characteristic diagram for explaining the attack response. The figure is a block diagram when the present invention is applied to a signal compression device. In addition, in the symbols used in the drawings, 12-- −〜−・
Division circuit 14-1-------------------1 output terminal i 5-----------------
−Comparator 17.23−−−−−−−−−・−−−
--It is a ROM.

Claims (1)

[Claims] means for detecting the absolute value of input data; means for determining the ratio between the absolute value and the current value of the detection signal; means for comparing the ratio with a predetermined value; and a comparison result between the ratio and the comparison means. 1. A digital level detection circuit comprising: storage means storing constants corresponding to the respective values; and means for calculating the next value of the detection signal based on the constants read from the storage means.