JP3679310B2 - Compression circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a compression circuit that can be used in a syllable compander provided in a wireless communication device.
[0002]
[Prior art]
Conventional compression circuits are performed by analog signal processing. Specifically, as shown in FIG. 5, an input signal Vin such as an audio signal is supplied to the rectifier 12, and a DC signal corresponding to the level of the input signal Vin is generated in the rectifier 12, and the level of the DC signal is set. The gain of the amplifier 11 is varied proportionally, the input signal Vin is amplified by the amplifier 11, and the amplified output Vout of the amplifier 11 is sent as a compressed output via the buffer 14.
[0003]
Here, the response speed of the rectifier 12 to the speed at which the level of the input signal changes is determined by the capacitance of the capacitor 13 that cooperates with the rectifier 12 and the input impedance of the rectifier 12.
[0004]
For example, at the time of compression processing with a compression ratio of 2, the gain of the amplifier 11 is controlled based on the output of the rectifier 12 so that the relationship between the input signal Vin and the output signal Vout becomes Vout = 0.3162 × √ (Vin). As a result, in the decibel expression, Vout = 0.5 × Vin (dB) and a compression ratio of 2 is obtained.
[0005]
[Problems to be solved by the invention]
However, when the input signal is compressed by the conventional compression circuit as described above, there is a problem that the characteristics change due to variations in electrical characteristics of components such as amplifiers, rectifiers, and shock absorbers, and changes in ambient temperature. there were. Furthermore, there is a problem that the response speed of the signal output from the rectifier changes due to the change in the capacitance of the capacitor.
[0006]
An object of the present invention is to provide a compression circuit in which there is no variation in the electrical characteristics of components and no characteristic change due to a change in ambient temperature.
[0007]
[Means for Solving the Problems]
A compression circuit according to the present invention is a compression circuit for compressing an input signal,
A / D conversion means for A / D converting the input signal;
Absolute value calculating means for obtaining an absolute value of the A / D conversion output;
Level detection means for detecting the maximum value in the absolute value over at least half a period of the input signal obtained by the absolute value calculation means ;
When the maximum value detected by the level detection means and the signal value subjected to attack time processing and release time processing for the maximum value detected immediately before the maximum value are compared, the maximum value is equal to the signal value. Stores the signal value as the maximum value as a new signal value, and when the comparison results are not equal, the polarity of the difference between the maximum value and the signal value is not the same as in the previous comparison result A change value based on the maximum value, the signal value, the attack time, and the release time is obtained, and the signal value is added to the change value and stored as a new signal value. When the polarity of the difference from the signal value is the same as in the previous comparison result, the attack time for adding the signal value to the change value obtained immediately before and storing it as the first maximum value, And lease time processing means,
A compression process based on a compression ratio is performed on the stored first maximum value, and the result of the compression process is multiplied by a value 1 / B (B is a positive number greater than 1). A compression operation is performed by multiplying the result by an A / D converted input signal and multiplying the multiplication result by a value B.
[0008]
According to the compression circuit of the present invention, the maximum value of the input signal for compression is obtained as the absolute value of the input signal, and the maximum value of the absolute value obtained over at least a half cycle of the input signal. Therefore, the storage period of the digitally converted input signal data may be a half-cycle period, and the compression operation is performed based on this maximum value. However, it is sufficient to store the absolute value of the input signal data digitally converted for obtaining the maximum value for a half period of the input signal, and the memory capacity for storage can be reduced.
[0010]
Further, according to the compression circuit according to the present invention, the result of comparing the maximum value detected by the level detection means and the signal value subjected to the attack time processing and the release time processing with respect to the maximum value detected immediately before the maximum value. When the maximum value and the signal value are equal, the signal value is stored as a new signal value as the maximum value, and when the comparison result is not equal, the polarity of the difference between the maximum value and the signal value is When it is not the same as the case of the previous comparison result, the change value based on the maximum value, the signal value, the attack time, and the release time is obtained and the signal value is added to the change value and stored as a new signal value. When the comparison result is not equal and the polarity of the difference between the maximum value and the signal value is the same as in the previous comparison result, the signal value is added to the change value obtained immediately before Because it is stored as the serial first maximum value, a rapid change of the maximum value for the compression action is suppressed become Rukoto, to process the instantaneous change in the input signal in the execution of the compression action is to follow This is the same as the case where the compression circuit is constituted by an analog circuit, while the change in the tracking characteristic caused by the change in the electrical characteristic of the electric circuit component in the case of the analog circuit is eliminated.
[0012]
Furthermore, according to the compression circuit according to the present invention, compression operation scree made to the detected maximum value by Bell detecting means, then it is multiplied by the value 1 / B in the result of the compression processing for the maximum value Since the level is once reduced and then multiplied by the value B, there is no problem even when the compression operation is performed within the limited numerical range.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a compression circuit according to the present invention will be described according to an embodiment.
[0014]
FIG. 1 is a block diagram showing a configuration of a compression circuit according to an embodiment of the present invention.
[0015]
A compression circuit 10 according to an embodiment of the present invention shown in FIG. 1 illustrates a case where the compression ratio is 2.
[0016]
The compression circuit 10 supplies an input signal to the A / D converter 1 to convert it into a digital signal, and the digital signal output from the A / D converter 1 is supplied to a compressor circuit 2 including a digital signal processor or the like. The compressor circuit 2 performs a compression operation, and the digital signal compressed in the compressor circuit 2 is supplied to the D / A converter 3 to be converted into an analog signal and output.
[0017]
The compressor circuit 2 includes an absolute value level detection circuit 20 including an absolute value calculation circuit 21 that calculates an absolute value of an input signal in a predetermined time range, and a level detection circuit 22 that detects the maximum level of the calculated absolute value. The absolute value level detected by the absolute value level detection circuit 20 is processed by the attack time / release time processing circuit 23 and the attack time / release time processing circuit 23 for performing processing based on the attack time or release time. A compression arithmetic processing circuit 24 that performs compression processing by multiplying the signal level by the A / D converted input signal is functionally provided, and the compression arithmetic processing output is sent to the D / A converter 3.
[0018]
The operation of the compression circuit 10 configured as described above will be described based on the flowchart shown in FIG. 2 where the input signal Vin is an audio signal and Vin = A · sin ωt.
[0019]
The relationship between the input signal and the output signal before the compression processing is as shown in FIG. 4A and corresponds to the reference level of the compression circuit.
[0020]
The input signal is converted into a digital signal by the A / D converter 1 (step S1), and the absolute value of the digitally converted input signal is calculated (step S2). Here, the processing in step S 1 corresponds to the processing of the absolute value calculation circuit 21.
[0021]
Following step S2, the absolute value data is stored in the memory of the compressor circuit 2 for a predetermined time. Here, since the lower limit of the frequency required for the input signal (audio signal) is 300 Hz, the input signal level can be detected if there is data for half a cycle (about 1.67 msec). The predetermined time is, for example, 1.86 msec, and is stored in the memory for 1.86 msec (step S3). Subsequent to step S3, the maximum value in the memory is detected every time A / D conversion sampling is performed (step S4).
[0022]
Here, the processing in step S3 and step S4 corresponds to the processing of the level detection circuit 22. By taking the absolute value in this way, the maximum level of the positive and negative amplitudes can be obtained only on the positive side, and in addition, the digitally converted input signal is used to obtain the absolute value and obtain the maximum level. The data storage time is almost half a cycle.
[0023]
Before compressing the input signal, the response speed of the compressor circuit 2 is adjusted so that the process does not follow the instantaneous change of the input signal so that the process substantially has a time constant. To absorb changes. That is, the maximum level detected in step S4 is compared with the attack time stored in step S7 and the detection level after release time processing, and the difference and the direction of change are detected (step S5).
[0024]
As a result of the comparison in step S5, if the maximum level detected in step S4 is higher than the attack level stored in step S7 and the detection level after release time processing, the stored detection level is increased and decreased. If there is no change in the comparison result, the detection level is not increased or decreased, and the detection level value thus obtained is saved for comparison with the maximum data at the next sample. (Steps S6 to S7).
[0025]
Here, the processing of step S5 to step S7 corresponds to the processing of the attack time / release time processing circuit 23.
[0026]
Regarding the constants for increasing and decreasing in step S6, the constant for the direction in which the maximum level decreases is called attack time (attack time), and the constant for the direction in which the maximum level increases is called release time (release time). The standard attack time specified in the ITU-T recommendation is 3 msec, and the standard release time is 13.5 msec, which is set to this value in step S6.
[0027]
Next, attack time and release time processing in the compression circuit 10 will be described in more detail with reference to FIG.
[0028]
A level comparison is made between the maximum level A detected in step S4 and the level A ′ subjected to the attack time and release time processing stored in step S7 (step S5), and (maximum level A−level A ′). It is checked whether or not> 0 (step S61). If it is determined in step S61 that (maximum level A−level A ′)> 0 is not satisfied, it is checked whether (maximum level A−level A ′) <0 (step S62). If it is determined in step S62 that (maximum level A−level A ′) <0, the maximum level A = level A ′, and the level A ′ obtained in the previous process is detected as the detection level after step S62. Used (step S63), step S8 described later is executed.
[0029]
If it is determined in step S61 that (maximum level A−level A ′)> 0, whether or not (maximum level A−level A ′)> 0 has been the same in the previous time after step S61, that is, (maximum level A−level A ′)> (maximum It is checked whether level A = level A ′) or not (step S64). When it is determined in step S64 that the previous state was not the same as before, the increase rate ΔA is obtained by the increase rate ΔA = {(A−A ′) / the number of sampling times reaching the release time} (step S65). (A ′ + ΔA) is calculated (step S66), and A ′ calculated in step S66 is stored as a new detection level (step S7).
[0030]
If it is determined in step S64 that the state is the same as the previous time, step S65 is skipped, then steps S66 and S7 are executed, and the calculated A ′ is stored as a new detection level.
[0031]
If it is determined in step S62 that (maximum level A−level A ′) <0, whether or not (maximum level A−level A ′) <0 is the same as in the previous time following step S62, that is, (maximum level A−level A ′) It is checked whether level A = level A ′) or not (step S67). When it is determined in step S67 that the previous state was not the same, the decrease rate ΔA is obtained by the decrease rate ΔA = {(A′−A) / number of sampling times reaching the attack time} (step S68). (A′−ΔA) is calculated (step S69), and A ′ calculated in step S69 is stored as a new detection level (step S7).
[0032]
When it is determined in step S67 that the same state has been obtained in the previous time, step S68 is skipped and steps S69 and S7 are executed, and the calculated A ′ is stored as a new detection level.
[0033]
Specifically, if A = 100 mV, A ′ = 80 mV in step S61, and A = A ′ in the previous time, A−A ′> 0, so that the same state as in the previous time in step S64. In step S65, an increase rate ΔA = (100 mV−80 mV) / 10 = 2 mV is calculated. Here, the denominator 10 indicates a case where the release time is 13.5 msec by sampling 10 times. Therefore, new A ′ = (old A ′ + ΔA) = 80 mV + 2 mV = 82 mV, and this 82 mV becomes a new detection level and is stored.
[0034]
In execution of the next step S5, A = 100 mV, A ′ = (the above-mentioned new detection level) 82 mV in step S61, and A (100 mV) −A ′ (82 mV)> 0 in the previous time, step S64. In step S65, the new A ′ = (old A ′ + ΔA) = (82 mV + 2 mV) = 84 mV, and this 84 mV becomes a new detection level and is saved. The
[0035]
In the execution of the next step S5, if A = 64 mV, A ′ = (the above-mentioned new detection level) 84 mV in step S62, and A−A ′> 0 in the previous time, A−A ′ <0. Instead of the same state as the previous time, the reduction rate is calculated by the reduction rate ΔA = (84 mV−64 mV) / 2 = 10 mV. Here, the denominator 2 indicates a case where the attack time is 3 msec by sampling twice. Therefore, new A ′ = (old A ′ + ΔA) = (84 mV−10 mV) = 74 mV, and this 74 mV becomes a new detection level and is stored.
[0036]
Next, referring back to FIG. A compression operation is performed to obtain the square level of the detection level used in step S63 or the value of the detection level stored in step S7 (step 8). Here, since the value of the detection level used in step S63 and the level stored in step S7 is A, √A is obtained by the calculation in step S8 and is compressed at the compression ratio of 2. This result is schematically shown in FIG. 4B. In FIG. 4B, the solid line schematically shows the state after the compression processing, and the broken line shows the input signal.
[0037]
As shown in FIG. 4B, the level after the compression processing in step S8 exceeds the input signal level because the magnitude of the signal processed in the compressor circuit 2 composed of a digital signal processor is (−1 to +1). This is because when the square root operation is performed, the value becomes larger than the original numerical value.
[0038]
Subsequent to step S8, a reference level coefficient α for matching the reference level is multiplied (step S9). Here, the reference level is a level at which the input and output of the compressor circuit 20 become equal, and the gain between the input and output signals at this point is 0 dB. By executing step S9, α√A is obtained. The result of execution of step S9 is as shown in FIG. In FIG. 4C, the alternate long and short dash line indicates the signal level compressed in step S8, and the compressed signal level is multiplied by the reference level coefficient α in step S9 to obtain the compressed signal level indicated by the solid line. Become. The intersection of both is the reference level. In FIG.4 (c), the broken line has shown the input signal level.
[0039]
Although the level of the signal to be compressed can be calculated by the processing in step S9, as is apparent from the display of FIG. 4C, the output signal has a gain with respect to the input signal below the reference level. However, the compressor circuit 2 composed of a digital signal processor cannot directly calculate the gain. This is because the magnitude of the signal processed in the compressor circuit 2 is in the range of (−1 to +1). Therefore, subsequent to step S9, the calculation result α√A in step S9 is multiplied by 1 / B so that the gain is less than 1 (step S10). As a result of the execution of step S10, α√A / B. Here, B is a positive number greater than 1.
[0040]
If this state is illustrated, as shown in FIG. 4 (d), the calculation result of step S9 indicated by a one-dot chain line is reduced to 1 / B as indicated by a solid line to lower the level. In FIG.4 (c), the broken line has shown the input signal level. In this case, as a result of 1 / B, a portion having a level higher than the input signal level, that is, a portion having a gain, takes a portion of the input signal level as described later.
[0041]
Subsequent to step S10, the calculation result in step S10 is divided by the detection level A stored in steps S63 and S7 to obtain a coefficient (step S11). As a result of the calculation in step S11, the obtained coefficient is α√A / (A · B) = α / (B√A). Subsequent to step S11, the coefficient obtained in step S11 is multiplied by the A / D converted input signal (step S12). The multiplication result in step S12 is A · sinωt · α / (B√A) = α√A · sinωt / B.
[0042]
Subsequent to step S12, in order to restore the gain once lowered in step S10, the calculation result in step S12 is multiplied by B in step S10 to return to the original signal level (step S13). The calculation result in step S13 is α√A · sin ωt, and the maximum gain due to compression is B times. As a result, as shown in FIG. 4E, an output signal subjected to compression processing indicated by a solid line with respect to an input signal before compression processing indicated by a broken line is obtained. The signal obtained in step S13 is output as an analog signal by the D / A converter 3 (step S14).
[0043]
Here, adopting as the B example ^{2 4} in step S10. If this is done, the maximum gain due to compression will be 16 times, and the gain of the minute signal will drop, but as a result of the actual measurement, the signal that is 16 times the gain (about 10 Hz for the input signal) is weak, In order to prevent S / N deterioration due to compression of noise components, there was no inconvenience even when the gain by compression was set to 16 times.
[0044]
【The invention's effect】
As described above, according to the compression circuit of the present invention, a compression operation can be performed by digital signal processing, and a compression circuit free from variations in electrical characteristics of components and changes in characteristics due to changes in ambient temperature can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a compression circuit according to an embodiment of the present invention.
FIG. 2 is a flowchart for explaining the operation of the compression circuit according to the embodiment of the present invention.
FIG. 3 is a flowchart for explaining attack time and release time processing in the compression circuit according to the embodiment of the present invention;
FIG. 4 is an explanatory diagram for explaining the operation of the compression circuit according to the embodiment of the present invention.
FIG. 5 is a circuit diagram of a conventional compression circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 A / D converter 2 Compressor circuit 3 D / A converter 10 Compression circuit 20 Absolute value level detection circuit 21 Absolute value calculation circuit 22 Level detection circuit 23 Attack time, release time processing circuit 24 Compression arithmetic processing circuit

Claims (1)

A compression circuit for compressing an input signal,
A / D conversion means for A / D converting the input signal;
Absolute value calculating means for obtaining an absolute value of the A / D conversion output;
Level detection means for detecting a maximum value in the absolute value over at least half a period of the input signal obtained by the absolute value calculation means ;
When the maximum value detected by the level detection means and the signal value subjected to attack time processing and release time processing for the maximum value detected immediately before the maximum value are compared, the maximum value is equal to the signal value. Stores the signal value as a new signal value as the maximum value, and when the comparison result is not equal, the polarity of the difference between the maximum value and the signal value is not the same as in the previous comparison result, A change value based on the maximum value, the signal value, the attack time, and the release time is obtained, and the signal value is added to the change value and stored as a new signal value. When the polarity of the difference from the signal value is the same as in the previous comparison result, an attack time for adding the signal value to the change value obtained immediately before and storing it as the first maximum value, And lease time processing means,
A compression process based on a compression ratio is performed on the stored first maximum value, and the result of the compression process is multiplied by a value 1 / B (B is a positive number greater than 1). A compression circuit characterized in that a compression operation is performed by multiplying an A / D converted input signal by a result and multiplying the multiplication result by a value B.

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