JPS61214810A - Current mirror circuit - Google Patents

Abstract

PURPOSE:To shorten the rise time and the fall time of an output waveform to obtain a current mirror circuit superior in quick responsiveness by connecting a constant current source to the input terminal. CONSTITUTION:A constant current source I1 is connected to the collector of an input-side transistor TRQ11. The current of the constant current source I1 is so set that the TR Q11 is not cur off even if an input current IIN is zero. The variation of the collector potential of the TR Q11 is reduced by this setting. Consequently, the rise time and the fall time of the output waveform due to respective base area charging capacities and parasitic capacities of TRs Q11 and Q12 are shortened. Thus, the current mirror circuit superior is quick responsiveness is obtained.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a current mirror circuit.

[Technical background of the invention]

Figure 4 shows “Special Public Service 1973-8008J (Westing)
This figure shows a current mirror circuit described in [House Corporation]. Note that in the following description, elements and their characteristics are represented by the same reference numerals.

The current mirror circuit shown in FIG. 4 consists of two transistors, the first and second transistors Q! , Qs are connected to the first reference potential terminal (voltage V1), and the collector of the first transistor Ql is connected to the first reference potential terminal (voltage V1). A second transistor QU is connected to the pace of Q2, an input terminal IN is provided at the collector of the first transistor Qs, an input current "IN is passed therethrough, and an output terminal OUT is provided at the collector of the second transistor Q8. , here, corresponding to the input electric current, nine output currents I..7 are obtained.

[Problems with background technology]

However, the above configuration has the following problems.

That is, now suppose that an input current IIN% of a loop shape as shown in FIG. Collector potential V of Q1
Consider changes in First, the collector potential V when the transistor Q1 is off, that is, when the input current I4 is 0.

, 2 becomes =v1... (1). Next, when transistor Q1 is on, the
Collector potential V when input current I is zero. , becomes . This situation is also shown in FIG. 5(b). Here, Ill is the pace-emitter reverse saturation current of the transistor Q1. In addition, 7 is given by q: charge element: Boltzmann's constant T: absolute temperature.

According to equations (1) and (2), transistor Qt is turned on,
When off, the collector potential V is ΔV expressed by the following formula (4)
It can be seen that only c changes.

However, in actual transistor circuits, typical examples include the pace region shown by the dotted line connections in Figure 4,
There are charging capacitances Cb1eCb2 and parasitic capacitances C. Therefore, when the transistor Q1 is switched from off to on, the capacitor co is discharged and the capacitors ci and c2 are charged, as shown in FIG. Sometimes, as shown in FIG. 7, the capacitance C0 is charged and the capacitance C1yC! A discharge occurs.

As a result, the collector potential V of the transistor Ql is equal to the input current! , does not immediately follow the changes in , and its short rise time to and fall time tl become non-negligible as shown in FIG. 5(,). Further, as described above, since the collector potential V of the transistor Q1 cannot follow the change in the input current v4, the output current I flows to the collector of the transistor Q2. U? As shown in FIG. 5(d), it is no longer possible to follow the change in the input current IXN.

Note that t6et1 is the time for charging and discharging the capacitance Cb1 ``b2 #CO, so if the drive current at that time is I, generally, ΔQ=ΔVCX C= I t-(5)C= Cb1+
Cb2+Co-(6) holds true. Therefore, the larger the drive current and the smaller ΔVc,
The rise time and fall time tend to be shorter.

[Purpose of the invention]

The present invention was made in order to cope with the above-mentioned circumstances, and an object of the present invention is to provide a current mirror circuit with excellent high-speed response.

[Summary of the invention]

If this invention is explained using the embodiment shown in FIG. 1, for example,
A constant current source 11 is connected to the collector of the transistor Qll on the input side.
By connecting the transistor Q1! so that the transistor Q11 does not cut off even when the input current IXN is O, the transistor Q1! This is to reduce fluctuations in the collector potential of the output waveform and shorten the rise time and fall time of the output waveform.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, 1. Second transistor Qst #
The emitter of Qlx is connected to the first reference potential end (reference voltage Vl
)It is connected to the. The collector of the first transistor Qst is connected to the first transistor Qst. It is connected to the pace of the second transistor Q1te Qtz. The collector of the first transistor Q1t is connected to one end of the constant current source i. The other end of this constant current source I is connected to the second reference potential point (reference voltage Vz
)It is connected to the. Input current I shielding transistor Ql
flows into the collector of the output current I. U'r flows to the collector of transistor Q2.

In the above configuration, at the collector of the transistor Qll,
The input current shown in Figure 5 (,) above has a more linear shape.
If IN is allowed to flow, the collector potential V of the transistor Qll will be as follows.

First, the collector potential V when the input current I4 is O. ,2
becomes . Next, the collector potential V when the input current I4 is ◎. N is as follows.

According to equations (8) and (9), when switching from y to off, the collector potential V of transistor Q11 changes by Δvc' expressed by the following equation.

Here, if the electric construction 1 of the constant current source Il is set so that this equation < 10 and the previous equation (4) hold true, then the first
Fluctuation Δvc in collector potential V of transistor Qll in the figure
' can be made much smaller than the fluctuation Δvc of the collector potential V of the transistor Q1 shown in FIG.

1ΔVc'l(lΔVCI,,-(
By the way, in order for electrical construction 1 to satisfy formula α,
Electrical construction 1 is required to be much larger than current I8. Further, in order to be able to ignore the influence of the current 11 on the output current Iotrt (see FIG. 2), the electrical construction 1 is required to be considerably smaller than the electrical construction ◎. Therefore,
The conditions for current ■1 are as follows.

In < If < IO... (To) For example, Is
e Io + It, respectively, l5=2X10
(A) Io-100 (μA) = t o (A) II =
Io / 100 z 10 (A), Δvc
, Δvc' are calculated as follows. ΔVc = 26.94XVT ΔVc' = 4.615xVte, respectively. Δvc' is suppressed to 1/5.84 of ΔVc.

In this way, as a result of Δvc' becoming smaller, the second
As shown in the figure, it is possible to obtain a current mirror circuit with short rise time to' and fall time 11/ of the output waveform due to the capacitance Cb1 #Cbi co and which has a short response time.

As detailed above, in this embodiment, the transistor Qll
A constant current source 1 is connected to the collector of the transistor Qtt to prevent the transistor Qtt from being cut off even when the input current IIN is O. As a result, transistor Ql
It is possible to reduce the fluctuation Δvc' in the collector potential V of l, and it is possible to shorten the short rise time and fall time caused by the capacitance Cb1°Cb21CO.

In this way, according to this embodiment, a current mirror circuit with excellent high-speed response is obtained, so if this is used as an output circuit of a multiplication circuit, a multiplication output with small second-order distortion can be obtained. There is an effect.

FIG. 3 is a circuit diagram showing a second embodiment of the invention.

In this embodiment, resistors R1□ and R1 are connected between the emitters of transistors Q11 and Q12 and the first reference potential point, respectively.
2 was inserted. And this resistance R11l
The input current depends on the Rtz resistance ratio! IN and output current 1
．． This allows the ratio of U-cho to be determined. According to such a configuration, the ratio of both currents 11wrlaur is 1:
If a value other than 1 is selected, the same effect as in the previous embodiment can be obtained even in such a case.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a current mirror circuit with excellent high-speed response.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of this invention, FIG. 2 is a diagram showing the output waveform of FIG. 1, FIG. 3 is a circuit diagram showing another embodiment of this invention, and FIG. 4 is a circuit diagram showing a conventional current mirror circuit; ゛Figure 5 is a signal waveform diagram to explain the on/off operation in Figure 4; Figures 6 and 7 are to explain the problem in Figure 4. FIG. Qlt * Qtz...transistor, If...constant current source, R1□, R12...resistance. 1st cause Figure 2 tQ'tl' Figure 3 Figure 4

Claims (1)

[Claims] A current mirror circuit characterized by a constant current source connected to the input end.