JPS61212052A - Semiconductor device with beam structure - Google Patents

Semiconductor device with beam structure

Info

Publication number
JPS61212052A
JPS61212052A JP60053627A JP5362785A JPS61212052A JP S61212052 A JPS61212052 A JP S61212052A JP 60053627 A JP60053627 A JP 60053627A JP 5362785 A JP5362785 A JP 5362785A JP S61212052 A JPS61212052 A JP S61212052A
Authority
JP
Japan
Prior art keywords
weight
semiconductor device
beam structure
movable beam
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60053627A
Other languages
Japanese (ja)
Inventor
Shigeo Hoshino
重夫 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP60053627A priority Critical patent/JPS61212052A/en
Publication of JPS61212052A publication Critical patent/JPS61212052A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N39/00Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a semiconductor device with a beam structure, whose natu ral frequency is set, at low cost and with high precision by a method wherein the beam structure is constituted of a movable beam, and a weight provided on the movable beam, and the weight is made of the same material as that of the electrode of the semiconductor device. CONSTITUTION:The movable beam formed by laminating an upper nitride film 19 and a lower nitride film 17 on the upper and lower sides of a high- precision P<+> type polycrystalline Si film 18 in a sandwiched form is provided on the side of the upper surface of an SiO2 film 13. The end part of this movable beam is connected to the gate region 16 of the P-type MOSFET, wherein P<+> type diffusion layers 12a and 12b are used as the source and drain of the MOSFET, through an electrode wiring (such as an Al wiring) 22, and moreover, a weight 40 made of the same material as that of the electrode wiring 22 is provided on the upper surface of the movable beam. By changing the length of the mask to be used for forming the weight forming pattern, when the natural frequency of a beam structure 100 consisting of the movable beam and the weight is ready-conformed to the knocking vibration, the knocking detection can be performed utilizing a resonance phenomenon.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、可動梁の固有振動数を高精度に設定すること
ができる梁構造体を有する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having a beam structure that allows the natural frequency of a movable beam to be set with high precision.

(発明の背景) 従来の梁構造体を有する半導体装置としては、先に本発
明者が特願昭57−154826号で提案した例えば第
6図に示すようなものがある。
(Background of the Invention) As a conventional semiconductor device having a beam structure, there is a device as shown in FIG. 6, which was previously proposed by the present inventor in Japanese Patent Application No. 57-154826.

第6図は、第5図に示す工程で製造した梁構造体を有す
る半導体装置の断面図を示している。
FIG. 6 shows a cross-sectional view of a semiconductor device having a beam structure manufactured by the process shown in FIG.

この梁構造体を有する半導体装置の製造方法を第5A図
(△)〜第5B図(H>に従って説明する。
A method of manufacturing a semiconductor device having this beam structure will be described with reference to FIGS. 5A (Δ) to 5B (H>).

(A>−・・まず、N型3i基板11 ニP−MO3の
ソース、ドレイン用および固定電極用のP中領域12を
形成し、N型3i基板11の表面には熱酸化5IChI
l’13を例えば1ooo人〕厚さニ形成する。
(A>-... First, the N-type 3i substrate 11 is formed with P-middle regions 12 for source, drain, and fixed electrodes of P-MO3, and the surface of the N-type 3i substrate 11 is thermally oxidized with 5IChI.
1'13 is formed to a thickness of, for example, 100 mm.

(B)・・・次に熱酸化5i(h膜13の全面に、例え
ば減圧CVD法によりS!H+(モノシラン)を約62
0℃で熱分解し、例えば1〜3μmの不純物を含まない
ポリシリコン層を形成し、その後フォトエツチングによ
りポリシリコンスペーサ14を形成する。
(B)... Next, about 62% of S!
The polysilicon layer is thermally decomposed at 0 DEG C. to form an impurity-free polysilicon layer having a thickness of, for example, 1 to 3 .mu.m, and then polysilicon spacers 14 are formed by photoetching.

(C)・・・次に全面に、例えば減圧C,V D法によ
り、NH3(7ンーEニア) とsi H2C1,? 
(ジクロールシラン)を約750℃で熱分解し、約50
0人の厚さにナイトライド膜を形成する。そしてナイト
ライド膜の一部をフォトエツチングすることによりポリ
シリコンスペーサ14の酸化を防止する酸化防止膜15
を形成する。
(C)...Next, apply NH3 (7-Enia) and si H2C1, ? to the entire surface by, for example, the reduced pressure C, V D method.
(Dichlorosilane) is thermally decomposed at about 750°C, and about 50%
A nitride film is formed to a thickness of 0. Then, a part of the nitride film is photo-etched to prevent oxidation of the polysilicon spacer 14.
form.

(D>・・・P−MOSのゲート部およびコンタクト部
に相当する熱酸化S! 02膜13の部分をフォトエツ
チングにより除去し、例えば1050℃の酸素雰囲気中
で熱酸化し、ゲート酸化膜16を形成する。その後、必
要に応じてゲート−ソース間に加えるしきい値電圧vT
Hコントロール用のイオン注入をゲート酸化膜16を通
して行なう。
(D>... The portions of the thermally oxidized S!02 film 13 corresponding to the gate and contact portions of the P-MOS are removed by photoetching, and thermally oxidized in an oxygen atmosphere at, for example, 1050° C. to form the gate oxide film 16. Then, if necessary, apply a threshold voltage vT between the gate and source.
Ion implantation for H control is performed through the gate oxide film 16.

(E)・・・次に、熱リン酸(150℃)で酸化防止膜
15を除去した後に、全面に例えば、減圧CVD法によ
り、約300〜500人の厚さの下層ナイトライド膜1
7を形成し、さらにその全面に例えば減圧CVD法によ
り約5000〜10000人の厚さのポリシリコン膜を
形成し、このポリシリコン膜に例えばBBr 3を用い
た不純物拡散法で高濃度のボロンをドープし、高濃度P
+ポリシリコン膜18を形成する。
(E)...Next, after removing the anti-oxidation film 15 with hot phosphoric acid (150°C), the lower layer nitride film 1 with a thickness of about 300 to 500 mm is coated on the entire surface by, for example, low pressure CVD.
A polysilicon film with a thickness of about 5,000 to 10,000 wafers is formed on the entire surface by, for example, a low-pressure CVD method, and a high concentration of boron is added to this polysilicon film by an impurity diffusion method using, for example, BBr3. Doped and high concentration P
+Polysilicon film 18 is formed.

さらに高濃度P+ポリシリコン膜18の全面に例えば減
圧CVD法により下層ナイトライド膜17より厚さが数
十人、厚い上層ティ1−ライド膜19を形成する。
Furthermore, an upper nitride film 19 is formed on the entire surface of the high concentration P+ polysilicon film 18, for example, by low pressure CVD, which is several tens of times thicker than the lower nitride film 17.

(F)・・・次に、CF 4を用いたプラズマエツチン
グにより、片持梁パターン20を形成し、ざらにフォト
エツチングにより電極取出部21に相当する部分の上層
ナイトライド膜19を除去する。
(F)...Next, a cantilever pattern 20 is formed by plasma etching using CF 4 , and the upper layer nitride film 19 corresponding to the electrode extraction portion 21 is roughly removed by photoetching.

(G)・・・次に、フォトエツチングにより、コンタク
ト部30の熱酸化S! 02膜13に孔を開け、全面に
例えば真空蒸着法により1〜1.5μmの厚さのへ!膜
を形成し、さらにフォトエツチングにより不要部分を除
去して電極配線22を形成する。
(G)...Next, the contact portion 30 is thermally oxidized S! by photoetching. A hole is made in the 02 membrane 13, and a hole with a thickness of 1 to 1.5 μm is formed on the entire surface by, for example, a vacuum evaporation method. A film is formed, and unnecessary portions are removed by photoetching to form electrode wiring 22.

(1−1>・・・次に全面に例えば常圧CVD法により
約400’CでS!hLとPH3(ホスフィン)を熱分
解し、例えば厚さ1.2μmのPSG膜を形成し、フォ
トエツチングによって不要部分を除去してポンディング
パッドおよび可動梁領域上以外に保護1123を形成す
る。
(1-1>...Next, S!hL and PH3 (phosphine) are thermally decomposed at about 400'C by atmospheric pressure CVD method to form a PSG film with a thickness of 1.2 μm, for example, on the entire surface, and photo Unwanted portions are removed by etching to form protection 1123 except on the bonding pad and movable beam area.

最後に、強アルカリ水溶液(例えばエチレンジアミン+
ピロカテコール士水の混合液)をエツチング液として全
体をエツチングする。
Finally, add a strong alkaline aqueous solution (e.g. ethylenediamine +
Etch the entire surface using a mixture of pyrocatechol and water as an etching solution.

すると、ポロンの点火されていないポリシリコンスペー
サ14は約50μm/時の速度でエツチングされ、第6
図に示す梁構造体を有する半導体装置が完成する。
Then, the unlit polysilicon spacer 14 of Poron is etched at a rate of about 50 μm/hour, and the sixth
A semiconductor device having the beam structure shown in the figure is completed.

しかしながら、このような従来の梁構造体を有する半導
体装置にあっては、梁構造体である片持梁の固有振動数
fは、その長さをし、厚さをt、梁材の密度をρおよび
ヤング率をEとすると、で決まるため、この片持梁の長
さし、厚さt、梁材の密度ρおよびヤング率Eを正確に
制御することにより、設計値の固有振動数となるように
梁構造体の形成する方法を採用していた。
However, in a semiconductor device having such a conventional beam structure, the natural frequency f of a cantilever beam, which is a beam structure, is determined by its length, t, and density of the beam material. If ρ and Young's modulus are E, then it is determined by A method of forming a beam structure was adopted to achieve this.

このために半導体装置の製造ロッド間で特に片持梁の厚
ざt1ヤング率Eにばらつきが生じ、その結果梁構造体
の固有振動数が製造ロッド間で設計値に対してばらつき
が生じ易く、高精度(例えば±2%〉に固有振動数を設
定した梁構造体を有する半導体装置を安価に製造するこ
とができないという問題がおった。
For this reason, variations occur particularly in the thickness t1 Young's modulus E of the cantilever beam between manufacturing rods of semiconductor devices, and as a result, the natural frequency of the beam structure tends to vary from the design value between manufacturing rods. A problem has arisen in that a semiconductor device having a beam structure whose natural frequency is set to a high precision (for example, ±2%) cannot be manufactured at a low cost.

一方、本出願人は特願昭57−148874@において
、半導体基板上に一端が支持された可動片の先端部に錘
を設け、この錘の重量を変えることにより可動片の固有
振動数(共振周波数)を変更することができる半導体装
置について提案している。
On the other hand, in Japanese Patent Application No. 57-148874@, the present applicant provided a weight at the tip of a movable piece whose one end was supported on a semiconductor substrate, and by changing the weight of this weight, the natural frequency (resonance) of the movable piece was This paper proposes a semiconductor device that can change the frequency.

しかしながら、この場合に錘の重量を任意に変更するこ
とが容易なことではなく、結局上記従来例と同様な問題
があった。
However, in this case, it is not easy to arbitrarily change the weight of the weight, resulting in the same problems as in the conventional example described above.

(発明の目的) 本発明の目的は安価でかつ可動梁の固有振動数を高精度
に設定することができる梁構造体を有する半導体装置を
提供することにある。
(Object of the Invention) An object of the present invention is to provide a semiconductor device having a beam structure that is inexpensive and capable of setting the natural frequency of a movable beam with high precision.

(発明の構成) 本発明は、半導体基板上に少なくとも一端が支持され、
電極と接続されてなる可動梁と、該可動梁上面に設けら
れた錘とからなる梁構造体を有する半導体装置において
; 前記錘を電極と同一材料で形成したことを特徴とするも
のである。
(Structure of the Invention) The present invention provides at least one end supported on a semiconductor substrate,
A semiconductor device having a beam structure consisting of a movable beam connected to an electrode and a weight provided on the upper surface of the movable beam; characterized in that the weight is made of the same material as the electrode.

(実施例の説明) 本発明の実施例を図面に基づいて説明する。第1図には
本発明に係る梁構造体を有する半導体装置の一実施例の
構成が示されており、同図においてN型シリコン基板1
1の表面にはP型不純物をイオン注入等の方法により導
入してなるP型高濃度埋め込み領域12A、12B、1
2Cが形成されている。
(Description of Examples) Examples of the present invention will be described based on the drawings. FIG. 1 shows the configuration of an embodiment of a semiconductor device having a beam structure according to the present invention, in which an N-type silicon substrate 1
P-type high concentration buried regions 12A, 12B, 1 are formed by introducing P-type impurities into the surface of 1 by a method such as ion implantation.
2C is formed.

また、これらの上部にはシリコン基板110表面を高温
酸化してなるS! 02膜13が成長形成されている。
Moreover, on top of these, S! is formed by high-temperature oxidation of the surface of the silicon substrate 110. 02 film 13 is grown and formed.

さらに、S!(h膜13の上面側には、高濃度P÷ポリ
シリコン膜18の上下に、上層ナイトライド膜19およ
び下層ナイトライド膜17をサンドイッチ状に積層して
なる可動梁が設けられている。
Furthermore, S! (On the upper surface side of the h film 13, there is provided a movable beam formed by stacking an upper nitride film 19 and a lower nitride film 17 in a sandwich manner above and below the high concentration P/polysilicon film 18.

この可動梁の端部は電極配線(例えばA6>22を介し
て、P十拡散1i12a、12bをソース。
The end of this movable beam is connected to the source of P1 diffusion 1i12a, 12b via electrode wiring (for example A6>22).

ドレインとするP−MOSFETのゲート領域16へと
接続され、かつ可動梁の上面には電極配線22と同一材
料で形成された錘40が設けられている。そしてシリコ
ン基板11の上部におけるポンディングパッドおよび可
動梁領域上以外の部分は保護膜(例えばPSG膜)23
により覆われている。
A weight 40 connected to the gate region 16 of the P-MOSFET serving as a drain and made of the same material as the electrode wiring 22 is provided on the upper surface of the movable beam. A protective film (for example, a PSG film) 23 is provided on the upper part of the silicon substrate 11 other than on the bonding pad and the movable beam area.
covered by.

次に、この半導体装置の製造工程を第2A図(a )〜
第2B図(f )を参照しながら説明する。
Next, the manufacturing process of this semiconductor device is shown in FIGS.
This will be explained with reference to FIG. 2B (f).

(a)−・・まず第5A図〈A)〜第5B図(F)まで
に示した従来装置と同様の工程を経て第2図(a )に
示す状態を得る。
(a)--First, the state shown in FIG. 2(a) is obtained through the same steps as in the conventional apparatus shown in FIGS. 5A (A) to 5B (F).

(b )・・・次に、フォトエツチングによりコンタク
ト部30のS!(h膜13に孔を開け、全面に例えば真
空蒸着法により約1゜5μmのアルミ膜を形成し、フォ
トエツチングにより不要部分を除去して電極配線22を
形成し、ざらに片持梁パターン20の先端部付近に錘用
アルミパターン25を形成する。
(b)...Next, S! of the contact portion 30 is formed by photo-etching. (H) A hole is made in the film 13, an aluminum film of about 1.5 μm is formed on the entire surface by vacuum evaporation, and unnecessary parts are removed by photoetching to form the electrode wiring 22, and the cantilever pattern 20 is roughly formed. An aluminum pattern 25 for a weight is formed near the tip.

(C)・・・ざらに、これらの全面にネガレジストを塗
布し、必要部分の露光を行ない、レジストパターン31
を形成する。
(C) Roughly apply a negative resist to these entire surfaces, expose the necessary parts, and form the resist pattern 31.
form.

(d )・・・次に、ポジレジストをその全面に塗布し
、第3図に示すように1回目の露光位置32で露光し、
さらにマスクをずらして2回目の露光位置33で露光し
、錘の加重位置34に中心が来るように錘形成パターン
35を形成する。
(d)...Next, a positive resist is applied to the entire surface and exposed at the first exposure position 32 as shown in FIG.
Further, the mask is shifted and exposure is performed at the second exposure position 33 to form a weight forming pattern 35 so that the center is located at the weighted position 34 of the weight.

このとき、露光位置32.33は自由に決められるため
、第3図中に示されている錘形成パターン35の長ざl
はO−lの範囲で自由に変えることができる。
At this time, since the exposure positions 32 and 33 can be determined freely, the length of the weight forming pattern 35 shown in FIG.
can be freely changed within the range of O-l.

(e )・・・この工程ではレジストパターン31゜錘
形成パターン35を使用し、フォトエツチングにより錘
用アルミパターン30の不要部分のアルミを除去し、錘
40を形成する。
(e) In this step, a resist pattern 31° and a weight forming pattern 35 are used, and unnecessary portions of aluminum of the weight aluminum pattern 30 are removed by photoetching to form a weight 40.

(f )・・・次に、全面に例えば、常圧CVD法によ
り約400℃でS! H4とPH3を熱分解し、例えば
厚さ1.2μmのPSGIIiを形成し、フォトエツチ
ングによってポンディングパッドおよび梁構造体のでき
る領域上以外に保護膜23を形成する。
(f)...Next, the entire surface is coated with S! at about 400°C by, for example, atmospheric pressure CVD. H4 and PH3 are thermally decomposed to form PSG IIi with a thickness of, for example, 1.2 .mu.m, and a protective film 23 is formed by photoetching on areas other than the regions where the bonding pads and beam structures will be formed.

最後に、強アルカリ水溶液(例えばエチレンジアミン+
ピロカテコール+水の混合液)をエツチング液として全
体をエツチングする。すると、ボロンの添加されていな
いポリシリコンスペーサ14は約50μm/時の速度で
エツチングされ、第1図に示す梁構造体50を有する半
導体装置が完成する。
Finally, add a strong alkaline aqueous solution (e.g. ethylenediamine +
Etch the entire surface using a mixture of pyrocatechol and water as an etching solution. Then, the polysilicon spacer 14 to which no boron is added is etched at a rate of about 50 μm/hour, and a semiconductor device having the beam structure 50 shown in FIG. 1 is completed.

また、第2B図(d >の工程において、鍾形成パター
ン35を作成するマスクの長さく第3図中の長さりを変
えて多種類作成しておき、最適な長さ芝を有するマスク
を使用すれば、1回の露光で錘形成パターン35を作成
することができる。
In addition, in the process shown in Fig. 2B (d), various lengths of the mask for forming the peg formation pattern 35 in Fig. 3 are changed, and the mask having the optimum length is used. Then, the weight forming pattern 35 can be created with one exposure.

この場合にはレジストはネガレジストでも良い。In this case, the resist may be a negative resist.

次に作用を説明す金。第1図に示すような主として高濃
度P+ポリシリコン膜18からなる片持梁とその先端部
に設けられた錘40とからなる梁構造体100の固有振
動数fは、片持梁の幅をb、長さをし、厚さをt、ヤン
グ率をE、片持梁の質量をm、錘の質量をMとすると次
式で表わされる。
Next, explain the effect of gold. As shown in FIG. 1, the natural frequency f of a beam structure 100 consisting of a cantilever made mainly of a high concentration P+ polysilicon film 18 and a weight 40 provided at its tip is determined by the width of the cantilever. When b is the length, t is the thickness, E is the Young's modulus, m is the mass of the cantilever, and M is the mass of the weight, it is expressed by the following equation.

梁構造体の固有振動数を設計値に合せるために変化させ
た質量である。
This is the mass that is changed to match the natural frequency of the beam structure to the design value.

次に、M=Aりの時の固有振動数を「。とし、ると、f
、/foは、 となる。上式(3)においてA=0.15の時のBとf
 、 7f oとの関係を第4図に示す。
Next, let the natural frequency when M=A be ``.'', then f
, /fo is as follows. In the above formula (3), B and f when A=0.15
, 7f o is shown in FIG.

−例として錘40の幅、厚さ、密度が片持梁の幅、厚さ
、密度と同じ場合を考えると、片持梁の長さを500μ
mとすると鍾40の長ざlは75μmとなり、梁構造体
50の固有振動数を設計値に適合させるために変化させ
るべき質量am/200に相当する錘40の長さの変化
Δlは2,58μmとなる。
- For example, if the width, thickness, and density of the weight 40 are the same as the width, thickness, and density of the cantilever beam, the length of the cantilever beam is 500μ.
m, the length l of the weight 40 is 75 μm, and the change Δl in the length of the weight 40 corresponding to the mass am/200 that should be changed in order to adapt the natural frequency of the beam structure 50 to the design value is 2, It becomes 58 μm.

第2B図(d >に示す工程において錘40の長さlを
±75μm  (B=30)だけ変化させることで、梁
構造体50の固有振動数が設計値から±15%程度ずれ
ても設計値に近付けることができる。
By changing the length l of the weight 40 by ±75 μm (B = 30) in the process shown in Figure 2B (d), the design can be achieved even if the natural frequency of the beam structure 50 deviates by about ±15% from the design value. value can be approximated.

また、標準の錘の質量を変えることにより梁構造体50
の固有振動数の設計値自体を変えることができる。
Also, by changing the mass of the standard weight, the beam structure 50
The design value of the natural frequency itself can be changed.

上記した半導体装置の応用の一例として自動車エンジン
のノッキング検出の場合について述べる。
As an example of the application of the semiconductor device described above, the case of detecting knocking in an automobile engine will be described.

ノッキング発生時にはエンジンから顕著な約7KHzの
振動が発生するが、上記方法で製造した梁構造体の固有
振動数をノッキング撮動に合せておけば、共振現象を利
用してこのノッキング検出を行なうことができる。
When knocking occurs, a noticeable vibration of about 7 KHz is generated from the engine, but if the natural frequency of the beam structure manufactured by the above method is matched to the knocking imaging, this knocking can be detected using the resonance phenomenon. I can do it.

このとき、共振現象を利用してノッキングの検出出力を
取り出すため、梁構造体の固有振動数がノッキング振動
の振動数から10%ずれると、検出出力が極端に小さく
なるために梁構造体の固有振動数を高精度にノッキング
振動数に合せる必要がある。
At this time, since the detection output of knocking is extracted using the resonance phenomenon, if the natural frequency of the beam structure deviates by 10% from the frequency of knocking vibration, the detection output becomes extremely small. It is necessary to match the vibration frequency to the knocking frequency with high precision.

(発明の効果) 以上説明したように本発明では、梁構造体を可動梁と該
可動梁上に設けられた錘で構成し、かつこの錘を半導体
装置の電極と同一材料で形成するように構成したので、
半導体装置の電極形成時に任意面積の錘が同時に作れる
ため、半導体装置の可動梁部の製造条件を緩和でき、そ
れゆえ安価でかつ高精度に固有振動数が設定された梁構
造体を有する半導体装置が得られる。
(Effects of the Invention) As explained above, in the present invention, the beam structure is composed of a movable beam and a weight provided on the movable beam, and the weight is made of the same material as the electrode of the semiconductor device. Since I configured it,
Since a weight of arbitrary area can be created at the same time when forming the electrodes of a semiconductor device, the manufacturing conditions for the movable beam part of the semiconductor device can be relaxed, and therefore the semiconductor device has a beam structure that is inexpensive and whose natural frequency is set with high precision. is obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る梁構造体を有する半導体装置の一
実施例の構成を示す断面図、第2A図。 第2B図は第1図に示した半導体装置の製造工程を示す
図、第3図は第2B図(d >に示す工程を説明するた
めの図、第4図は錘の修正値Bに対する固有振動数の変
化比率f 、 、、’f oの関係の一例を示す図、第
5A図、第5B図は従来の梁構造体を有する半導体装置
の製造工程を示す図、第6図は第5A図、第5B図に示
した製造工程により製造された従来の梁構造体を有する
半導体装置の構成を示す断面図である。 11・・・半導体基板 13・・・S!02膜 17・・・下層ナトライド膜 18・・・高濃度P÷ポリシリコン膜 19・・・上層ティ1−ライド膜 22・・・電極配線 23・・・保護膜 40・・・錘 100・・・梁構造体
FIG. 1 is a cross-sectional view showing the structure of an embodiment of a semiconductor device having a beam structure according to the present invention, and FIG. 2A. 2B is a diagram showing the manufacturing process of the semiconductor device shown in FIG. 1, FIG. 3 is a diagram for explaining the process shown in FIG. 5A and 5B are diagrams showing the manufacturing process of a semiconductor device having a conventional beam structure, and FIG. 5B is a cross-sectional view showing the configuration of a semiconductor device having a conventional beam structure manufactured by the manufacturing process shown in FIG. Lower layer natride film 18...high concentration P÷polysilicon film 19...upper layer T1-ride film 22...electrode wiring 23...protective film 40...weight 100...beam structure

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板上に少なくとも一端が支持され、電極
と接続されてなる可動梁と、該可動梁上面に設けられた
錘とからなる梁構造体を有する半導体装置において; 前記錘を電極と同一材料で形成したことを特徴とする梁
構造体を有する半導体装置。
(1) In a semiconductor device having a beam structure consisting of a movable beam having at least one end supported on a semiconductor substrate and connected to an electrode, and a weight provided on the upper surface of the movable beam; the weight being the same as the electrode. A semiconductor device having a beam structure formed of a material.
JP60053627A 1985-03-18 1985-03-18 Semiconductor device with beam structure Pending JPS61212052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60053627A JPS61212052A (en) 1985-03-18 1985-03-18 Semiconductor device with beam structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60053627A JPS61212052A (en) 1985-03-18 1985-03-18 Semiconductor device with beam structure

Publications (1)

Publication Number Publication Date
JPS61212052A true JPS61212052A (en) 1986-09-20

Family

ID=12948144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60053627A Pending JPS61212052A (en) 1985-03-18 1985-03-18 Semiconductor device with beam structure

Country Status (1)

Country Link
JP (1) JPS61212052A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619050A (en) * 1994-03-07 1997-04-08 Nippondenso Co., Ltd. Semiconductor acceleration sensor with beam structure
US5808331A (en) * 1995-09-05 1998-09-15 Motorola, Inc. Monolithic semiconductor device having a microstructure and a transistor
US5851851A (en) * 1994-03-07 1998-12-22 Nippondenso Co., Ltd. Method for fabricating a semiconductor acceleration sensor
JP2007001004A (en) * 2005-05-27 2007-01-11 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method of it
US8008737B2 (en) 2005-05-27 2011-08-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619050A (en) * 1994-03-07 1997-04-08 Nippondenso Co., Ltd. Semiconductor acceleration sensor with beam structure
US5851851A (en) * 1994-03-07 1998-12-22 Nippondenso Co., Ltd. Method for fabricating a semiconductor acceleration sensor
US5808331A (en) * 1995-09-05 1998-09-15 Motorola, Inc. Monolithic semiconductor device having a microstructure and a transistor
JP2007001004A (en) * 2005-05-27 2007-01-11 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method of it
US8008737B2 (en) 2005-05-27 2011-08-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8455287B2 (en) 2005-05-27 2013-06-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device including microstructure

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