JPS61210725A - Differential pcm coding and decoding circuit for multiplex processing - Google Patents

Abstract

PURPOSE:To select optionally coding decoding processings corresponding to respective channels by providing a delaying circuit to hold a coding/decoding processing designating signal, an uncommon circuit part to process individually the coding and the decoding, a selector, and a coding/decoding common circuit part commonly used to the coding and decoding processings. CONSTITUTION:A processing designating signal is supplied to a delaying circuit 1-1, and sent successively to the next stage delaying circuit for each processing cycle. An uncommon circuit part 2 executes the individual processing of the coding and decoding for the input shown in the figure. The output is respectively fed to a selector 3. The selector 3 selects either of the data of the coding and the decoding corresponding to respective channels by the output of a delaying circuit 1-2. The processed data are commonly processed by a coding/decoding common circuit part 4, and at a RAM 5, the delaying coefficient generated by respective channel processings is held. The output of the circuit part 4 is processed by an uncommon circuit part 6, and the output data coded and decoded by a selector 7 are selected.

Description

[Detailed Description of the Invention] [Summary] In a differential pulse code modulation method such as adaptive differential pulse code modulation (ADPCM) that performs multiplex processing on multiple channels in a time-division manner, a circuit portion common to an encoder and a decoder is used. A multiplexing system that makes it possible to arbitrarily designate processing as an encoder or decoder for any channel in the multiplex process by sharing the input data and inputting an encoding/decoding process designation signal synchronized with the input data. Processing difference P
A CM encoding/decoding circuit is disclosed.

[Industrial application field]

The present invention relates to an adaptive differential pulse code modulation method, which is a field of high-efficiency speech encoding methods, and in particular, to a multiprocessing differential PCM that performs time-division multiplex encoding and decoding processing on two input data. This relates to an encoding/decoding circuit.

[Conventional technology and problems]

In audio signal processing, etc., the ADPCM method, which is capable of highly efficient data compression with a relatively simple configuration, is often used.Also, multi-processing encoding circuits or decoding circuits that support multi-channels are used. It is being

However, in conventional multiprocessing circuits, a processing circuit component that performs encoding and a processing circuit component that performs decoding are provided as completely separate processing circuits. Therefore, in an apparatus that requires both encoding processing and decoding processing, there is a problem that the scale of two circuits or the scale of processing increases.

In addition, a synchronous processing method has been considered in which encoding processing and decoding processing are performed alternately. The problem is that it cannot be dealt with effectively.

[Means for solving problems]

The present invention is configured as shown in FIG. 1 in order to solve the above-mentioned problems and to make it possible to arbitrarily select either encoding processing or decoding processing for each channel.

FIG. 1 shows a schematic configuration of the present invention, and FIG. 2 shows a diagram for explaining data input/output arrangement and encoding/decoding processing designation signals.

In Figure 1, ■-1 to 1-4 are delay circuits for holding the encoding/decoding processing designation signal in synchronization with input data, and 2 is a delay circuit for encoding processing and decoding processing separately. 3 is a first selector that selects either data related to encoding or data related to decoding; 4 is a code composed of a portion shared in encoding processing and decoding processing; encoding/decoding common circuit section, 5
is random access memory (RAM), 6 is encoding/
The decoding non-common circuit section 7 represents a second selector that selects either data related to encoding or data related to decoding.

[Effect]

For example, when the bit width of the code to be encoded is 8 bits, the data input for each channel is arranged as shown in FIG. 2(a). The encoding/decoding process designation signal is
It is given in synchronization with the timing of input data, and when it is at H level, it represents a decoding process designation, and when it is at an L level, it represents an encoding process designation. Therefore, in the example shown in FIG. 2(a), channels chi and channel ch2 are subject to decoding processing, and channel ch3 is subject to encoding processing.

When the input shown in FIG. 2 (a) is given to the circuit shown in FIG. 1, the data output is arranged as follows.

The result will be as shown in Figure 2 (b). Decoded data is output to channel chi and channel ch2,
Data encoded into 4 bits 1 is output to channel ch3.

The processing designation signal is supplied to the delay circuit 1-1 shown in FIG. 1, and is sequentially sent to the secondary stage delay circuit for each processing cycle. The non-common circuit section 2 performs individual encoding and decoding processing for the human power shown in FIG. 2(A). These outputs are respectively given to the selector 3, and the selector 3 selects either data related to encoding or data related to decoding for each channel based on the output of the delay circuit 1-2.

The selected data is commonly processed by the common encoding/decoding circuit unit 4, and the RAM 5 holds delay coefficients generated in each channel process. The output of the encoding/decoding common circuit section 4 is further subjected to post-processing such as output timing synchronization processing by the non-common circuit section 6, and the encoded or decoded output data is selected by the selector 5. Ru.

With the above configuration, it is possible to designate encoding processing or decoding processing using a processing designation signal for each channel, and to perform both processing in a two-time division manner using one circuit. .

〔Example〕

FIG. 3 shows a block diagram of a more detailed embodiment.

In the figure, numerals 1-1 to 1-4 and 3,4°7 correspond to those shown in FIG. 1, 10-1 to 10-4 are delay circuits, 11 is a μ/L conversion section, and 12 An adder, 13 a quantizer, and 14 an inverse quantizer.

15 is a predictor, 16 is an adder, 17 is a RAM,] 8 is a step size update section, 19 is a RAM, and 20 is an L/μ conversion section.

As shown in FIG. 3 as periods P1 to P4, the entire process is divided into four periods for two-time division multiplexing. Data processing stage 1 corresponding to each channel is assigned to each period IS. Inverse quantizer 14 in the common encoding/decoding circuit section 4. Predictor 15
．． Adder 16. Step size update unit 18 and RAM
17.19 is commonly used in encoding processing and decoding processing.

The human data is supplied to the μ/L converter 11 and the delay circuit 10-1 of period P1. The μ/L converter 11 converts the 8-bit PCM code into a 14-bit linear code SL, and the adder 12 subtracts the predicted value SR from this linear code SL. This subtraction information becomes an error signal, which is quantized by a quantizer 13 and
This becomes the bit quantization code I. Then, it is input to the selector 3. Moreover, the input data divided into two is transmitted by delay circuit 10-1 and delay circuit 10-2 on the one hand.

The signal is input to the selector 3 after a two-period delay.

On the other hand, the encoding/decoding process designation signal is also input to the selector 3 after being delayed for 2 periods, and controls the selector 3. When it is "H", it means decoding process designation, so
Select the input data that has undergone a period delay and select “′■,”
When , the encoding process is specified, so the quantization code I
Select.

The signal that has passed through the selector 3 is sent to the step size update unit 1
8, and here the step size Y to be used in the next processing corresponding to the channel is determined. This result is stored in RAM 19.

Furthermore, the dequantizer 14 outputs the reproduced error signal DQ, which is sent to the predictor 15 and also to the adder 16, where the reproduced error signal DQ and the predicted value SE are added. . The addition result is.

5 predictor 15 and L/μ converter 2 as reproduced signal SR.
Sent to 0.

The predictor 15 outputs a predicted value SE in response to the input of the reproduced error signal DQ and the reproduced signal SR, and stores the result in the RAM1.
Store in 7. In the L/μ converter 20, the 16-bit reproduced signal SR is limited to 14 bits, which is the full scale of the μ-law companding law.

Converted to 8-bit PCM code.

In the selector 7, the quantization code I, which is the output of the selector 3, that is, the signal delayed by two periods of the ADPCM code, and the signal SP of the PCM code, which is the output of the /μ converter 20, are converted into the code The selection is made based on the encoding/decoding processing designation signal delayed by four periods. That is, when the processing designation signal is "L", the ADPCM code (I) is selected because it is encoding processing, and the signal is "H".
When , the PCM code (SP
) is selected and output.

Although the present invention has been described above using an example of an ADPCM encoder/decoder, it can be similarly applied to a simple differential PCM system.

〔Effect of the invention〕

As described above, according to the present invention, encoding processing and decoding processing can be realized with one type of processing circuit, and the scale of the entire processing configuration can be reduced. Also,
Encoding or decoding processing can be arbitrarily specified for each channel for input data, and various manual interface designs can be designed depending on the purpose, so versatility is significantly improved.

[Brief explanation of drawings]

FIG. 1 shows a general configuration of the present invention, FIG. 2 is a diagram for explaining data input/output arrangement and encoding/decoding processing designation signals, and FIG. 3 is a block diagram of an embodiment of the present invention. In the figure, -1 to 1-4 are delay circuits, 2 is a non-common circuit section, 3 is a first selector, 4 is an encoding/decoding common circuit section, 5 is a RAM, 6 is a non-common circuit section, 7 represents the second selector. Patent Applicant Fujitsu Co., Ltd. Representative Patent Attorney Hiroshi Mori (1 other person) Kanrankan-＼

Claims (1)

[Scope of Claims] A differential PCM encoding/decoding circuit for multiple processing that performs encoding and decoding using adaptive differential pulse code modulation for data input to a plurality of channels for each channel, comprising: input data; Means (1-1 to 1
-4) and an encoding system configured such that at least a part including an inverse quantizer and a predictor used for encoding and a part including an inverse quantizer and a predictor used for decoding are shared. a common decoding circuit section (4); a first selector (3) that selects data to be input to the common encoding/decoding circuit section based on the encoding/decoding process designation signal; A second selector (7) that makes a selection regarding data processed by the encoding/decoding common circuit unit based on the encoding/decoding processing designation signal. PCM encoding/decoding circuit.