JPS61210654A - Chip tray - Google Patents
Chip trayInfo
- Publication number
- JPS61210654A JPS61210654A JP60050405A JP5040585A JPS61210654A JP S61210654 A JPS61210654 A JP S61210654A JP 60050405 A JP60050405 A JP 60050405A JP 5040585 A JP5040585 A JP 5040585A JP S61210654 A JPS61210654 A JP S61210654A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chip tray
- tray
- chips
- contained
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/67333—Trays for chips
- H01L21/67336—Trays for chips characterized by a material, a roughness, a coating or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体やバブルメモリをチップの状態で収納し
搬送あるいは保管用などとして使用されるチップトレー
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a chip tray that stores semiconductors or bubble memories in the form of chips and is used for transportation or storage.
市販されているチップトレーは、基材としてアルキルベ
ンゼンスルホン酸(ABS)などの樹脂を使用した標準
品が主流である。特殊な用途として、耐薬品性を考慮し
た基材を用いることもあるが、一般のチップの搬送や保
管lこはあまり用いられていない。Most commercially available chip trays are standard products that use a resin such as alkylbenzenesulfonic acid (ABS) as a base material. For special purposes, substrates with chemical resistance in mind may be used, but they are not used much for general chip transportation or storage.
しかし、h、1記A IJ S樹脂製のチップトレーは
、静電気の帯止、が著(7,<、数KVに及ぶ。このた
め、チップトレー(こ収納したチップの配線や層間の絶
縁破壊による不良の原因の一つlこなっていた。However, chip trays made of IJS resin are susceptible to static electricity (7, <, several KV. One of the causes of defects was failure.
かかる帯電防止対策として、カーボンや静電防止剤をA
13S樹脂などの基材ζこ調合したチップトレーが市販
されている。As a countermeasure against static electricity, carbon and antistatic agents are used as A.
Chip trays made of a base material such as 13S resin are commercially available.
しかし、これらの帯電防止チップトレーは、混入された
添加物が表面lこ露出し、添加物自体が収納されたチッ
プに影響を及ぼすおそれがある。例えば、チップ内のA
13配線を腐蝕させることがあり、実用前lこテストや
使用経過lこ伴うテストなどの確認が必要である。また
基材の静電気特性は、チップトレーが射出成形で製作さ
れるため品質制御が困難であり、製品ロフト毎の変動が
生ずる。However, in these antistatic chip trays, the mixed additives are exposed on the surface, and the additives themselves may affect the chips stored therein. For example, A in the chip
13 It may corrode the wiring, so it is necessary to conduct tests before putting it into use and tests over the course of use. Furthermore, since the chip tray is manufactured by injection molding, it is difficult to control the quality of the electrostatic properties of the base material, and variations occur depending on the product loft.
このように、市販のチップトレーは、汎用品であるので
、価格が安く、入手が容易という利点があるが、帯電が
著しいという問題点を有する。しかし、市販の帯電防止
したチップトレーは、帯電防止の利点を有しながら、前
記したようlこそれlこ付随する種々の欠点を合わせ持
っている。As described above, commercially available chip trays have the advantage of being cheap and easy to obtain because they are general-purpose products, but they have the problem of being significantly charged with electricity. However, while commercially available antistatic chip trays have the advantage of antistatic properties, they also have various attendant disadvantages as described above.
本発明の目的は、収納チップlこ悪影響を及ぼさなく、
更(こ良好な導電性を有するチップトレーを提供するこ
(!:Iこある。The purpose of the present invention is to have a storage chip that does not have any adverse effects;
In addition, we would like to provide a chip tray with good electrical conductivity.
本発明の一実施例をこよれば、チップトレーにアルミニ
ウムなどの金属薄膜を塗膜してなるので、市販品のメリ
ットを生かし、収納チップに悪影響を及ぼさないチップ
トレーが得られる。According to one embodiment of the present invention, since the chip tray is coated with a thin film of metal such as aluminum, it is possible to obtain a chip tray that takes advantage of the advantages of a commercially available product and does not adversely affect the stored chips.
以下、本発明の一実施例を図fこより説明する。 An embodiment of the present invention will be described below with reference to FIG.
半導体やバブルメモリなどのチップは、第1図に示すチ
ップトレー1の凹部21こ収納されて各工程fこ送られ
る。チップトレー1の基材としては、従来と同様tこア
ルキルベンゼンスルホン酸(ABS)などの樹脂材より
なる。Chips such as semiconductors and bubble memories are stored in the recess 21 of the chip tray 1 shown in FIG. 1 and sent to each process f. The base material of the chip tray 1 is made of a resin material such as alkylbenzenesulfonic acid (ABS) as in the conventional case.
今、−例として、ウェハダイシングのバブルメモリチッ
プがチップトレー11こ収納され通過する工程の概略l
こついて述べると、第2図に示すようlこ、ウェハダイ
シングされたチップは、トレーlこ収納され、特性選別
、洗浄、外観検査の各工程lこ送られ、その後トレーか
ら取り出されてデバイスキャリアにダイボンディングさ
れる。なお、第2図tこは工程間の移動、工場間の移動
あるいは工程待ちの保管などは示していない。Now, as an example, an outline of the process of wafer dicing in which bubble memory chips are stored and passed through a chip tray 11.
Specifically, as shown in Figure 2, the wafer-diced chips are stored in a tray and sent through the process of characteristic selection, cleaning, and appearance inspection, and then taken out from the tray and placed in a device carrier. is die bonded. Note that FIG. 2 does not show movement between processes, movement between factories, or storage while waiting for a process.
チップトレーへの帯電は、前記した第2図のフローチャ
ートの中で、どこでの帯電が一番多く、どこでチップに
静電破壊などのダメージを与えるかは、必ずしも明らか
ではなく、またそれを究明するのは非常tこ困難である
。しかし、工程内では、導電シート上での作業、イオン
ζこよる静電気中和、接地などを徹底しているのlこも
かかわらず、チップトレーの帯電を完全lこ除去できず
、収納チップに対する静電障害のポテンシャルが最も高
いと考えられ、極端な時には50%以上の不良率ζこな
る。In the flowchart shown in Figure 2 above, it is not always clear where the chip tray is charged the most, and where it causes damage such as electrostatic damage to the chips, and this needs to be investigated. It is extremely difficult to do so. However, despite thorough efforts such as working on a conductive sheet, neutralizing static electricity caused by ions, and grounding during the process, the charge on the chip tray cannot be completely removed, and the static electricity on the stored chips cannot be completely removed. It is thought that the potential for electrical damage is the highest, and in extreme cases the defective rate can be 50% or more.
第3図は層間の絶縁破壊箇所の例を示すバブルメモリチ
ップの概略断面図、第4図はklやAuなどによる配線
間の絶縁破壊箇所を示すバブルメモリチップの配線の概
略平面図である。第3図、第4図1こおいて、3はGG
G基板、4は単結晶磁性膜、5は第1絶縁層、6は第1
層配線、7は第2絶縁層、8は第2層配線、9は第3絶
縁層、1゜は第3層配線を示す。絶縁破壊箇所11は、
第3図及び第4図に示すように、層間の一番薄い箇所及
び配線間隔が最も接近している箇所に発生し易い傾向−
こある。FIG. 3 is a schematic cross-sectional view of a bubble memory chip showing an example of a dielectric breakdown point between layers, and FIG. 4 is a schematic plan view of the wiring of the bubble memory chip showing a dielectric breakdown point between wirings caused by Kl, Au, or the like. Figures 3 and 4 In 1, 3 is GG
G substrate, 4 is a single crystal magnetic film, 5 is a first insulating layer, 6 is a first
7 is a second insulating layer, 8 is a second layer wiring, 9 is a third insulating layer, and 1° is a third layer wiring. The dielectric breakdown point 11 is
As shown in Figures 3 and 4, this tendency tends to occur where the interlayers are thinnest and where the wiring spacing is closest.
There it is.
そこで、第1図に示すチップトレー11こ蒸着あるいは
メッキなどの方法で、A7または8nなどの金属を塗膜
する。Therefore, the chip tray 11 shown in FIG. 1 is coated with a metal such as A7 or 8n by a method such as vapor deposition or plating.
このように、チップトレー11こ金属薄膜を塗膜すると
、チップトレー1の表面の導電特性は向上し、はぼ完全
tこ帯電を防止できる。また添加物などlこよる収納チ
ップの汚染による影響も防止できる。また母体は一般市
販品を用いることができ、コスト、入手の容易さなどの
大きなメリットを有する。In this way, by coating the chip tray 11 with a metal thin film, the conductive properties of the surface of the chip tray 1 are improved, and it is possible to completely prevent electrification. It is also possible to prevent the influence of contamination of the stored chips due to additives and the like. In addition, a general commercially available product can be used as the matrix, which has great advantages such as cost and ease of acquisition.
なお、上記実施例においては、チップトレー自体に適用
した場合について説明したが、チップトレーは、カバー
なしで用いられる場合と、カバー付きで用いられる場合
がある。カバーはチップトレーと同じ材料よりなるので
、前記したことはカバーについても同様なこ吉がいえる
。従って、本発明はチップトレーのみでなく、カバー(
こ適用した場合も含むことはいうまでもない。In the above embodiments, the case where the present invention is applied to the chip tray itself has been described, but the chip tray may be used without a cover or with a cover. Since the cover is made of the same material as the chip tray, the same applies to the cover. Therefore, the present invention applies not only to the chip tray but also to the cover (
Needless to say, this also includes cases where this is applied.
以上の説明から明らかなように、本発明擾こよれば、収
納チップに悪影響を及ぼさないで帯電を防止することが
でき、静電気Iこよる収納チップの絶縁破壊が防止され
る。As is clear from the above description, according to the present invention, charging can be prevented without adversely affecting the stored chip, and dielectric breakdown of the stored chip due to static electricity I can be prevented.
第1図はチップトレーを示し、+a+は正面図、(bl
は・平面図、第2図はチツプトV−を使用するバブルメ
モリ工程の概略フローチャート図、第3図は眉間の絶縁
破壊箇所の例を示すバブルメモリチップの概略断面図、
第4図は配線間の絶縁破壊箇所を示すバブルメモリチッ
プの配線の概略平面図である。
1・・・チップトレー、 2・・・凹部。
第3図
1凸
第4図Figure 1 shows the chip tray, +a+ is a front view, (bl
Figure 2 is a schematic flowchart of the bubble memory process using Chip V-, Figure 3 is a schematic cross-sectional view of the bubble memory chip showing an example of dielectric breakdown between the eyebrows,
FIG. 4 is a schematic plan view of the wiring of the bubble memory chip showing locations of dielectric breakdown between the wirings. 1... Chip tray, 2... Recess. Figure 3: 1 convex Figure 4
Claims (1)
アルミニウムなどの金属薄膜を塗膜したことを特徴とす
るチップトレー。In chip trays that store chips such as semiconductors,
A chip tray characterized by being coated with a thin film of metal such as aluminum.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60050405A JPS61210654A (en) | 1985-03-15 | 1985-03-15 | Chip tray |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60050405A JPS61210654A (en) | 1985-03-15 | 1985-03-15 | Chip tray |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61210654A true JPS61210654A (en) | 1986-09-18 |
Family
ID=12857952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60050405A Pending JPS61210654A (en) | 1985-03-15 | 1985-03-15 | Chip tray |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61210654A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01268041A (en) * | 1988-04-19 | 1989-10-25 | Shimizu Corp | Wafer carrier |
-
1985
- 1985-03-15 JP JP60050405A patent/JPS61210654A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01268041A (en) * | 1988-04-19 | 1989-10-25 | Shimizu Corp | Wafer carrier |
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