JPS61210654A - Chip tray - Google Patents

Abstract

PURPOSE:To obtain more excellent conductivity without adverse effect on contained chips, by applying a thin metal film such as aluminum on a chip tray. CONSTITUTION:Chips such as semiconductor and bubble memories are contained in recess parts 2 in a chip tray 1 and sent to each process. The base material of the chip tray 1 comprises a rsin material such as alkylbenzenesulfonate like the conventional tray. A metal such as Al or Sn is applied on the chip plate 1 by evaporation or plating. When a thin metal film is applied on the chip plate 1 in this way, the conductivity of the surface of the chip tray 1 is improved, and charging can be prevented approximately perfectly. Effefts of contamination of the contained chips due to added materials can be also prevented. Commercially available products can be used for the matrix. Large merits such as low costs and good availability are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a chip tray that stores semiconductors or bubble memories in the form of chips and is used for transportation or storage.

[Background of the invention]

Most commercially available chip trays are standard products that use a resin such as alkylbenzenesulfonic acid (ABS) as a base material. For special purposes, substrates with chemical resistance in mind may be used, but they are not used much for general chip transportation or storage.

However, chip trays made of IJS resin are susceptible to static electricity (7, <, several KV. One of the causes of defects was failure.

As a countermeasure against static electricity, carbon and antistatic agents are used as A.
Chip trays made of a base material such as 13S resin are commercially available.

However, in these antistatic chip trays, the mixed additives are exposed on the surface, and the additives themselves may affect the chips stored therein. For example, A in the chip
13 It may corrode the wiring, so it is necessary to conduct tests before putting it into use and tests over the course of use. Furthermore, since the chip tray is manufactured by injection molding, it is difficult to control the quality of the electrostatic properties of the base material, and variations occur depending on the product loft.

As described above, commercially available chip trays have the advantage of being cheap and easy to obtain because they are general-purpose products, but they have the problem of being significantly charged with electricity. However, while commercially available antistatic chip trays have the advantage of antistatic properties, they also have various attendant disadvantages as described above.

[Purpose of the invention]

The purpose of the present invention is to have a storage chip that does not have any adverse effects;
In addition, we would like to provide a chip tray with good electrical conductivity.

[Summary of the invention]

According to one embodiment of the present invention, since the chip tray is coated with a thin film of metal such as aluminum, it is possible to obtain a chip tray that takes advantage of the advantages of a commercially available product and does not adversely affect the stored chips.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

Chips such as semiconductors and bubble memories are stored in the recess 21 of the chip tray 1 shown in FIG. 1 and sent to each process f. The base material of the chip tray 1 is made of a resin material such as alkylbenzenesulfonic acid (ABS) as in the conventional case.

Now, as an example, an outline of the process of wafer dicing in which bubble memory chips are stored and passed through a chip tray 11.
Specifically, as shown in Figure 2, the wafer-diced chips are stored in a tray and sent through the process of characteristic selection, cleaning, and appearance inspection, and then taken out from the tray and placed in a device carrier. is die bonded. Note that FIG. 2 does not show movement between processes, movement between factories, or storage while waiting for a process.

In the flowchart shown in Figure 2 above, it is not always clear where the chip tray is charged the most, and where it causes damage such as electrostatic damage to the chips, and this needs to be investigated. It is extremely difficult to do so. However, despite thorough efforts such as working on a conductive sheet, neutralizing static electricity caused by ions, and grounding during the process, the charge on the chip tray cannot be completely removed, and the static electricity on the stored chips cannot be completely removed. It is thought that the potential for electrical damage is the highest, and in extreme cases the defective rate can be 50% or more.

FIG. 3 is a schematic cross-sectional view of a bubble memory chip showing an example of a dielectric breakdown point between layers, and FIG. 4 is a schematic plan view of the wiring of the bubble memory chip showing a dielectric breakdown point between wirings caused by Kl, Au, or the like. Figures 3 and 4 In 1, 3 is GG
G substrate, 4 is a single crystal magnetic film, 5 is a first insulating layer, 6 is a first
7 is a second insulating layer, 8 is a second layer wiring, 9 is a third insulating layer, and 1° is a third layer wiring. The dielectric breakdown point 11 is
As shown in Figures 3 and 4, this tendency tends to occur where the interlayers are thinnest and where the wiring spacing is closest.
There it is.

Therefore, the chip tray 11 shown in FIG. 1 is coated with a metal such as A7 or 8n by a method such as vapor deposition or plating.

In this way, by coating the chip tray 11 with a metal thin film, the conductive properties of the surface of the chip tray 1 are improved, and it is possible to completely prevent electrification. It is also possible to prevent the influence of contamination of the stored chips due to additives and the like. In addition, a general commercially available product can be used as the matrix, which has great advantages such as cost and ease of acquisition.

In the above embodiments, the case where the present invention is applied to the chip tray itself has been described, but the chip tray may be used without a cover or with a cover. Since the cover is made of the same material as the chip tray, the same applies to the cover. Therefore, the present invention applies not only to the chip tray but also to the cover (
Needless to say, this also includes cases where this is applied.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, charging can be prevented without adversely affecting the stored chip, and dielectric breakdown of the stored chip due to static electricity I can be prevented.

[Brief explanation of the drawing]

Figure 1 shows the chip tray, +a+ is a front view, (bl
Figure 2 is a schematic flowchart of the bubble memory process using Chip V-, Figure 3 is a schematic cross-sectional view of the bubble memory chip showing an example of dielectric breakdown between the eyebrows,
FIG. 4 is a schematic plan view of the wiring of the bubble memory chip showing locations of dielectric breakdown between the wirings. 1... Chip tray, 2... Recess. Figure 3: 1 convex Figure 4

Claims (1)

[Claims] In chip trays that store chips such as semiconductors,
A chip tray characterized by being coated with a thin film of metal such as aluminum.